Sagar Ghuge [Fri, 24 Jan 2020 06:00:44 +0000 (22:00 -0800)]
intel/genxml: Add patch count threshold field on gen12
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>
Andres Gomez [Mon, 24 Feb 2020 13:52:53 +0000 (15:52 +0200)]
gitlab-ci/traces: Add Vulkan sample entries for POLARIS10
v2:
- Updated commit log.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4103>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4103>
Denys [Tue, 1 Oct 2019 13:24:20 +0000 (14:24 +0100)]
gitlab: add bug report template
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4089>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4089>
Rhys Perry [Wed, 26 Feb 2020 13:35:26 +0000 (13:35 +0000)]
aco: emit IR in IF's merge block instead if the other side ends in a jump
Fixes NIR such as:
if (divergent) {
a = sgpr()
} else {
break;
}
use(a)
Previously we would have emitted:
if (divergent) {
a = sgpr()
}
if (!divergent) {
break;
}
use(a)
But "a" isn't available at it's use. Now we emit:
if (divergent) {
}
if (!divergent) {
break;
}
a = sgpr()
use(a)
pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 1936 -> 1936 (0.00 %)
VGPRS: 1264 -> 1264 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 159408 -> 159152 (-0.16 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 81 -> 81 (0.00 %)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2557
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
Rhys Perry [Fri, 31 Jan 2020 16:39:20 +0000 (16:39 +0000)]
aco: improve check for unreachable loop continue blocks
The old code would have previously caught:
loop {
...
break
}
when it was meant to just catch:
loop {
if (...)
break
else
break
}
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
Rhys Perry [Fri, 31 Jan 2020 16:47:10 +0000 (16:47 +0000)]
aco: skip NIR in unreachable merge blocks
NIR removes most of this but undef instructions for loop header phis can
remain. These were harmless because ACO would DCE them itself.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
Rhys Perry [Fri, 31 Jan 2020 13:56:26 +0000 (13:56 +0000)]
aco: handle when ACO adds new continue edges
Usually a loop ends with a uniform continue. If it doesn't and we end up
adding our own continue edges (because of continue_or_break or divergent
breaks at the end), we have to add extra operands to the loop header phis.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
Rhys Perry [Fri, 31 Jan 2020 12:41:19 +0000 (12:41 +0000)]
aco: handle missing second predecessors at merge block phis
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
Rhys Perry [Fri, 31 Jan 2020 12:40:51 +0000 (12:40 +0000)]
aco: set has_divergent_branch for discards in loops
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
Andres Gomez [Wed, 18 Mar 2020 09:52:53 +0000 (11:52 +0200)]
gitlab-ci: add python3-requests to the test-vk container
After
90a39af5f65 ("ci: Drop the git dependency in tracie"), we have
this error in the radv-polaris10-traces job:
"
...
+ /builds/tanty/mesa/artifacts/tracie/tests/test.sh
tracie_succeeds_if_all_images_match: Fail
Traceback (most recent call last):
File "/tmp/tracie.test.glY0O23HJo/tracie.py", line 6, in <module>
import requests
ModuleNotFoundError: No module named 'requests'
...
"
v2:
- Updated commit log to be more descriptive (Michel).
Fixes: 90a39af5f65 ("ci: Drop the git dependency in tracie")
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4237>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4237>
Samuel Pitoiset [Mon, 23 Mar 2020 11:02:15 +0000 (12:02 +0100)]
radv/llvm: fix subgroup shuffle for chips without bpermute
bpermute only exists on GFX8+ and only with Wave32 on GFX10. Instead
we have to use readlane with a waterfall loop to defeat the LLVM
backend.
This fixes DOOM Eternal which requires subgroup shuffle.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4284>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4284>
Roman Stratiienko [Sun, 22 Mar 2020 21:36:16 +0000 (23:36 +0200)]
panfrost: Align Android makefiles with recent changes
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Roman Stratiienko <roman.stratiienko@nure.ua>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4280>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4280>
Samuel Pitoiset [Fri, 6 Mar 2020 08:48:03 +0000 (09:48 +0100)]
gitlab-ci: add a bunch of new fossils from the Sascha Vulkan demos
The whole fossils-db is only 448KB of data which is pretty small.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4082>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4082>
Samuel Pitoiset [Fri, 6 Mar 2020 07:39:25 +0000 (08:39 +0100)]
gitlab-ci: add a new stage for RADV CI
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4082>
Samuel Pitoiset [Fri, 6 Mar 2020 07:36:14 +0000 (08:36 +0100)]
gitlab-ci: compile fossils with more ASICs
I think we want to cover these 3 generations at the barely minimum.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4082>
Samuel Pitoiset [Fri, 6 Mar 2020 07:29:45 +0000 (08:29 +0100)]
gitlab-ci: compile fossils with both RADV compiler backends (LLVM/ACO)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4082>
Jan Zielinski [Wed, 18 Mar 2020 12:36:53 +0000 (13:36 +0100)]
gallium/gallivm: Remove workaround disabling AVX code for newer CPUs
The change enables using full 256-bit AVX and AVX2 instructions
on newer platforms.
Reviewed-by: Alok Hota <alok.hota@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4225>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4225>
Samuel Pitoiset [Fri, 6 Mar 2020 09:23:41 +0000 (10:23 +0100)]
radv/winsys: spoof some values for num_render_backends in the null winsys
To avoid crashes when RADV_FORCE_FAMILY is set to GFX9+ because
num_render_backends is used to compute binning state.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4282>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4282>
Samuel Pitoiset [Fri, 6 Mar 2020 10:11:04 +0000 (11:11 +0100)]
radv/winsys: fix wrong PCI ID for Vega10 in the null winsys
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4282>
Eric Anholt [Tue, 17 Mar 2020 19:45:46 +0000 (12:45 -0700)]
glsl: Restore the IsES flag on the shader when reading from cache.
I found that when trying to MESA_SHADER_CAPTURE_PATH a trace, I was
getting "GLSL >= 3.00" for the ES shaders I was trying to capture.
Keeping this metadata in the cached shader program lets us capture
correctly.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4219>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4219>
Dave Airlie [Wed, 19 Feb 2020 02:40:50 +0000 (12:40 +1000)]
gallivm: add support for rgtc/latc fetches.
Annoyingly heaven uses rgtc2 snorm but this at least avoids
the function call overheads to the util fetch functions.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3924>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3924>
Dave Airlie [Wed, 19 Feb 2020 00:19:52 +0000 (10:19 +1000)]
gallivm/s3tc: split out dxt5 alpha code
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3924>
Jordan Justen [Fri, 20 Mar 2020 22:10:09 +0000 (15:10 -0700)]
intel: Add TGL PCI ID
Ref: Bspec 44455
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jordan Justen [Fri, 20 Mar 2020 22:08:12 +0000 (15:08 -0700)]
intel: Update TGL PCI strings
Ref: Bspec 44455
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Alyssa Rosenzweig [Sun, 22 Mar 2020 01:19:43 +0000 (21:19 -0400)]
pan/bi: Pack csel4 opcodes
These are pretty straightforward but there's a lot of details to keep
straight. In the IR, we keep a general logical comparator and types
separately; in the hardware, the type gets fused with a (much more)
limited number of comparators. So there's a fair bit of code here to
account for these differences, fusing in the type information, and
changing up argument order as necessary to make it actually correct.
Anything to save a bit!
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Sun, 22 Mar 2020 01:19:14 +0000 (21:19 -0400)]
pan/bi: Default csel to "!= 0" mode
This way we always have regular csel conditions instead of a weird
.always special case for 3-src CSEL mode.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Sun, 22 Mar 2020 00:54:24 +0000 (20:54 -0400)]
pan/bi: Use bi_lookup_immediate when packing
This gets us part of the way there to packing lo/hi separately. A little
more work is needed to do this "properly", but hey.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Sat, 21 Mar 2020 22:42:58 +0000 (18:42 -0400)]
pan/bi: Respect shift when printing immediates
We allow packing multiple immediates in, but we were missing this in the
print.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Sat, 21 Mar 2020 22:13:49 +0000 (18:13 -0400)]
pan/bi: Implement csel fusing
When generating csel instructions, we can peak to see what condition is
being used. If we're using a "nice" condition, we can fuse it in with
the csel itself, ideally letting the condition itself be DCE'd away.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Sat, 21 Mar 2020 22:12:31 +0000 (18:12 -0400)]
pan/bi: Add `soft` NIR->BIR condition translation
We would like to use this routine opportunistically when fusing
conditions into csels and branches, so let's add a mode where we don't
abort.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Sat, 21 Mar 2020 21:41:34 +0000 (17:41 -0400)]
pan/bi: Remove hacks for 1-bit booleans in IR
Now that we lower them away, a bunch of special cases disappear.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Sat, 21 Mar 2020 21:37:47 +0000 (17:37 -0400)]
pan/bi: Lower bool to ints
Currently we lower to int32, but once mediump lands we'll be ready for
that too.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Sat, 21 Mar 2020 19:25:54 +0000 (15:25 -0400)]
pan/bi: Pack LD_ATTR
Also requires the usual R61/62 games.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Fri, 20 Mar 2020 16:39:29 +0000 (12:39 -0400)]
pan/bi: Pack st_vary
This should let varying writes go through finally.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Fri, 20 Mar 2020 16:38:53 +0000 (12:38 -0400)]
pan/bi: Add store_channels property
It can't be inferred from the usual writemask since stores don't write
to a register destination.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Fri, 20 Mar 2020 16:38:08 +0000 (12:38 -0400)]
pan/bi: Generalize data register setting
So we can use it for stores too.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Fri, 20 Mar 2020 16:25:08 +0000 (12:25 -0400)]
pan/bi: Flesh out st_vary IR
We need to make the semantics of BI_VECTOR a bit more precise -
vectorize only the first argument, not all of them. This is enough for
current and future users, as far as I know.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Fri, 20 Mar 2020 16:16:10 +0000 (12:16 -0400)]
pan/bi: Pack ld_var_addr
Choo choo.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Fri, 20 Mar 2020 15:52:43 +0000 (11:52 -0400)]
pan/bi: Pack ld_ubo ops
Routes some infrastructure to do so at least slightly generically but
we'll see.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Fri, 20 Mar 2020 15:52:33 +0000 (11:52 -0400)]
pan/bi: Add bi_load32_components helper
Pattern seems to crop up a lot.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Fri, 20 Mar 2020 15:38:21 +0000 (11:38 -0400)]
pan/bi: Include UBO index for sysval reads
Trivially zero.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Fri, 20 Mar 2020 02:43:06 +0000 (22:43 -0400)]
pan/bi: Index out constants in instructions
We rewrite BIR_INDEX_CONSTANT (and _ZERO) to preassigned constant ports
when assign uniform_const for the bundle. There are a lot of issues
raised here, unfortunately, and the implementation here is woefully
incomplete with a nasty hack for loads... nevertheless, it's somewhere
to start.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Fri, 20 Mar 2020 02:05:24 +0000 (22:05 -0400)]
pan/bi: Document constant related errata(?)
We're not totally sure what's up with this but Connor says if you
violate it Bad Things happen in your shader. I think this might be an
issue affecting early Bifrost (G71, ..?); when we know more we can look
into patching in a fix.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Fri, 20 Mar 2020 01:45:18 +0000 (21:45 -0400)]
pan/bi: Pack a constant quadword
The piping isn't there to make use of it yet, but this stubs out
constant support at the clause level.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Thu, 19 Mar 2020 21:21:49 +0000 (17:21 -0400)]
pan/bi: Add move lowering pass
We need ALU mostly scalarized, but we get vector moves created from
lower_vec_to_mov so let's scalarize that ourselves rather than bother
NIR.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Thu, 19 Mar 2020 21:21:34 +0000 (17:21 -0400)]
pan/bi: Add bi_emit_before helper
For BIR lowering passes.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Alyssa Rosenzweig [Thu, 19 Mar 2020 20:58:48 +0000 (16:58 -0400)]
pan/bi: Implement FMA/MOV without modifiers
We split off MOV from FMOV since the canonical move on Bifrost doesn't
accept modifiers. (We can still do fmov, but with something like add-0.)
This will also make copyprop a little nicer, I think. Anyway, the
non-modifier version we can implement as-is for FMA.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Jonathan Marek [Sun, 15 Mar 2020 22:53:36 +0000 (18:53 -0400)]
etnaviv: nir: add compile_check_limits
To match TGSI compiler behaviour in glmark terrain scene for example.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4199>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4199>
Marek Olšák [Fri, 20 Mar 2020 20:35:45 +0000 (16:35 -0400)]
ac: fix fast division
This stopped working with LLVM 11 and might occasionally have been broken
on older LLVM, because the metadata was set on the mul, not on the rcp.
Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4268>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4268>
Eduardo Lima Mitev [Fri, 20 Mar 2020 08:32:03 +0000 (09:32 +0100)]
turnip: Instance can be NULL resolving 'GetInstanceProcAddr' entry point
Using turnip driver without a vulkan loader is currently broken because
the entry point resolver is expecting a valid instance when resolving
'vkGetInstanceProcAddr' through vk_icdGetInstanceProcAddr().
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4257>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4257>
Marek Olšák [Wed, 11 Mar 2020 21:19:10 +0000 (17:19 -0400)]
vbo,gallium: make glBegin/End buffer size configurable by drivers
The default is 512 KB, but radeonsi wants 4 MB.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4154>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4154>
Marek Olšák [Tue, 10 Mar 2020 00:33:06 +0000 (20:33 -0400)]
glthread: remove the marshal_fail XML attribute
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
Marek Olšák [Mon, 9 Mar 2020 02:50:16 +0000 (22:50 -0400)]
glthread: ignore vertex arrays with user pointers if they're disabled
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
Marek Olšák [Wed, 4 Mar 2020 19:49:09 +0000 (14:49 -0500)]
glthread: track which vertex array attribs are enabled
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
Marek Olšák [Fri, 6 Mar 2020 21:53:54 +0000 (16:53 -0500)]
glthread: rename non_vbo helper functions
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
Marek Olšák [Wed, 4 Mar 2020 21:18:28 +0000 (16:18 -0500)]
glthread: handle buffer unbinding via glDeleteBuffers
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
Marek Olšák [Fri, 6 Mar 2020 19:54:50 +0000 (14:54 -0500)]
mesa: put gl_thread_state inside gl_context to remove pointer indirection
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
Marek Olšák [Fri, 6 Mar 2020 19:33:20 +0000 (14:33 -0500)]
glthread: rename marshal.h/c to glthread_marshal.h and glthread_shaderobj.c
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
Marek Olšák [Fri, 6 Mar 2020 19:22:58 +0000 (14:22 -0500)]
glthread: move buffer functions into glthread_bufferobj.c
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
Marek Olšák [Thu, 19 Mar 2020 05:56:57 +0000 (01:56 -0400)]
glthread: autogenerate prototypes for custom-marshalled functions
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
Marek Olšák [Fri, 6 Mar 2020 19:35:02 +0000 (14:35 -0500)]
glthread: simplify printing safe_mul in gl_marshal.py
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
Marek Olšák [Fri, 6 Mar 2020 19:20:05 +0000 (14:20 -0500)]
glthread: remove _mesa_post_marshal_hook, because it's not very useful
and also remove the useless forward declaration of enum marshal_dispatch_cmd_id.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
Jason Ekstrand [Wed, 18 Mar 2020 16:48:47 +0000 (11:48 -0500)]
util/sparse_array: Stash the node level in the node pointer
This reworks the data structure a bit and, in my view, simplifies it.
Instead of each node having a header which has the node level in it, we
use the bottom 6 bits of the pointer for that. This requires us to
allocate with the os_malloc/free_aligned helpers (which call into
posix_memalign on Linux) but cache-line aligning our allocations is
actually probably a good thing given that we're doing atomics on them.
The primary advantages to doing this is that it changes the number of
memory accesses per tree level from 2 to 1 when walking the tree because
we no longer have to look at node->level.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4228>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4228>
Jason Ekstrand [Thu, 19 Mar 2020 17:50:33 +0000 (12:50 -0500)]
meson,ci: Disable sparse_array tests on windows
As soon as I switch to using the allocation helpers in os_memory.h,
these tests start blowing up on the Windows build in GitLab CI. As far
as I can tell, the issue is something with the combination of the debug
allocator in u_debug_memory.c and the mutex implementation in the
version of Wine running in CI. The tests don't fail on real windows nor
do they fail with newer versions of Wine.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4228>
Jason Ekstrand [Wed, 18 Mar 2020 16:32:15 +0000 (11:32 -0500)]
util/sparse_array: Add a node_size_log2 temporary
We use this value several times. It's probably best to encourage the
compiler to only read it once. I have no proof that this actually makes
any performance improvement whatsoever.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4228>
Jason Ekstrand [Thu, 19 Mar 2020 14:39:38 +0000 (09:39 -0500)]
util/sparse_array: Finish the sparse_array in the tests
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4228>
Eric Anholt [Thu, 19 Mar 2020 18:45:01 +0000 (11:45 -0700)]
ci: Move db820c and db410c's gles3 tests to manual, like radv did.
This should make these tests available for clicking on the web ui in
personal branches, while hiding them from marge and the post-merge CI
pipelines. We had already disabled db410c's gles3, but it wasn't
available in the ui and you had to hack .gitalb-ci.yml. db820c is now
being disabled by default, due to instaboots mentioned in
https://gitlab.freedesktop.org/mesa/mesa/issues/2649
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4247>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4247>
Mark Menzynski [Tue, 28 Jan 2020 12:20:01 +0000 (13:20 +0100)]
tgsi/util: Change boolean for bool
I was getting errors with "boolean" when compiling. This patch changes
boolean to bool from <stdbool.h>.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Mark Menzynski <mmenzyns@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3903>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3903>
Mark Menzynski [Tue, 10 Dec 2019 10:28:11 +0000 (11:28 +0100)]
util/blob: Add overwrite function for uint8
Overwrite function for this type was missing and I needed it for my project.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Mark Menzynski <mmenzyns@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3903>
Vasily Khoruzhick [Thu, 19 Mar 2020 02:27:12 +0000 (19:27 -0700)]
lima: add support for R and RG formats
Unfortunately these are not supported natively for sampling
so we have to lower them.
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4241>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4241>
Vasily Khoruzhick [Thu, 19 Mar 2020 02:21:57 +0000 (19:21 -0700)]
lima: split pixel and texel format tables
This is preparation for the next commit where we may need different
swap_r_b flags for pixel and texel formats.
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4241>
Erik Faye-Lund [Tue, 3 Mar 2020 18:37:37 +0000 (19:37 +0100)]
zink/spirv: do not use bitwise operations on booleans
According to the SPIR-V specification, these operations require
integer-types. When bit_size is 1, we use booleans, which makes us emit
illegal code.
So let's fix the emitting to check if the first source is one bit wide.
For inot we can take a short-cut, and check the destination instead.
This doesn't work for ieq and ine, so let's not bother to do this
BINOP_LOG.
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4036>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4036>
Michel Dänzer [Wed, 18 Mar 2020 17:41:43 +0000 (18:41 +0100)]
gitlab-ci: Restrict s390x/ppc64el jobs to packet runners
They are hitting timeouts on the gstreamer runners now... *sigh*
Reviewed-by: Adam Jackson <ajax@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4233>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4233>
Rhys Perry [Thu, 19 Mar 2020 20:13:52 +0000 (20:13 +0000)]
radv/winsys: set has_syncobj_wait_for_submit in the null winsys
Needed for Vulkan 1.1+
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4249>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4249>
Lionel Landwerlin [Thu, 19 Mar 2020 19:30:01 +0000 (21:30 +0200)]
intel: add new TGL pci ids
Update following kernel : https://patchwork.freedesktop.org/patch/357921/
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bspec: 44455
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4248>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4248>
Samuel Pitoiset [Wed, 18 Mar 2020 17:49:23 +0000 (18:49 +0100)]
radv: fix optional pSizes parameter when binding streamout buffers
The Vulkan spec 1.2.135 says:
"pSizes is an optional array of buffer sizes, specifying the maximum
number of bytes to capture to the corresponding transform feedback
buffer. If pSizes is NULL, or the value of the pSizes array element
is VK_WHOLE_SIZE, then the maximum bytes captured will be the size
of the corresponding buffer minus the buffer offset."
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2650
Fixes: b4eb029062a ("radv: implement VK_EXT_transform_feedback")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4232>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4232>
Caio Marcelo de Oliveira Filho [Thu, 19 Mar 2020 00:14:19 +0000 (17:14 -0700)]
mesa/main: Fix overflow in validation of DispatchComputeGroupSizeARB
An uint64_t can store the result of multiplying two GLuint (uint32_t),
so use that property to check for overflow when calculating the total.
Change the error message so we don't need to care about the actual
total -- which means we don't need a larger than 64-bit value to hold
it.
Fixes: 45ab63c0cb2 ("mesa/main: add support for ARB_compute_variable_groups_size")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4240>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4240>
Marek Olšák [Fri, 20 Mar 2020 01:01:24 +0000 (21:01 -0400)]
driconf: enable glthread for "From The Depths"
25% perf improvement
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4254>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4254>
Marek Olšák [Fri, 13 Mar 2020 20:10:56 +0000 (16:10 -0400)]
winsys/radeon: change to 3-space indentation
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4192>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4192>
Marek Olšák [Thu, 5 Mar 2020 21:03:19 +0000 (16:03 -0500)]
glthread: don't declare unmarshal functions as inline
They are never inlined.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
Marek Olšák [Thu, 5 Mar 2020 20:59:49 +0000 (15:59 -0500)]
glthread: clean up debug_print_sync code
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
Marek Olšák [Thu, 5 Mar 2020 20:57:46 +0000 (15:57 -0500)]
glthread: remove debug_print_marshal function
We don't need to print every function we execute.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
Marek Olšák [Wed, 4 Mar 2020 20:02:15 +0000 (15:02 -0500)]
glthread: don't execute any custom VAO and BindBuffer code in the Core profile
It's not needed, because user pointers can never occur there.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
Marek Olšák [Wed, 4 Mar 2020 19:46:56 +0000 (14:46 -0500)]
glthread: track VAOs created by CreateVertexArrays
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
Marek Olšák [Thu, 20 Feb 2020 03:25:07 +0000 (22:25 -0500)]
glthread: enable display lists
They seem to work fine.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
Marek Olšák [Fri, 6 Mar 2020 03:21:11 +0000 (22:21 -0500)]
glthread: align the batch buffer to 8 bytes for pointers and doubles again
This was changed when I switched to types from size_t to int.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
Marek Olšák [Mon, 9 Mar 2020 23:37:39 +0000 (19:37 -0400)]
mesa: remove redundant api_loopback functions
vbo_attrib_tmp.h implements them, so this loopback code isn't needed
and shouldn't be used.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4123>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4123>
Marek Olšák [Sun, 8 Mar 2020 22:47:56 +0000 (18:47 -0400)]
mesa: use vbo_attrib_tmp.h to generate display list vertex attrib functions
This removes about 1150 lines of code.
The diff is messy, but the new code really starts with save_Attr32bit and
below. Ignore false Eval/Material/Begin changes etc. Git can't figure out
what was really changed. I didn't change them.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4123>
Jason Ekstrand [Wed, 18 Mar 2020 18:29:06 +0000 (13:29 -0500)]
anv: Only add END_OF_PIPE_SYNC if we actually have AUX_INVAL
Fixes: 43dc842cb91c "anv: Wait for the GPU to be idle before..."
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: D Scott Phillips <d.scott.phillips@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4234>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4234>
Eric Anholt [Tue, 17 Mar 2020 23:03:11 +0000 (16:03 -0700)]
freedreno: Switch to exposing only half-integer pixel centers.
This is what the HW provides us. If we need integer pixel centers, we
want the state tracker to do the lowering pass so that it gets to optimize
on the subtract. This is also the shader instructions that the blob is
doing on GLES, and is what Vulkan wants too, as was noted in MR !4172.
shader-db on a630:
total instructions in shared programs: 186689 -> 186168 (-0.28%)
total nops in shared programs: 66253 -> 66139 (-0.17%)
total non-nops in shared programs: 120436 -> 120029 (-0.34%)
total dwords in shared programs: 292192 -> 291168 (-0.35%)
total last-baryf in shared programs: 4810 -> 4734 (-1.58%)
total full in shared programs: 10176 -> 10195 (0.19%)
total constlen in shared programs: 54589 -> 54575 (-0.03%)
total sstall in shared programs: 24582 -> 24802 (0.89%)
total (ss) in shared programs: 3921 -> 3925 (0.10%)
total (sy) in shared programs: 1934 -> 1923 (-0.57%)
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4223>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4223>
John Stultz [Thu, 12 Mar 2020 22:42:29 +0000 (22:42 +0000)]
r600: Fix build error in sfn_nir_lower_fs_out_to_vector.cpp
In trying a full build under AOSP, I ran into the following error:
In file included from external/mesa3d/src/gallium/drivers/r600/sfn/sfn_nir_lower_fs_out_to_vector.cpp:33:
external/libcxx/include/set:942:26: error: the specified comparator type does not provide a const call operator [-Werror,-Wuser-defined-warnings]
static_assert(sizeof(__diagnose_non_const_comparator<_Key, _Compare>()), "");
^
external/mesa3d/src/gallium/drivers/r600/sfn/sfn_nir_lower_fs_out_to_vector.cpp:78:34: note: in instantiation of template class 'std::__1::multiset<nir_intrinsic_ins
tr *, r600::nir_intrinsic_instr_less, std::__1::allocator<nir_intrinsic_instr *> >' requested here
using InstrSubSet = std::pair<InstrSet::iterator, InstrSet::iterator>;
^
external/libcxx/include/__tree:967:5: note: from 'diagnose_if' attribute on '__diagnose_non_const_comparator<nir_intrinsic_instr *, r600::nir_intrinsic_instr_less>':
_LIBCPP_DIAGNOSE_WARNING(!std::__invokable<_Compare const&, _Tp const&, _Tp const&>::value,
^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
external/libcxx/include/__config:1244:21: note: expanded from macro '_LIBCPP_DIAGNOSE_WARNING'
__attribute__((diagnose_if(__VA_ARGS__, "warning")))
^ ~~~~~~~~~~~
1 error generated.
Which is pretty opaque to me, but searching the web suggested
adding a cost, which seems to resovle it.
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4175>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4175>
John Stultz [Thu, 12 Mar 2020 21:21:50 +0000 (21:21 +0000)]
vc4_bufmgr: Remove duplicative VC definition
This is already defined in
src/broadcom/cle/v3d_packet_helpers.h:42:9
And was causing build issues in AOSP when building with mmma
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4175>
John Stultz [Thu, 12 Mar 2020 22:21:29 +0000 (22:21 +0000)]
etnaviv: Avoid shift overflow
Building with AOSP I'm seeing:
external/mesa3d/src/gallium/drivers/etnaviv/etnaviv_screen.c:245:31: error: signed shift result (0x100000000) requires 34 bits to represent, but 'int' only has 32 bits [-Werror,-Wshift-overflow]
system_memory = 4096 << 20;
system_memory is a uint_64t, so this patch addresses the issue
by casting 4096 to a unint_64t before the shift is done.
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4175>
John Stultz [Fri, 26 Apr 2019 16:35:13 +0000 (09:35 -0700)]
Android.mk: Tweak MESA_ENABLE_LLVM checks
Change the MESA_ENABLE_LLVM checks in Android.mk
files in order to get mesa3d to build w/ AOSP
using mmma.
This tries to re-create a change that was introduced
in the following merge in the AOSP branch:
69f2c0128d2b Merge branch 'aosp/upstream-18.0'
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4175>
Jason Ekstrand [Wed, 4 Mar 2020 20:37:03 +0000 (14:37 -0600)]
intel/iris: Always initialize CCS to 0
Previously, we were initializing the CCS to 0xFF for MCS+CCS due to a
misunderstanding of the following lines in the bspec:
The following are the general SW requirements for MCS buffer clear
functionality:
...
- If Software wants to enable Color Compression without Fast
clear, Software needs to initialize MCS with zeros.
- Lossless compression and CCS initialized to all F (using HW
Fast Clear or SW direct Clear) on the same surface is not
supported.
The first line does not refer to the CCS as the comment author supposed
but refers to the MCS as the comment says. It means that if you want to
use MCS compression without a fast-clear, you should initialize the MCS
to 0x00. This is because the value 0x00 in the MCS means "all data is
in plane 0" which is a perfectly valid non-fast-clear initialization.
It's also the value the MCS should be in if you do a RECTLIST slow-clear
where the primitive fully covers each pixel such that the same value is
written to all samples.
The second line in the above quote seems to imply that CCS fast-clear is
incompatible with MCS fast-clear. In particular, MCS+CCS fast-clear
uses a 0xff value in the MCS (like on Gen7-11) and leaves the CCS in
either the compressed or the pass-through state. Therefore, we should
initialize the CCS to 0x00 even for MCS+CCS surfaces.
Reviewed-by: Sagar Ghuge<sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4074>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4074>
Lionel Landwerlin [Wed, 18 Mar 2020 18:03:53 +0000 (20:03 +0200)]
isl: drop min row pitch alignment when set by the driver
When the caller of the isl_surf_init() specifies a row pitch, do not
consider the minimum CCS requirement if it's incompatible with the
caller's value.
isl_surf_get_ccs_surf() will check that the main surface alignment
matches CCS expectations.
v2: Simplify checks (Nanley)
v3: Add Comment about isl_surf_get_ccs_surf() (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Fixes: a3f6db2c4e92 ("isl: drop CCS row pitch requirement for linear surfaces")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
Lionel Landwerlin [Thu, 20 Feb 2020 14:16:33 +0000 (16:16 +0200)]
isl: only apply main surface ccs pitch constraint with CCS
We could be creating a Y-tiled surface that isn't going to use CCS
(this could be the case when clearly indicated through modifiers).
Don't apply the main surface pitch alignment constraint in that case.
v2: Use logical NOT (Sagar)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a3f6db2c4e92 ("isl: drop CCS row pitch requirement for linear surfaces")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
Lionel Landwerlin [Tue, 15 Oct 2019 11:37:45 +0000 (14:37 +0300)]
isl: properly filter supported display modifiers on Gen9+
Y tiling is supported for display on Gen9+ so don't filter it from the
possible flags.
v2: Drop Yf from display supported tilings on Gen12+ (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
Lionel Landwerlin [Mon, 14 Oct 2019 18:26:18 +0000 (21:26 +0300)]
isl: implement linear tiling row pitch requirement for display
We're missing a requirement for alignment of row pitch for the display
HW. In linear tiling, the row pitch must be a 64bytes aligned.
v2: Use correct formula to align to 64bytes (Chad)
v3: Matching {} (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
Eric Anholt [Wed, 18 Mar 2020 16:51:03 +0000 (09:51 -0700)]
ci: Only run the freedreno baremetal tests when freedreno/core changes.
Same as we do for a630 (docker) tests.
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4229>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4229>
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