Andrew Lukefahr [Wed, 21 Mar 2012 15:34:06 +0000 (10:34 -0500)]
O3: Fix sizing of decode to rename skid buffer.
Koan-Sin Tan [Wed, 21 Mar 2012 15:34:05 +0000 (10:34 -0500)]
ARM: Add RTC to PBX System
Brian Grayson [Wed, 21 Mar 2012 15:34:05 +0000 (10:34 -0500)]
O3: Fix size of skid buffer between fetch and decode when widths are different
Ali Saidi [Wed, 21 Mar 2012 15:34:05 +0000 (10:34 -0500)]
ARM: Fix uninitialized value in ARM RTC model.
Tushar Krishna [Mon, 19 Mar 2012 21:34:17 +0000 (17:34 -0400)]
Garnet: Stats at vnet granularity + code cleanup
This patch
(1) Moves redundant code from fixed and flexible networks to BaseGarnetNetwork.
(2) Prints network stats at vnet granularity.
Andreas Hansson [Mon, 19 Mar 2012 10:36:09 +0000 (06:36 -0400)]
gcc: Clean-up of non-C++0x compliant code, first steps
This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).
Andreas Hansson [Mon, 19 Mar 2012 10:35:04 +0000 (06:35 -0400)]
clang: Fix recently introduced clang compilation errors
This patch makes the code compile with clang 2.9 and 3.0 again by
making two very minor changes. Firt, it maintains a strict typing in
the forward declaration of the BaseCPUParams. Second, it adds a
FullSystemInt flag of the type unsigned int next to the boolean
FullSystem flag. The FullSystemInt variable can be used in
decode-statements (expands to switch statements) in the instruction
decoder.
Andreas Hansson [Mon, 19 Mar 2012 10:34:02 +0000 (06:34 -0400)]
scripts: Fix to ensure that port connection count is always set
This patch ensures that the port connection count is set to zero in those
cases when the port is not connected.
Nilay Vaish [Fri, 16 Mar 2012 12:47:03 +0000 (07:47 -0500)]
ruby_fs.py: Add call to createInterruptController()
Nilay Vaish [Fri, 16 Mar 2012 12:46:45 +0000 (07:46 -0500)]
FSConfig.py: fix a typo makeLinuxAlphaRubySystem
Marc Orr [Fri, 16 Mar 2012 10:29:07 +0000 (03:29 -0700)]
build: remove implicit-cache setting of scons from recent build faster patch
Nilay Vaish [Sun, 11 Mar 2012 21:51:38 +0000 (16:51 -0500)]
se.py: Changes to ruby portion due to SE/FS merge
With the SE/FS merge, interrupt controller is created irrespective of the
mode. This patch creates the interrupt controller when Ruby is used and
connects its ports.
Brian Grayson [Sun, 11 Mar 2012 14:20:54 +0000 (10:20 -0400)]
O3: Add fatal when fetchWidth > Impl::MaxWidth.
Ali Saidi [Fri, 9 Mar 2012 21:45:47 +0000 (16:45 -0500)]
ARM: Fix memory starting at non-zero address and exceeding max mem for a system.
Ali Saidi [Fri, 9 Mar 2012 20:33:07 +0000 (15:33 -0500)]
ARM: Update stats for CBNZ fix.
Brian Grayson [Fri, 9 Mar 2012 20:32:41 +0000 (15:32 -0500)]
ARM: Fix branch prediction issue with CB(N)Z instruction
Ali Saidi [Fri, 9 Mar 2012 14:59:29 +0000 (09:59 -0500)]
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
Geoffrey Blake [Fri, 9 Mar 2012 14:59:28 +0000 (09:59 -0500)]
O3/Ozone: Eliminate dead code counting software prefetch insts
Eliminates dead code in the O3 and Ozone CPU models that counted
software prefetch instructions separately for the ALPHA ISA only.
Geoffrey Blake [Fri, 9 Mar 2012 14:59:28 +0000 (09:59 -0500)]
CheckerCPU: Make some basic regression tests for CheckerCPU
Adds regression tests for the CheckerCPU. ARM ISA support
only at this point.
Geoffrey Blake [Fri, 9 Mar 2012 14:59:28 +0000 (09:59 -0500)]
CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU
Making the CheckerCPU a runtime time option requires the code to be compatible
with ISAs other than ARM. This patch adds the appropriate function
stubs to allow compilation.
Geoffrey Blake [Fri, 9 Mar 2012 14:59:27 +0000 (09:59 -0500)]
CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
Enables the CheckerCPU to be selected at runtime with the --checker option
from the configs/example/fs.py and configs/example/se.py configuration
files. Also merges with the SE/FS changes.
Ali Saidi [Fri, 9 Mar 2012 14:59:26 +0000 (09:59 -0500)]
ARM: Don't reset CPUs that are going to be switched in.
Ali Saidi [Fri, 9 Mar 2012 14:59:26 +0000 (09:59 -0500)]
System: Move code in initState() back into constructor whenever possible.
The change to port proxies recently moved code out of the constructor into
initState(). This is needed for code that loads data into memory, however
for code that setups symbol tables, kernel based events, etc this is the wrong
thing to do as that code is only called when a checkpoint isn't being restored
from.
Ali Saidi [Fri, 9 Mar 2012 14:59:26 +0000 (09:59 -0500)]
ARM: Fix valgrind reported error on O3 that was causing minor stats changes.
Ali Saidi [Fri, 9 Mar 2012 14:59:25 +0000 (09:59 -0500)]
cache: Allow main memory to be at disjoint address ranges.
Gabe Black [Thu, 8 Mar 2012 10:10:03 +0000 (02:10 -0800)]
Fix the SPARC fs regression by adding a call to createInterruptController.
Marc Orr [Wed, 7 Mar 2012 03:07:41 +0000 (19:07 -0800)]
build scripts: Made minor modifications to reduce build overhead time.
1. --implicit-cache behavior is default.
2. makeEnv in src/SConscript is conditionally called.
3. decider set to MD5-timestamp
4. NO_HTML build option changed to SLICC_HTML (defaults to False)
Andreas Hansson [Tue, 6 Mar 2012 16:14:54 +0000 (11:14 -0500)]
Stats: Update stats for changeset 8868
Changeset 8868 slightly changes the statistics for the parser and
bzip2 regressions for ARM o3-timing. This patch merely updates the
statistics to reflect these changes.
Steve Reinhardt [Fri, 2 Mar 2012 22:05:00 +0000 (14:05 -0800)]
SConstruct: rename and document AddM5Option
Got rid of gratuitous M5 reference in the function name.
In the process, wondered why we have this function at all and
spent time trying to get rid of it and eventually firgured out
why it's needed. Put the answer in a comment so we don't have
to wonder again.
Steve Reinhardt [Fri, 2 Mar 2012 21:53:52 +0000 (13:53 -0800)]
SConstruct: update comments & doc strings
Lots of references to 'M5' still, and some to SE/FS
Steve Reinhardt [Fri, 2 Mar 2012 17:17:42 +0000 (09:17 -0800)]
DynInst: get rid of dead MyHash code.
Not sure what this was ever used for, but it
doesn't seem used anymore.
Andreas Hansson [Fri, 2 Mar 2012 14:21:48 +0000 (09:21 -0500)]
CPU: Check that the interrupt controller is created when needed
This patch adds a creation-time check to the CPU to ensure that the
interrupt controller is created for the cases where it is needed,
i.e. if the CPU is not being switched in later and not a checker CPU.
The patch also adds the "createInterruptController" call to a number
of the regression scripts.
Andreas Hansson [Fri, 2 Mar 2012 14:18:50 +0000 (09:18 -0500)]
Stats: Fix the realview regression stats after nvmem move
This patch updates the realview regressions stats to reflect that nvmem
moved in the object hierarchy and is now under system.realview.
Andreas Hansson [Fri, 2 Mar 2012 14:16:50 +0000 (09:16 -0500)]
Ruby: Rename RubyPort::sendTiming to avoid overriding base class
This patch renames the sendTiming member function in the RubyPort to
avoid inadvertently hiding Port::sendTiming (discovered through some
rather painful debugging). The RubyPort does, in fact, rely on the
functionality of the queued port and the implementation merely
schedules a send the next cycle. The new name for the member function
is sendNextCycle to better reflect this behaviour.
In the unlikely event that we ever shift to using C++11 the member
functions in Port should have a "final" identifier to prevent any
overriding in derived classes.
Ali Saidi [Fri, 2 Mar 2012 14:18:19 +0000 (08:18 -0600)]
ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine.
New kernel code verifies that multi-processor extensions are available
before booting secondary CPUs.
Ali Saidi [Fri, 2 Mar 2012 04:43:23 +0000 (22:43 -0600)]
ARM: FIx missing cf controller connection.
Chander Sudanthi [Thu, 1 Mar 2012 23:26:36 +0000 (17:26 -0600)]
VNC: spacing
Fixed some spacing in a switch statement
Ali Saidi [Thu, 1 Mar 2012 23:26:31 +0000 (17:26 -0600)]
ARM: Add support for Versatile Express extended memory map
Also clean up how we create boot loader memory a bit.
Ali Saidi [Thu, 1 Mar 2012 23:26:31 +0000 (17:26 -0600)]
ARM: Add RTC device for ARM platforms.
This change implements a PL031 real time clock.
--HG--
rename : src/dev/arm/timer_sp804.cc => src/dev/arm/rtc_pl031.cc
rename : src/dev/arm/timer_sp804.hh => src/dev/arm/rtc_pl031.hh
Matt Horsnell [Thu, 1 Mar 2012 23:26:31 +0000 (17:26 -0600)]
ARM: Add limited CP14 support.
New kernels attempt to read CP14 what debug architecture is available.
These changes add the debug registers and return that none is currently
available.
Ali Saidi [Thu, 1 Mar 2012 23:26:31 +0000 (17:26 -0600)]
Cache: Fix an issue with LRU when bonus block is used to complete transaction.
The block is never inserted because it's the one extra block in the cache, but
it can be invalidated twice in a row. In that case the block doesn't have a
new master id (beacuse it was never inserted), however it is valid and
the accounting goes wrong at that point.
Dam Sunwoo [Thu, 1 Mar 2012 23:26:31 +0000 (17:26 -0600)]
ARM: move kernel func event to correct location.
With the recent series of patches, the symbol table loading moved from
"construct" time to "init" time, but the kernel function event
callback registration was left behind. This patch moves it to the
proper location.
Giacomo Gabrielli [Thu, 1 Mar 2012 23:26:30 +0000 (17:26 -0600)]
ARM: fix bits-to-fp conversion function declarations.
Add extra declarations to allow the compiler to pick up the right function.
Please note that these declarations have been added as part of the
clang-related changes.
Nilay Vaish [Thu, 1 Mar 2012 17:37:03 +0000 (11:37 -0600)]
x86: Fix x86 TLB and Walker
This patch adds a function to X86 tlb that returns the
walker port. This port is required for correctly connecting
the walker ports for the cpu just switched in
Nilay Vaish [Thu, 1 Mar 2012 17:37:02 +0000 (11:37 -0600)]
x86: Fix switching of CPUs
This patch prevents creation of interrupt controller for
cpus that will be switched in later
Nilay Vaish [Thu, 1 Mar 2012 17:36:59 +0000 (11:36 -0600)]
Config: make option ruby available always
Andreas Hansson [Wed, 29 Feb 2012 09:47:51 +0000 (04:47 -0500)]
MEM: Make all the port proxy members const
This is a trivial patch that merely makes all the member functions of
the port proxies const. There is no good reason why they should not
be, and this change only serves to make it explicit that they are not
modified through their use.
Andreas Hansson [Wed, 29 Feb 2012 09:26:58 +0000 (04:26 -0500)]
SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1
This patch fixes a compilation error that occurs with gcc >= 4.6.1,
caused by swig not including cstddef and not using the std:: namespace
prefix for ptrdiff_t. There is an old patch,
http://reviews.m5sim.org/r/913/ that no longer applies cleanly and
this might be re-iterating the same issue.
We work around the problem by always enforcing the inclusion of
cstddef in all swig interface declarations, and also by explicitly
using std::ptrdiff_t.
Steve Reinhardt [Wed, 29 Feb 2012 06:51:39 +0000 (01:51 -0500)]
EIO: update stats (mostly order change, some renames)
Gabe Black [Sun, 26 Feb 2012 23:33:07 +0000 (15:33 -0800)]
Make the IO bridge accept address headed to all the local APICs.
Gabe Black [Sun, 26 Feb 2012 23:32:53 +0000 (15:32 -0800)]
X86: Use the M5PanicFault fault in execute methods instead of calling panic.
If an instruction is executed speculatively and hits a situation where it
wants to panic, it should return a fault instead. If the instruction was
misspeculated, the fault can be thrown away. If the instruction wasn't
misspeculated, the fault will be invoked and the panic will still happen.
Andreas Hansson [Fri, 24 Feb 2012 16:52:49 +0000 (11:52 -0500)]
MEM: Simplify cache ports preparing for master/slave split
This patch splits the two cache ports into a master (memory-side) and
slave (cpu-side) subclass of port with slightly different
functionality. For example, it is only the CPU-side port that blocks
incoming requests, and only the memory-side port that schedules send
events outside of what the transmit list dictates.
This patch simplifies the two classes by relying further on
SimpleTimingPort and also generalises the latter to better accommodate
the changes (introducing trySendTiming and scheduleSend). The
memory-side cache port overrides sendDeferredPacket to be able to not
only send responses from the transmit list, but also send requests
based on the MSHRs.
A follow on patch further simplifies the SimpleTimingPort and the
cache ports.
Andreas Hansson [Fri, 24 Feb 2012 16:50:15 +0000 (11:50 -0500)]
MEM: Prepare mport for master/slave split
This patch simplifies the mport in preparation for a split into a
master and slave role for the message ports. In particular,
sendMessageAtomic was only used in a single location and similarly so
sendMessageTiming. The affected interrupt device is updated
accordingly.
Andreas Hansson [Fri, 24 Feb 2012 16:48:48 +0000 (11:48 -0500)]
Ruby: Simplify tester ports by not using SimpleTimingPort
This patch simplfies the master ports used by RubyDirectedTester and
RubyTester by avoiding the use of SimpleTimingPort. Neither tester
made any use of the functionality offered by SimpleTimingPort besides
a trivial implementation of recvFunctional (only snoops) and
recvRangeChange (not relevant since there is only one master).
The patch does not change or add any functionality, it merely makes
the introduction of a master/slave port easier (in a future patch).
Andreas Hansson [Fri, 24 Feb 2012 16:46:39 +0000 (11:46 -0500)]
MEM: Move all read/write blob functions from Port to PortProxy
This patch moves the readBlob/writeBlob/memsetBlob from the Port class
to the PortProxy class, thus making a clear separation of the basic
port functionality (recv/send functional/atomic/timing), and the
higher-level functional accessors available on the port proxies.
There are only a few places in the code base where the blob functions
were used on ports, and they are all for peeking into the memory
system without making a normal memory access (in the memtest, and the
malta and tsunami pchip). The memtest also exemplifies how easy it is
to create a non-translating proxy if desired. The malta and tsunami
pchip used a slave port to perform a functional read, and this is now
changed to rely on the physProxy of the system (to which they already
have a pointer).
Andreas Hansson [Fri, 24 Feb 2012 16:45:30 +0000 (11:45 -0500)]
MEM: Make port proxies use references rather than pointers
This patch is adding a clearer design intent to all objects that would
not be complete without a port proxy by making the proxies members
rathen than dynamically allocated. In essence, if NULL would not be a
valid value for the proxy, then we avoid using a pointer to make this
clear.
The same approach is used for the methods using these proxies, such as
loadSections, that now use references rather than pointers to better
reflect the fact that NULL would not be an acceptable value (in fact
the code would break and that is how this patch started out).
Overall the concept of "using a reference to express unconditional
composition where a NULL pointer is never valid" could be done on a
much broader scale throughout the code base, but for now it is only
done in the locations affected by the proxies.
Andreas Hansson [Fri, 24 Feb 2012 16:43:53 +0000 (11:43 -0500)]
MEM: Move port creation to the memory object(s) construction
This patch moves all port creation from the getPort method to be
consistently done in the MemObject's constructor. This is possible
thanks to the Swig interface passing the length of the vector ports.
Previously there was a mix of: 1) creating the ports as members (at
object construction time) and using getPort for the name resolution,
or 2) dynamically creating the ports in the getPort call. This is now
uniform. Furthermore, objects that would not be complete without a
port have these ports as members rather than having pointers to
dynamically allocated ports.
This patch also enables an elaboration-time enumeration of all the
ports in the system which can be used to determine the masterId.
Andreas Hansson [Fri, 24 Feb 2012 16:42:00 +0000 (11:42 -0500)]
CPU: Round-two unifying instr/data CPU ports across models
This patch continues the unification of how the different CPU models
create and share their instruction and data ports. Most importantly,
it forces every CPU to have an instruction and a data port, and gives
these ports explicit getters in the BaseCPU (getDataPort and
getInstPort). The patch helps in simplifying the code, make
assumptions more explicit, andfurther ease future patches related to
the CPU ports.
The biggest changes are in the in-order model (that was not modified
in the previous unification patch), which now moves the ports from the
CacheUnit to the CPU. It also distinguishes the instruction fetch and
load-store unit from the rest of the resources, and avoids the use of
indices and casting in favour of keeping track of these two units
explicitly (since they are always there anyways). The atomic, timing
and O3 model simply return references to their already existing ports.
Andreas Hansson [Fri, 24 Feb 2012 16:40:29 +0000 (11:40 -0500)]
MEM: Fatal when no port can be found for an address
This patch adds a check in the findPort method to ensure that an
invalid port id is never returned. Previously this could happen if no
default port was set, and no address matched the request, in which
case -1 was returned causing a SEGFAULT when using the id to index in
the port array. To clean things up further a symbolic name is added
for the invalid port id.
Steve Reinhardt [Mon, 20 Feb 2012 16:11:14 +0000 (08:11 -0800)]
SimObject: make get_config_as_dict() tolerate undefined params
Without this patch, undefined params cause a cryptic KeyError
in multidict inside get_config_as_dict(). This patch lets
undefined params through get_config_as_dict() so they can
once again generate meaningful error messages later on in
the configuration process.
Andreas Hansson [Tue, 14 Feb 2012 19:15:30 +0000 (14:15 -0500)]
MEM: Fix residual bus ports and make them master/slave
This patch cleans up a number of remaining uses of bus.port which
is now split into bus.master and bus.slave. The only non-trivial change
is the memtest where the level building now has to be aware of the role
of the ports used in the previous level.
Andreas Hansson [Tue, 14 Feb 2012 17:11:18 +0000 (12:11 -0500)]
Script: Fix the scripts that use the num_cpus cache parameter
This patch merely removes the use of the num_cpus cache parameter
which no longer exists after the introduction of the masterIds. The
affected scripts fail when trying to set the parameter. Note that this
patch does not update the regression stats.
Andreas Hansson [Tue, 14 Feb 2012 08:41:53 +0000 (03:41 -0500)]
MEM: Fix master/slave ports in Ruby and non-regression scripts
This patch brings the Ruby and other scripts up to date with the
introduction of the master/slave ports.
Ali Saidi [Mon, 13 Feb 2012 18:30:30 +0000 (12:30 -0600)]
bp: fix up stats for changes to branch predictor
Mrinmoy Ghosh [Mon, 13 Feb 2012 18:26:25 +0000 (12:26 -0600)]
BPred: Fix RAS to handle predicated call/return instructions.
Change RAS to fix issues with predicated call/return instructions.
Handled all cases in the life of a predicated call and return instruction.
Mrinmoy Ghosh [Mon, 13 Feb 2012 18:26:24 +0000 (12:26 -0600)]
BP: Fix several Branch Predictor issues.
1. Updates the Branch Predictor correctly to the state
just after a mispredicted branch, if a squash occurs.
2. If a BTB does not find an entry, the branch is predicted not taken.
The global history is modified to correctly reflect this prediction.
3. Local history is now updated at the fetch stage instead of
execute stage.
4. In the Update stage of the branch predictor the local predictors are
now correctly updated according to the state of local history during
fetch stage.
This patch also improves performance by as much as 17% on some benchmarks
Andreas Hansson [Mon, 13 Feb 2012 11:46:43 +0000 (06:46 -0500)]
MEM: Explicit ports and Python binding on CopyEngine
The copy-engine ports were previously created implicitly and bound
based on the dma port peer rather than relying on the normal Python
binding (connectPorts) being called explicitly. This patch makes the
copy engine port similar to all other ports in that they are visibly
in the Python class and bound using the normal explicit calls through
Python.
Andreas Hansson [Mon, 13 Feb 2012 11:45:11 +0000 (06:45 -0500)]
MEM: Pass the ports from Python to C++ using the Swig params
This patch adds basic information about the ports in the parameter
classes to be passed from the Python world to the corresponding C++
object. Currently, the only information passed is the number of
connected peers, which for a Port is either 0 or 1, and for a
VectorPort reflects the size of the VectorPort. The default port of
the bus had to be renamed to avoid using the name "default" as a field
in the parameter class. It is possible to extend the Swig'ed
information further and add e.g. a pair with a description and size.
Andreas Hansson [Mon, 13 Feb 2012 11:43:09 +0000 (06:43 -0500)]
MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.
The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.
Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
Ali Saidi [Mon, 13 Feb 2012 00:35:59 +0000 (18:35 -0600)]
tests: fix diff-out script for op/inst stat changes.
Gabe Black [Mon, 13 Feb 2012 00:41:29 +0000 (16:41 -0800)]
X86: open flags: Another patch from Vince Weaver
Ali Saidi [Sun, 12 Feb 2012 23:18:53 +0000 (17:18 -0600)]
configs: fix minor config bugs posted on the mailing list
Ali Saidi [Sun, 12 Feb 2012 22:07:43 +0000 (16:07 -0600)]
stats: update stats for insts/ops and master id changes
Anthony Gutierrez [Sun, 12 Feb 2012 22:07:39 +0000 (16:07 -0600)]
cpu: add separate stats for insts/ops both globally and per cpu model
Dam Sunwoo [Sun, 12 Feb 2012 22:07:39 +0000 (16:07 -0600)]
mem: fix cache stats to use request ids correctly
This patch fixes the cache stats to use the new request ids.
Cache stats also display the requestor names in the vector subnames.
Most cache stats now include "nozero" and "nonan" flags to reduce the
amount of excessive cache stat dump. Also, simplified
incMissCount()/incHitCount() functions.
Ali Saidi [Sun, 12 Feb 2012 22:07:38 +0000 (16:07 -0600)]
mem: Add a master ID to each request object.
This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
Mrinmoy Ghosh [Sun, 12 Feb 2012 22:07:38 +0000 (16:07 -0600)]
prefetcher: Make prefetcher a sim object instead of it being a parameter on cache
Nilay Vaish [Sun, 12 Feb 2012 19:22:04 +0000 (13:22 -0600)]
Regressions: Update stats due to change in MESI protocol
Gabe Black [Sat, 11 Feb 2012 22:16:38 +0000 (14:16 -0800)]
SPARC: Make PSTATE and HPSTATE a BitUnion.
This gets rid of cryptic bits of code with lots of bit manipulation, and makes
some comments redundant.
Nilay Vaish [Fri, 10 Feb 2012 17:29:02 +0000 (11:29 -0600)]
Ruby: Remove isTagPresent() calls from Sequencer.cc
This patch removes the calls to isTagPresent() from Sequencer.cc. These
calls are made just for setting the cache block to have been most recently
used. The calls have been folded in to the function setMRU().
Nilay Vaish [Fri, 10 Feb 2012 17:05:24 +0000 (11:05 -0600)]
MESI: Add queues for stalled requests
This patch adds support for stalling the requests queued up at different
controllers for the MESI CMP directory protocol. Earlier the controllers
would recycle the requests using some fixed latency. This results in
younger requests getting serviced first at times, and can result in
starvation. Instead all the requests that need a particular block to be
in a stable state are moved to a separate queue, where they wait till
that block returns to a stable state and then they are processed.
Nilay Vaish [Fri, 10 Feb 2012 15:52:32 +0000 (09:52 -0600)]
sim/system: initialize the pagePtr variable
Nilay Vaish [Fri, 10 Feb 2012 15:51:37 +0000 (09:51 -0600)]
Regressions: Update stats due to O3 CPU changes
Nilay Vaish [Fri, 10 Feb 2012 14:37:31 +0000 (08:37 -0600)]
O3 CPU: Improve handling of delayed commit flag
The delayed commit flag is used in conjunction with interrupt pending flag to
figure out whether or not fetch stage should get more instructions. This patch
clears this flag when instructions are squashed. Also, in case an interrupt is
pending, currently it is not possible to access the instruction cache. This
patch allows accessing the cache in case this flag is set.
Nilay Vaish [Fri, 10 Feb 2012 14:37:30 +0000 (08:37 -0600)]
O3 CPU: Strengthen condition for handling interrupts
The condition for handling interrupts is to check whether or not the cpu's
instruction list is empty. As observed, this can lead to cases in which even
though the instruction list is empty, interrupts are handled when they should
not be. The condition is being strengthened so that interrupts get handled only
when the last committed microop did not had IsDelayedCommit set.
Nilay Vaish [Fri, 10 Feb 2012 14:37:28 +0000 (08:37 -0600)]
O3 CPU: Provide the squashing instruction
This patch adds a function to the ROB that will get the squashing instruction
from the ROB's list of instructions. This squashing instruction is used for
figuring out the macroop from which the fetch stage should fetch the microops.
Further, a check has been added that if the instructions are to be fetched
from the cache maintained by the fetch stage, then the data in the cache should
be valid and the PC of the thread being fetched from is same as the address of
the cache block.
Nilay Vaish [Fri, 10 Feb 2012 14:37:26 +0000 (08:37 -0600)]
O3 Fetch: Check if PC is pointing to Microcode ROM
Gabe Black [Fri, 10 Feb 2012 10:05:31 +0000 (02:05 -0800)]
SE/FS: Record the system pointer all the time for the simple CPU.
This pointer was only being stored in code that came from SE mode. The system
pointer is always meaningful and available, so it should always be stored.
Andreas Hansson [Thu, 9 Feb 2012 18:06:27 +0000 (13:06 -0500)]
MEM: Remove onRetryList from BusPort and rely on retryList
This patch removes the onRetryList field from the BusPort class and
entirely relies on the retryList which holds all ports that are
waiting to retry. The onRetryList field and the retryList were
previously used with overloaded functionalities and only one is really
needed (there were also checks to assert they held the same
information). After this patch the bus ports will be split into master
and slave ports and this simplifies that transition.
Gabe Black [Tue, 7 Feb 2012 12:44:01 +0000 (04:44 -0800)]
Checker: Access workload element 0 only if there is an element 0.
Gabe Black [Tue, 7 Feb 2012 12:43:21 +0000 (04:43 -0800)]
Faults: Turn off arch/faults.hh
Because there are no longer architecture independent but specialized functions
in arch/XXX/faults.hh, code that isn't using the faults from a particular ISA
no longer needs to be able to include them through the switching header file
arch/faults.hh. By removing that header file (arch/faults.hh), the potential
interface between ISA code and non ISA code is narrowed.
Gabe Black [Tue, 7 Feb 2012 12:43:05 +0000 (04:43 -0800)]
m5=>gem5: Make the regression script build gem5.* instead of m5.*
Gabe Black [Sun, 5 Feb 2012 09:37:40 +0000 (01:37 -0800)]
X86: Rename the bridge which allows commnication back to the local APICs.
There was a collision with a name used in fs.py, and that causes that script
not to work when used with x86.
Gabe Black [Sun, 5 Feb 2012 09:23:22 +0000 (01:23 -0800)]
Regressions: Fix the regress script when "all" is used.
When the "all" test is specified, the "tests" list should have two elements in
it, "quick" and "long", not a single element "quick,long". The later would be
appropriate as the default for one of the command line options which are split
at commas, but at that point "tests" should already be a list.
Gabe Black [Fri, 3 Feb 2012 17:48:10 +0000 (09:48 -0800)]
System: Forgot to qrefresh with my last change.
Gabe Black [Fri, 3 Feb 2012 07:54:25 +0000 (23:54 -0800)]
System: Fix the check which detects running out of physical memory.
The code that checks whether pages allocated by allocPhysPages only checks
that the first page fits into physical memory, not that all of them do. This
change makes the code check the last page which should work properly. This
function used to only allocate one page at a time, so the first page and last
page used to be the same thing.
Andreas Hansson [Thu, 2 Feb 2012 09:51:13 +0000 (04:51 -0500)]
Regression: Update the regress script after SE/FS merge
This patch updates the regress script to reflect the merge of the
SE/FS builds and the new structure of the test directories. It adds a
"mode" flag to the script, that defaults to both se and fs.
Ali Saidi [Wed, 1 Feb 2012 17:48:28 +0000 (09:48 -0800)]
configs: More fixes for the memory system updates
Gabe Black [Wed, 1 Feb 2012 06:40:08 +0000 (22:40 -0800)]
Merge ... head, hopefully the last time for this batch.
Koan-Sin Tan [Tue, 31 Jan 2012 17:05:52 +0000 (12:05 -0500)]
clang: Enable compiling gem5 using clang 2.9 and 3.0
This patch adds the necessary flags to the SConstruct and SConscript
files for compiling using clang 2.9 and later (on Ubuntu et al and OSX
XCode 4.2), and also cleans up a bunch of compiler warnings found by
clang. Most of the warnings are related to hidden virtual functions,
comparisons with unsigneds >= 0, and if-statements with empty
bodies. A number of mismatches between struct and class are also
fixed. clang 2.8 is not working as it has problems with class names
that occur in multiple namespaces (e.g. Statistics in
kernel_stats.hh).
clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which
causes confusion between the container std::set and the function
Packet::set, and this is currently addressed by not including the
entire namespace std, but rather selecting e.g. "using std::vector" in
the appropriate places.