yosys.git
5 years agoImprove API of ID() macro
Clifford Wolf [Fri, 9 Aug 2019 16:54:03 +0000 (18:54 +0200)]
Improve API of ID() macro

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder
Eddie Hung [Sat, 10 Aug 2019 21:18:16 +0000 (14:18 -0700)]
Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder

Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"

5 years agoRevert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
David Shah [Sat, 10 Aug 2019 16:14:48 +0000 (17:14 +0100)]
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"

5 years agoMerge pull request #1258 from YosysHQ/eddie/cleanup
Clifford Wolf [Sat, 10 Aug 2019 07:52:14 +0000 (09:52 +0200)]
Merge pull request #1258 from YosysHQ/eddie/cleanup

Cleanup a few barnacles across codebase

5 years agoMerge pull request #1261 from YosysHQ/clifford/verific_init
Clifford Wolf [Sat, 10 Aug 2019 07:47:25 +0000 (09:47 +0200)]
Merge pull request #1261 from YosysHQ/clifford/verific_init

Automatically prune init attributes in verific front-end

5 years agoMerge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cell
Clifford Wolf [Sat, 10 Aug 2019 07:47:10 +0000 (09:47 +0200)]
Merge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cell

FIRRTL error on unsupported cell

5 years agoMerge pull request #1270 from YosysHQ/eddie/alu_lcu_doc
Clifford Wolf [Sat, 10 Aug 2019 07:46:46 +0000 (09:46 +0200)]
Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc

Add a few comments to document $alu and $lcu

5 years agoMerge pull request #1272 from mmicko/travis_fix
Clifford Wolf [Sat, 10 Aug 2019 07:45:26 +0000 (09:45 +0200)]
Merge pull request #1272 from mmicko/travis_fix

Propagate parameters for Travis build

5 years agoMerge pull request #1274 from YosysHQ/eddie/fix_1271
Clifford Wolf [Sat, 10 Aug 2019 07:45:06 +0000 (09:45 +0200)]
Merge pull request #1274 from YosysHQ/eddie/fix_1271

Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro

5 years agoMerge pull request #1276 from YosysHQ/clifford/fix1273
Clifford Wolf [Sat, 10 Aug 2019 07:38:22 +0000 (09:38 +0200)]
Merge pull request #1276 from YosysHQ/clifford/fix1273

Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib

5 years agoReformat so it shows up/looks nice when "help $alu" and "help $alu+"
Eddie Hung [Fri, 9 Aug 2019 19:33:39 +0000 (12:33 -0700)]
Reformat so it shows up/looks nice when "help $alu" and "help $alu+"

5 years agoDisable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g all", fixes...
Clifford Wolf [Fri, 9 Aug 2019 17:17:23 +0000 (19:17 +0200)]
Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g all", fixes #1273

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1267 from whitequark/proc_prune-fix-1243
whitequark [Fri, 9 Aug 2019 17:10:46 +0000 (17:10 +0000)]
Merge pull request #1267 from whitequark/proc_prune-fix-1243

proc_prune: fix handling of exactly identical assigns

5 years agoA bit more on where $lcu comes from
Eddie Hung [Fri, 9 Aug 2019 16:50:47 +0000 (09:50 -0700)]
A bit more on where $lcu comes from

5 years agoAdd more comments
Eddie Hung [Fri, 9 Aug 2019 16:48:17 +0000 (09:48 -0700)]
Add more comments

5 years agoAdd __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro
Eddie Hung [Fri, 9 Aug 2019 16:17:35 +0000 (09:17 -0700)]
Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro

5 years agoABC requires it like this
Miodrag Milanovic [Fri, 9 Aug 2019 06:54:17 +0000 (08:54 +0200)]
ABC requires it like this

5 years agoPropagate parameters for Travis build
Miodrag Milanovic [Fri, 9 Aug 2019 06:06:14 +0000 (08:06 +0200)]
Propagate parameters for Travis build

5 years agoAdd a few comments to document $alu and $lcu
Eddie Hung [Thu, 8 Aug 2019 17:05:28 +0000 (10:05 -0700)]
Add a few comments to document $alu and $lcu

5 years agoMerge pull request #1264 from YosysHQ/eddie/fix_1254
Eddie Hung [Thu, 8 Aug 2019 14:58:33 +0000 (07:58 -0700)]
Merge pull request #1264 from YosysHQ/eddie/fix_1254

opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)

5 years agoMerge pull request #1266 from YosysHQ/eddie/ice40_full_adder
Eddie Hung [Thu, 8 Aug 2019 14:58:11 +0000 (07:58 -0700)]
Merge pull request #1266 from YosysHQ/eddie/ice40_full_adder

Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER

5 years agoproc_prune: fix handling of exactly identical assigns.
whitequark [Thu, 8 Aug 2019 05:28:01 +0000 (05:28 +0000)]
proc_prune: fix handling of exactly identical assigns.

Before this commit, in a process like:
   process $proc$bug.v:8$3
     assign $foo \bar
     switch \sel
       case 1'1
         assign $foo 1'1
         assign $foo 1'1
       case
         assign $foo 1'0
     end
   end
both of the "assign $foo 1'1" would incorrectly be removed.

Fixes #1243.

5 years agoRemove dump call
Eddie Hung [Thu, 8 Aug 2019 04:36:02 +0000 (21:36 -0700)]
Remove dump call

5 years agoMove tests/various/opt* into tests/opt/
Eddie Hung [Thu, 8 Aug 2019 04:35:48 +0000 (21:35 -0700)]
Move tests/various/opt* into tests/opt/

5 years agoRemove ice40_unlut call, simply do equiv_opt on synth_ice40
Eddie Hung [Thu, 8 Aug 2019 04:33:56 +0000 (21:33 -0700)]
Remove ice40_unlut call, simply do equiv_opt on synth_ice40

5 years agoAdd testcase from removed opt_ff.{v,ys}
Eddie Hung [Thu, 8 Aug 2019 04:31:32 +0000 (21:31 -0700)]
Add testcase from removed opt_ff.{v,ys}

5 years agoRemove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but run
Eddie Hung [Wed, 7 Aug 2019 23:48:38 +0000 (16:48 -0700)]
Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but run

5 years agoAllow whitebox modules to be overwritten
Eddie Hung [Wed, 7 Aug 2019 23:40:24 +0000 (16:40 -0700)]
Allow whitebox modules to be overwritten

5 years agoUpdate CHANGELOG
Eddie Hung [Wed, 7 Aug 2019 23:33:46 +0000 (16:33 -0700)]
Update CHANGELOG

5 years agoAdd ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER
Eddie Hung [Wed, 7 Aug 2019 23:27:24 +0000 (16:27 -0700)]
Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER

5 years agoAdd test
Eddie Hung [Wed, 7 Aug 2019 23:27:07 +0000 (16:27 -0700)]
Add test

5 years agoRemove ice40_unlut
Eddie Hung [Wed, 7 Aug 2019 21:52:56 +0000 (14:52 -0700)]
Remove ice40_unlut

5 years agoWrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER
Eddie Hung [Wed, 7 Aug 2019 21:50:59 +0000 (14:50 -0700)]
Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER

5 years agoopt_lut to ignore LUT cells, or those that drive bits, with (* keep *)
Eddie Hung [Wed, 7 Aug 2019 20:12:28 +0000 (13:12 -0700)]
opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)

5 years agoMerge pull request #1248 from YosysHQ/eddie/abc9_speedup
Eddie Hung [Wed, 7 Aug 2019 19:25:26 +0000 (12:25 -0700)]
Merge pull request #1248 from YosysHQ/eddie/abc9_speedup

abc9: speedup by using using "clean" more efficiently

5 years agosubstr() -> compare()
Eddie Hung [Wed, 7 Aug 2019 19:20:08 +0000 (12:20 -0700)]
substr() -> compare()

5 years agoRTLIL::S{0,1} -> State::S{0,1} for headers
Eddie Hung [Wed, 7 Aug 2019 18:14:03 +0000 (11:14 -0700)]
RTLIL::S{0,1} -> State::S{0,1} for headers

5 years agoRTLIL::S{0,1} -> State::S{0,1}
Eddie Hung [Wed, 7 Aug 2019 18:12:38 +0000 (11:12 -0700)]
RTLIL::S{0,1} -> State::S{0,1}

5 years agoMerge remote-tracking branch 'origin/master' into eddie/cleanup
Eddie Hung [Wed, 7 Aug 2019 18:11:50 +0000 (11:11 -0700)]
Merge remote-tracking branch 'origin/master' into eddie/cleanup

5 years agoRemove std:: namespace
Eddie Hung [Wed, 7 Aug 2019 18:11:14 +0000 (11:11 -0700)]
Remove std:: namespace

5 years ago'make clean' to not remove anything abc
Eddie Hung [Wed, 7 Aug 2019 18:10:18 +0000 (11:10 -0700)]
'make clean' to not remove anything abc

5 years agostoi -> atoi
Eddie Hung [Wed, 7 Aug 2019 18:09:17 +0000 (11:09 -0700)]
stoi -> atoi

5 years agoMerge branch 'master' into firrtl_err_on_unsupported_cell
Jim Lawson [Wed, 7 Aug 2019 17:14:45 +0000 (10:14 -0700)]
Merge branch 'master' into firrtl_err_on_unsupported_cell

# Conflicts:
# backends/firrtl/firrtl.cc

5 years agoAdd comment
Eddie Hung [Tue, 6 Aug 2019 20:20:32 +0000 (13:20 -0700)]
Add comment

5 years agoRevert "Add TODO"
Eddie Hung [Tue, 6 Aug 2019 20:19:21 +0000 (13:19 -0700)]
Revert "Add TODO"

This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.

5 years agoAdd TODO
Eddie Hung [Fri, 2 Aug 2019 05:30:10 +0000 (22:30 -0700)]
Add TODO

5 years agoCompute box_lookup just once
Eddie Hung [Fri, 2 Aug 2019 05:21:56 +0000 (22:21 -0700)]
Compute box_lookup just once

5 years agoRun "clean" on mapped_mod in its own design
Eddie Hung [Fri, 2 Aug 2019 05:21:30 +0000 (22:21 -0700)]
Run "clean" on mapped_mod in its own design

5 years agoRun "clean -purge" on holes_module in its own design
Eddie Hung [Fri, 2 Aug 2019 05:21:14 +0000 (22:21 -0700)]
Run "clean -purge" on holes_module in its own design

5 years agoMerge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes
David Shah [Wed, 7 Aug 2019 14:35:29 +0000 (15:35 +0100)]
Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes

ecp5: Make cells_sim.v consistent with nextpnr

5 years agoAutomatically prune init attributes in verific front-end, fixes #1237
Clifford Wolf [Wed, 7 Aug 2019 13:31:49 +0000 (15:31 +0200)]
Automatically prune init attributes in verific front-end, fixes #1237

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoecp5: Make cells_sim.v consistent with nextpnr
David Shah [Wed, 7 Aug 2019 13:19:31 +0000 (14:19 +0100)]
ecp5: Make cells_sim.v consistent with nextpnr

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge pull request #1213 from YosysHQ/eddie/wreduce_add
Clifford Wolf [Wed, 7 Aug 2019 12:27:35 +0000 (14:27 +0200)]
Merge pull request #1213 from YosysHQ/eddie/wreduce_add

wreduce/opt_expr: improve width reduction for $add and $sub cells

5 years agoMerge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor
Clifford Wolf [Wed, 7 Aug 2019 10:31:32 +0000 (12:31 +0200)]
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor

 Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.

5 years agoMerge pull request #1249 from mmicko/anlogic_fix
Clifford Wolf [Wed, 7 Aug 2019 10:30:52 +0000 (12:30 +0200)]
Merge pull request #1249 from mmicko/anlogic_fix

anlogic : Fix alu mapping

5 years agoMerge pull request #1252 from YosysHQ/clifford/fix1231
Clifford Wolf [Wed, 7 Aug 2019 10:14:54 +0000 (12:14 +0200)]
Merge pull request #1252 from YosysHQ/clifford/fix1231

Fix handling of functions/tasks without top-level begin-end block

5 years agoMerge pull request #1253 from YosysHQ/clifford/check
Clifford Wolf [Wed, 7 Aug 2019 10:14:41 +0000 (12:14 +0200)]
Merge pull request #1253 from YosysHQ/clifford/check

Be less aggressive with running design->check()

5 years agoMerge pull request #1257 from YosysHQ/clifford/cellcosts
Clifford Wolf [Wed, 7 Aug 2019 10:13:50 +0000 (12:13 +0200)]
Merge pull request #1257 from YosysHQ/clifford/cellcosts

Redesign of cell cost API

5 years agoUpdate CHANGELOG
David Shah [Wed, 7 Aug 2019 09:56:32 +0000 (10:56 +0100)]
Update CHANGELOG

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge pull request #1241 from YosysHQ/clifford/jsonfix
David Shah [Wed, 7 Aug 2019 09:40:38 +0000 (10:40 +0100)]
Merge pull request #1241 from YosysHQ/clifford/jsonfix

Improved JSON attr/param encoding

5 years agoTweak default gate costs, cleanup "stat -tech cmos"
Clifford Wolf [Wed, 7 Aug 2019 08:25:51 +0000 (10:25 +0200)]
Tweak default gate costs, cleanup "stat -tech cmos"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoIdString::str().substr() -> IdString::substr()
Eddie Hung [Wed, 7 Aug 2019 02:08:33 +0000 (19:08 -0700)]
IdString::str().substr() -> IdString::substr()

5 years agoFix typos
Eddie Hung [Wed, 7 Aug 2019 02:07:45 +0000 (19:07 -0700)]
Fix typos

5 years agoFix spacing
Eddie Hung [Tue, 6 Aug 2019 23:47:55 +0000 (16:47 -0700)]
Fix spacing

5 years agoUse std::stoi instead of atoi(<str>.c_str())
Eddie Hung [Tue, 6 Aug 2019 23:45:48 +0000 (16:45 -0700)]
Use std::stoi instead of atoi(<str>.c_str())

5 years agoUse IdString::begins_with()
Eddie Hung [Tue, 6 Aug 2019 23:42:25 +0000 (16:42 -0700)]
Use IdString::begins_with()

5 years agoRTLIL::S{0,1} -> State::S{0,1}
Eddie Hung [Tue, 6 Aug 2019 23:23:37 +0000 (16:23 -0700)]
RTLIL::S{0,1} -> State::S{0,1}

5 years agoUse State::S{0,1}
Eddie Hung [Tue, 6 Aug 2019 23:22:47 +0000 (16:22 -0700)]
Use State::S{0,1}

5 years agoMake liberal use of IdString.in()
Eddie Hung [Tue, 6 Aug 2019 23:18:18 +0000 (16:18 -0700)]
Make liberal use of IdString.in()

5 years agoRedesign of cell cost API
Clifford Wolf [Tue, 6 Aug 2019 23:12:14 +0000 (01:12 +0200)]
Redesign of cell cost API

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoCleanup opt_expr.cc
Eddie Hung [Tue, 6 Aug 2019 23:04:21 +0000 (16:04 -0700)]
Cleanup opt_expr.cc

5 years agoAdd signed opt_expr tests
Eddie Hung [Tue, 6 Aug 2019 22:40:30 +0000 (15:40 -0700)]
Add signed opt_expr tests

5 years agoAdd signed test
Eddie Hung [Tue, 6 Aug 2019 22:38:43 +0000 (15:38 -0700)]
Add signed test

5 years agoMove LSB-trimming functionality from wreduce to opt_expr
Eddie Hung [Tue, 6 Aug 2019 22:25:50 +0000 (15:25 -0700)]
Move LSB-trimming functionality from wreduce to opt_expr

5 years agoAdd SigSpec::extract_end() convenience function
Eddie Hung [Tue, 6 Aug 2019 22:25:11 +0000 (15:25 -0700)]
Add SigSpec::extract_end() convenience function

5 years agoRestore original SigSpec::extract()
Eddie Hung [Tue, 6 Aug 2019 22:24:55 +0000 (15:24 -0700)]
Restore original SigSpec::extract()

5 years agoMove LSB tests from wreduce to opt_expr
Eddie Hung [Tue, 6 Aug 2019 22:24:49 +0000 (15:24 -0700)]
Move LSB tests from wreduce to opt_expr

5 years agoMerge remote-tracking branch 'origin/master' into eddie/wreduce_add
Eddie Hung [Tue, 6 Aug 2019 21:50:00 +0000 (14:50 -0700)]
Merge remote-tracking branch 'origin/master' into eddie/wreduce_add

5 years agoMerge pull request #1232 from YosysHQ/dave/write_gzip
David Shah [Tue, 6 Aug 2019 18:05:35 +0000 (19:05 +0100)]
Merge pull request #1232 from YosysHQ/dave/write_gzip

Add support for writing gzip-compressed files

5 years agoBe less aggressive with running design->check()
Clifford Wolf [Tue, 6 Aug 2019 17:21:37 +0000 (19:21 +0200)]
Be less aggressive with running design->check()

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd test for writing gzip-compressed files
David Shah [Wed, 31 Jul 2019 12:58:27 +0000 (13:58 +0100)]
Add test for writing gzip-compressed files

Signed-off-by: David Shah <dave@ds0.me>
5 years agoAdd support for writing gzip-compressed files
David Shah [Mon, 29 Jul 2019 08:28:31 +0000 (09:28 +0100)]
Add support for writing gzip-compressed files

Signed-off-by: David Shah <dave@ds0.me>
5 years agoFix handling of functions/tasks without top-level begin-end block, fixes #1231
Clifford Wolf [Tue, 6 Aug 2019 16:06:14 +0000 (18:06 +0200)]
Fix handling of functions/tasks without top-level begin-end block, fixes #1231

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1251 from YosysHQ/clifford/nmux
Clifford Wolf [Tue, 6 Aug 2019 13:18:18 +0000 (15:18 +0200)]
Merge pull request #1251 from YosysHQ/clifford/nmux

Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs

5 years agoAdd $_NMUX_, add "abc -g cmos", add proper cmos cell costs
Clifford Wolf [Tue, 6 Aug 2019 02:47:55 +0000 (04:47 +0200)]
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoanlogic : Fix alu mapping
Miodrag Milanovic [Sat, 3 Aug 2019 12:47:33 +0000 (14:47 +0200)]
anlogic : Fix alu mapping

5 years agoMerge pull request #1242 from jfng/fix-proc_prune-partial
whitequark [Sat, 3 Aug 2019 07:08:41 +0000 (07:08 +0000)]
Merge pull request #1242 from jfng/fix-proc_prune-partial

proc_prune: Promote partially redundant assignments.

5 years agoMerge pull request #1238 from mmicko/vsbuild_fix
Clifford Wolf [Fri, 2 Aug 2019 15:07:39 +0000 (17:07 +0200)]
Merge pull request #1238 from mmicko/vsbuild_fix

Visual Studio build fix

5 years agoMerge pull request #1239 from mmicko/mingw_fix
Clifford Wolf [Fri, 2 Aug 2019 14:37:57 +0000 (16:37 +0200)]
Merge pull request #1239 from mmicko/mingw_fix

Fix formatting for msys2 mingw build

5 years agoMerge pull request #1236 from YosysHQ/eddie/xc6s_brams_map
Eddie Hung [Thu, 1 Aug 2019 16:38:55 +0000 (09:38 -0700)]
Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map

xc6s_brams_map.v: RST -> RSTBRST for RAMB8BWER

5 years agoFix linking issue for new mxe and pthread
Miodrag Milanovic [Wed, 31 Jul 2019 16:02:27 +0000 (18:02 +0200)]
Fix linking issue for new mxe and pthread

5 years agoFix yosys linking for mxe
Miodrag Milanovic [Wed, 31 Jul 2019 15:31:07 +0000 (17:31 +0200)]
Fix yosys linking for mxe

5 years agoNew mxe hacks needed to support 2ca237e
Miodrag Milanovic [Wed, 31 Jul 2019 15:30:48 +0000 (17:30 +0200)]
New mxe hacks needed to support 2ca237e

5 years agoFix formatting for msys2 mingw build using GetSize
Miodrag Milanovic [Wed, 31 Jul 2019 09:49:48 +0000 (11:49 +0200)]
Fix formatting for msys2 mingw build using GetSize

5 years agoproc_prune: Promote partially redundant assignments.
Jean-François Nguyen [Wed, 31 Jul 2019 12:26:09 +0000 (14:26 +0200)]
proc_prune: Promote partially redundant assignments.

5 years agoUpdate JSON front-end to process new attr/param encoding
Clifford Wolf [Thu, 1 Aug 2019 10:48:22 +0000 (12:48 +0200)]
Update JSON front-end to process new attr/param encoding

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImplement improved JSON attr/param encoding
Clifford Wolf [Thu, 1 Aug 2019 10:34:52 +0000 (12:34 +0200)]
Implement improved JSON attr/param encoding

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoSupport explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semanti...
Jim Lawson [Wed, 31 Jul 2019 16:27:38 +0000 (09:27 -0700)]
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.

5 years agoMerge pull request #1233 from YosysHQ/clifford/defer
Clifford Wolf [Wed, 31 Jul 2019 11:30:52 +0000 (13:30 +0200)]
Merge pull request #1233 from YosysHQ/clifford/defer

Call "read_verilog" with -defer from "read"

5 years agoVisual Studio build fix
Miodrag Milanovic [Wed, 31 Jul 2019 07:10:24 +0000 (09:10 +0200)]
Visual Studio build fix