Benedikt Tutzer [Wed, 1 Aug 2018 06:04:08 +0000 (08:04 +0200)]
removed unused library and already present compiler flag
Benedikt Tutzer [Tue, 10 Jul 2018 10:51:02 +0000 (12:51 +0200)]
Added Monitor class that can monitor all changes in a Design or in a Module
Benedikt Tutzer [Tue, 10 Jul 2018 06:52:36 +0000 (08:52 +0200)]
added destructors for wires and cells
Benedikt Tutzer [Mon, 9 Jul 2018 14:02:10 +0000 (16:02 +0200)]
removed debug output
Benedikt Tutzer [Mon, 9 Jul 2018 14:01:56 +0000 (16:01 +0200)]
commands can now be run on arbitrary designs, not only on the active one
Benedikt Tutzer [Mon, 9 Jul 2018 13:48:06 +0000 (15:48 +0200)]
multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues
Benedikt Tutzer [Thu, 28 Jun 2018 13:07:21 +0000 (15:07 +0200)]
Introduced namespace and removed class-prefixes to increase readability
Benedikt Tutzer [Thu, 28 Jun 2018 12:44:28 +0000 (14:44 +0200)]
changed references from hash-ids to IdString names
Benedikt Tutzer [Mon, 25 Jun 2018 15:08:29 +0000 (17:08 +0200)]
added wrappers for Design, Modules, Cells and Wires
Benedikt Tutzer [Fri, 22 Jun 2018 09:15:03 +0000 (11:15 +0200)]
added ENABLE_PYTHON option in build environment
Clifford Wolf [Thu, 21 Jun 2018 14:56:55 +0000 (16:56 +0200)]
Add simplified "read" command, enable extnets in implicit Verific import
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 20 Jun 2018 21:45:26 +0000 (23:45 +0200)]
Merge branch 'master' of github.com:YosysHQ/yosys
Clifford Wolf [Wed, 20 Jun 2018 21:45:01 +0000 (23:45 +0200)]
Add automatic verific import in hierarchy command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 20 Jun 2018 18:40:59 +0000 (20:40 +0200)]
Merge pull request #572 from q3k/q3k/fix-protobuf-build
Fix protobuf build
Sergiusz Bazanski [Wed, 20 Jun 2018 18:28:43 +0000 (19:28 +0100)]
Fix protobuf build
Clifford Wolf [Tue, 19 Jun 2018 13:02:04 +0000 (15:02 +0200)]
Merge pull request #571 from q3k/q3k/protobuf-backend
Add Protobuf backend
Serge Bazanski [Tue, 19 Jun 2018 12:34:56 +0000 (13:34 +0100)]
Add Protobuf backend
Signed-off-by: Serge Bazanski <q3k@symbioticeda.com>
Clifford Wolf [Tue, 19 Jun 2018 12:29:38 +0000 (14:29 +0200)]
Be slightly less aggressive in "deminout" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 19 Jun 2018 11:47:39 +0000 (13:47 +0200)]
Merge pull request #570 from edcote/patch-4
Include module name for area summary stats
Edmond Cote [Tue, 19 Jun 2018 00:29:01 +0000 (17:29 -0700)]
Include module name for area summary stats
The PR prints the name of the module when displaying the final area count.
Pros:
- Easier for the user to `grep` for area information about a specific module
Cons:
- Arguably more verbose, less "pretty" than author desires
Verification:
~~~~
30c30
< Chip area for this module: 20616.349000
---
> Chip area for module '$paramod$
d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000
70c70
< Chip area for this module: 88.697700
---
> Chip area for module '\picorv32_axi_adapter': 88.697700
102c102
< Chip area for this module: 20705.046700
---
> Chip area for top module '\picorv32_axi': 20705.046700
~~~~
Clifford Wolf [Fri, 15 Jun 2018 16:56:44 +0000 (18:56 +0200)]
Bugfix in liberty parser (as suggested by aiju in #569)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 13 Jun 2018 11:35:10 +0000 (13:35 +0200)]
Add "synth_ice40 -json"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 11 Jun 2018 16:10:12 +0000 (18:10 +0200)]
Fix ice40_opt for cases where a port is connected to a signal with width != 1
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 6 Jun 2018 09:57:41 +0000 (11:57 +0200)]
Merge pull request #561 from udif/pr_skip_typo
Fixed typo (sikp -> skip)
Udi Finkelstein [Tue, 5 Jun 2018 14:52:36 +0000 (17:52 +0300)]
Fixed typo (sikp -> skip)
Clifford Wolf [Fri, 1 Jun 2018 11:25:42 +0000 (13:25 +0200)]
Add (* gclk *) attribute support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 1 Jun 2018 09:57:28 +0000 (11:57 +0200)]
Add setundef -anyseq / -anyconst support to -undriven mode
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 1 Jun 2018 09:49:58 +0000 (11:49 +0200)]
Add "setundef -anyconst"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 31 May 2018 16:09:31 +0000 (18:09 +0200)]
Bugfix in handling of array instances with empty ports
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 30 May 2018 12:17:36 +0000 (14:17 +0200)]
Update examples/cmos/counter.ys to use "synth" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 30 May 2018 11:17:09 +0000 (13:17 +0200)]
Make -nordff the default in "prep"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 30 May 2018 11:04:40 +0000 (13:04 +0200)]
Update ABC to git rev
6df1396
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 28 May 2018 15:16:15 +0000 (17:16 +0200)]
Disable memory_dff for initialized FFs
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 28 May 2018 14:42:06 +0000 (16:42 +0200)]
Add some cleanup code to memory_nordff
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 28 May 2018 11:36:35 +0000 (13:36 +0200)]
Add comment to VIPER #13453 work-around
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 25 May 2018 13:41:45 +0000 (15:41 +0200)]
Fix Verific handling of single-bit anyseq/anyconst wires
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 24 May 2018 16:13:38 +0000 (18:13 +0200)]
Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 24 May 2018 15:07:06 +0000 (17:07 +0200)]
Fix verific handling of anyconst/anyseq attributes
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 19 May 2018 06:42:45 +0000 (08:42 +0200)]
Merge pull request #454 from rqou/emscripten-and-abc
Add option to statically link abc; emscripten fixes
Robert Ou [Sat, 19 May 2018 05:45:43 +0000 (22:45 -0700)]
Force abc to align memory to 8 bytes
Apparently abc has a memory pool implementation that by default returns
memory that is unaligned. There is a workaround in the abc makefile that
uses uname to look for "arm" specifically and then sets the alignment.
However, ARM is not the only platform that requires proper alignment
(e.g. emscripten does too). For now, pessimistically force the alignment
for 8 bytes all the time (somehow 4 wasn't enough for fixing emscripten
despite being approximately a 32-bit platform).
Robert Ou [Tue, 14 Nov 2017 12:09:32 +0000 (04:09 -0800)]
Modify emscripten main to mount nodefs and to run arg as a script
Robert Ou [Sat, 31 Mar 2018 21:50:21 +0000 (14:50 -0700)]
Force abc to be linked statically and without threads in emscripten
Robert Ou [Tue, 14 Nov 2017 12:08:36 +0000 (04:08 -0800)]
Fix infinite loop in abc command under emscripten
Robert Ou [Tue, 14 Nov 2017 12:08:07 +0000 (04:08 -0800)]
Fix reading techlibs under emscripten
Robert Ou [Sat, 19 May 2018 05:42:24 +0000 (22:42 -0700)]
Add options to disable abc's usage of pthreads and readline
Robert Ou [Tue, 14 Nov 2017 10:19:21 +0000 (02:19 -0800)]
Add an option to statically link abc into yosys
This is currently incomplete because the output filter no longer works.
Robert Ou [Sat, 19 May 2018 05:01:25 +0000 (22:01 -0700)]
Makefile: Make abc always use stdint.h
Clifford Wolf [Thu, 17 May 2018 12:10:24 +0000 (14:10 +0200)]
Merge pull request #550 from jimparis/yosys-upstream
Support SystemVerilog `` extension for macros
Clifford Wolf [Thu, 17 May 2018 12:03:58 +0000 (14:03 +0200)]
Merge pull request #551 from olofk/ice40_cells_sim_ports
Avoid mixing module port declaration styles in ice40 cells_sim.v
Olof Kindgren [Thu, 17 May 2018 11:54:40 +0000 (13:54 +0200)]
Avoid mixing module port declaration styles in ice40 cells_sim.v
The current code requires workarounds for several simulators
For modelsim, the file must be compiled with -mixedansiports and
xsim needs --relax.
Jim Paris [Thu, 17 May 2018 04:09:56 +0000 (00:09 -0400)]
Support SystemVerilog `` extension for macros
Jim Paris [Thu, 17 May 2018 04:06:49 +0000 (00:06 -0400)]
Skip spaces around macro arguments
Clifford Wolf [Tue, 15 May 2018 17:27:00 +0000 (19:27 +0200)]
Fix handling of anyconst/anyseq attrs in VHDL code via Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 15 May 2018 12:19:05 +0000 (14:19 +0200)]
Remove mercurial from build instructions
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 15 May 2018 12:02:27 +0000 (14:02 +0200)]
Fix iopadmap for loops between tristate IO buffers
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 15 May 2018 11:13:43 +0000 (13:13 +0200)]
Fix iopadmap for cases where IO pins already have buffers on them
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 13 May 2018 14:36:12 +0000 (16:36 +0200)]
Some cleanups in setundef.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 13 May 2018 11:29:18 +0000 (13:29 +0200)]
Use $(OS) in makefile to check for Darwin
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 13 May 2018 11:27:14 +0000 (13:27 +0200)]
Merge pull request #505 from thefallenidealist/FreeBSD_build
FreeBSD build
Christian Krämer [Sat, 5 May 2018 11:02:44 +0000 (13:02 +0200)]
Add "#ifdef __FreeBSD__"
(Re-commit
e3575a8 with corrected author field)
Clifford Wolf [Sun, 13 May 2018 11:06:36 +0000 (13:06 +0200)]
Revert "Add "#ifdef __FreeBSD__""
This reverts commit
e3575a86c525f2511902e7022893c3923ba8093e.
Sergiusz Bazanski [Sat, 12 May 2018 18:53:24 +0000 (19:53 +0100)]
Also interpret '&' in liberty functions
Clifford Wolf [Sat, 12 May 2018 13:18:27 +0000 (15:18 +0200)]
Add optimization of tristate buffer with constant control input
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 12 May 2018 11:59:13 +0000 (13:59 +0200)]
Add "hierarchy -simcheck"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Johnny Sorocil [Sun, 6 May 2018 16:22:18 +0000 (18:22 +0200)]
update README
Johnny Sorocil [Sun, 6 May 2018 13:26:23 +0000 (15:26 +0200)]
autotest.sh: Change from /bin/bash to /usr/bin/env bash
This enables running tests on Unix systems which are not shipped with
bash installed in /bin/bash (eg *BSDs and Solaris).
Johnny Sorocil [Sun, 6 May 2018 13:19:44 +0000 (15:19 +0200)]
Enable building on FreeBSD
Clifford Wolf [Sat, 5 May 2018 12:32:04 +0000 (14:32 +0200)]
Further improve handling of zero-length SVA consecutive repetition
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 5 May 2018 11:58:01 +0000 (13:58 +0200)]
Fix handling of zero-length SVA consecutive repetition
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Johnny Sorocil [Sat, 5 May 2018 11:02:44 +0000 (13:02 +0200)]
Add "#ifdef __FreeBSD__"
Clifford Wolf [Fri, 4 May 2018 19:59:31 +0000 (21:59 +0200)]
Add ABC FAQ to "help abc"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 4 May 2018 13:27:28 +0000 (15:27 +0200)]
Add "yosys -e regex" for turning warnings into errors
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 4 May 2018 10:32:30 +0000 (12:32 +0200)]
Merge pull request #537 from mithro/yosys-vpr
Improving Yosys when used with VPR
Clifford Wolf [Thu, 3 May 2018 13:25:59 +0000 (15:25 +0200)]
Replace -ignore_redef with -[no]overwrite
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Dan Gisselquist [Thu, 3 May 2018 10:35:01 +0000 (12:35 +0200)]
Support more character literals
Clifford Wolf [Mon, 30 Apr 2018 17:50:34 +0000 (19:50 +0200)]
Update ABC to git rev
f23ea8e
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 30 Apr 2018 11:02:56 +0000 (13:02 +0200)]
Add "synth_intel --noiopads"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 22 Apr 2018 14:03:26 +0000 (16:03 +0200)]
Add $dlatch support to write_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Tim 'mithro' Ansell [Wed, 18 Apr 2018 23:48:05 +0000 (16:48 -0700)]
Improving vpr output support.
* Support output BLIF for Xilinx architectures.
* Support using .names in BLIF for Xilinx architectures.
* Use the same `NO_LUT` define in both `synth_ice40` and
`synth_xilinx`.
Tim 'mithro' Ansell [Sun, 15 Apr 2018 23:05:52 +0000 (16:05 -0700)]
synth_ice40: Rework the vpr blif output slightly.
Clifford Wolf [Mon, 16 Apr 2018 18:44:26 +0000 (20:44 +0200)]
Add "synth_ice40 -nodffe"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 15 Apr 2018 12:07:21 +0000 (14:07 +0200)]
Add "write_blif -inames -iattr"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 13 Apr 2018 09:52:28 +0000 (11:52 +0200)]
Add statement labels for immediate assertions
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 12 Apr 2018 12:28:28 +0000 (14:28 +0200)]
Allow "property" in immediate assertions
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 12 Apr 2018 12:02:57 +0000 (14:02 +0200)]
Improve Makefile error handling for when abc/ is a hg working copy
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 7 Apr 2018 16:38:42 +0000 (18:38 +0200)]
Add PRIM_HDL_ASSERTION support to Verific importer
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 6 Apr 2018 19:23:47 +0000 (21:23 +0200)]
Fix handling of $global_clocking in Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 6 Apr 2018 12:37:43 +0000 (14:37 +0200)]
Add documentation for anyconst/anyseq/allconst/allseq attribute
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 6 Apr 2018 12:35:11 +0000 (14:35 +0200)]
Add read_verilog anyseq/anyconst/allseq/allconst attribute support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 6 Apr 2018 12:19:55 +0000 (14:19 +0200)]
Add Verific anyseq/anyconst/allseq/allconst attribute support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 6 Apr 2018 12:10:57 +0000 (14:10 +0200)]
Add "verific -autocover"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 6 Apr 2018 11:50:23 +0000 (13:50 +0200)]
Merge pull request #530 from makaimann/set-ram-flags
Set RAM runtime flags for Verific frontend
makaimann [Fri, 6 Apr 2018 00:38:08 +0000 (17:38 -0700)]
Set RAM runtime flags for Verific frontend
Clifford Wolf [Thu, 5 Apr 2018 09:01:32 +0000 (11:01 +0200)]
Added missing dont_use handling for SR FFs to dfflibmap
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 4 Apr 2018 17:27:33 +0000 (19:27 +0200)]
Create issue_template.md
Clifford Wolf [Wed, 4 Apr 2018 16:12:27 +0000 (18:12 +0200)]
Add smtio.py support for parsing SMT2 (_ bvX n) syntax for BitVec constants
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 4 Apr 2018 15:28:07 +0000 (17:28 +0200)]
Fixed -stbv handling in SMT2 back-end
Clifford Wolf [Sun, 1 Apr 2018 13:32:47 +0000 (15:32 +0200)]
Merge pull request #522 from c60k28/master
Fixed broken Quartus backend on dffeas init value, and other updates.
c60k28 [Sun, 1 Apr 2018 04:48:47 +0000 (22:48 -0600)]
Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
Clifford Wolf [Sat, 31 Mar 2018 12:23:57 +0000 (14:23 +0200)]
Remove left-over log_ping debug commands.. oops.
Signed-off-by: Clifford Wolf <clifford@clifford.at>