litex.git
4 years ago.travis.yml: disable python3.5 test (nMigen requires 3.6+).
Florent Kermarrec [Fri, 1 May 2020 19:13:12 +0000 (21:13 +0200)]
.travis.yml: disable python3.5 test (nMigen requires 3.6+).

As discussed in #479.

4 years agoCHANGES: update.
Florent Kermarrec [Fri, 1 May 2020 18:13:05 +0000 (20:13 +0200)]
CHANGES: update.

4 years agocpu/minerva: add pythondata and use it to compile the sources.
Florent Kermarrec [Fri, 1 May 2020 18:12:02 +0000 (20:12 +0200)]
cpu/minerva: add pythondata and use it to compile the sources.

4 years agolitex_setup: add nmigen dependency (used to generate Minerva CPU).
Florent Kermarrec [Fri, 1 May 2020 17:09:32 +0000 (19:09 +0200)]
litex_setup: add nmigen dependency (used to generate Minerva CPU).

This also requires Yosys, but Yosys is already expected to be installed separately.

4 years agoCHANGES: start listing changes for next release.
Florent Kermarrec [Fri, 1 May 2020 17:07:43 +0000 (19:07 +0200)]
CHANGES: start listing changes for next release.

4 years agocpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs.
Florent Kermarrec [Fri, 1 May 2020 10:35:12 +0000 (12:35 +0200)]
cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs.

4 years agocpu/software: move CPU specific software from the BIOS to the CPU directories.
Florent Kermarrec [Fri, 1 May 2020 06:15:17 +0000 (08:15 +0200)]
cpu/software: move CPU specific software from the BIOS to the CPU directories.

This simplifies the integration of the CPUs' software, avoid complex switches in the code,
and is a first step to make CPUs fully pluggable.

The CPU name is no longer present in the crt0 files (for example crt0-vexriscv-ctr.o
becomes crt0-ctr.o) so users building firmwares externally will have to update their
Makefiles to remove the $(CPU) from crt0-$(CPU)-ctr.o.

4 years agocpu/Minerva: Clone the repository locally for now, we need to create a pythondata...
Florent Kermarrec [Fri, 1 May 2020 09:01:50 +0000 (11:01 +0200)]
cpu/Minerva: Clone the repository locally for now, we need to create a pythondata repository.

4 years agointegration/soc: rename usb_cdc to usb_acm.
Florent Kermarrec [Thu, 30 Apr 2020 19:45:53 +0000 (21:45 +0200)]
integration/soc: rename usb_cdc to usb_acm.

As discussed on Discord recently.

4 years agolitex/__init__.py: remove retro-compat > 6 months old.
Florent Kermarrec [Thu, 30 Apr 2020 19:31:58 +0000 (21:31 +0200)]
litex/__init__.py: remove retro-compat > 6 months old.

4 years agosoc: allow passing custom CPU class to SoC.
Florent Kermarrec [Wed, 29 Apr 2020 18:11:47 +0000 (20:11 +0200)]
soc: allow passing custom CPU class to SoC.

Useful to experiment with custom CPU wrappers and a first step to make CPUs plugable.

4 years agoMerge pull request #488 from enjoy-digital/python3.5
enjoy-digital [Wed, 29 Apr 2020 06:48:06 +0000 (08:48 +0200)]
Merge pull request #488 from enjoy-digital/python3.5

travis: add back test on python3.5 (python3.6 is recommended but we c…

4 years agotravis: add back test on python3.5 (python3.6 is recommended but we can try to keep...
Florent Kermarrec [Wed, 29 Apr 2020 06:00:55 +0000 (08:00 +0200)]
travis: add back test on python3.5 (python3.6 is recommended but we can try to keep 3.5 compatibility until we have good reason to no longer support it).

4 years agoMerge pull request #481 from betrusted-io/unfstringify
enjoy-digital [Tue, 28 Apr 2020 17:05:08 +0000 (19:05 +0200)]
Merge pull request #481 from betrusted-io/unfstringify

propose patch to not break litex for python 3.5

4 years agopropose patch to not break litex for python 3.5
bunnie [Tue, 28 Apr 2020 16:34:19 +0000 (00:34 +0800)]
propose patch to not break litex for python 3.5

4 years agocreate first release, add CHANGES and note about Python modules in README.
Florent Kermarrec [Tue, 28 Apr 2020 09:36:44 +0000 (11:36 +0200)]
create first release, add CHANGES and note about Python modules in README.

4 years agocpu/serv: switch to pythondata package instead of local git clone.
Florent Kermarrec [Tue, 28 Apr 2020 08:32:13 +0000 (10:32 +0200)]
cpu/serv: switch to pythondata package instead of local git clone.

4 years agoREADME: update Python minimal version to 3.6.
Florent Kermarrec [Tue, 28 Apr 2020 07:02:59 +0000 (09:02 +0200)]
README: update Python minimal version to 3.6.

4 years agolitex_setup: disable automatic clone of BlackParrot/Microwatt CPUs, reorder LiteX...
Florent Kermarrec [Tue, 28 Apr 2020 06:58:26 +0000 (08:58 +0200)]
litex_setup: disable automatic clone of BlackParrot/Microwatt CPUs, reorder LiteX data.

The support is not fully finished, so let the user install the pythondata for these CPUs manually with pip.

4 years agoMerge pull request #399 from mithro/litex-sm2py
enjoy-digital [Tue, 28 Apr 2020 06:34:19 +0000 (08:34 +0200)]
Merge pull request #399 from mithro/litex-sm2py

Converting LiteX to use Python modules.

4 years agosoc/cpu: add memory_buses to cpus and use them in add_sdram.
Florent Kermarrec [Mon, 27 Apr 2020 21:51:17 +0000 (23:51 +0200)]
soc/cpu: add memory_buses to cpus and use them in add_sdram.

This allows the CPU to have direct buses to the memory and replace the Rocket specific code.

4 years agosoc/cpu: rename cpu.buses to cpu.periph_buses.
Florent Kermarrec [Mon, 27 Apr 2020 21:08:15 +0000 (23:08 +0200)]
soc/cpu: rename cpu.buses to cpu.periph_buses.

4 years agoMerge branch 'master' into litex-sm2py
enjoy-digital [Mon, 27 Apr 2020 20:24:10 +0000 (22:24 +0200)]
Merge branch 'master' into litex-sm2py

4 years agoMerge pull request #477 from shuffle2/patch-1
enjoy-digital [Mon, 27 Apr 2020 19:07:27 +0000 (21:07 +0200)]
Merge pull request #477 from shuffle2/patch-1

diamond: fix include paths

4 years agodiamond: fix include paths
shuffle2 [Mon, 27 Apr 2020 18:14:18 +0000 (11:14 -0700)]
diamond: fix include paths

include paths given via tcl script need semicolon separators and forward slash as directory separator (even on windows)

4 years agosoc/cpu: simplify integration of CPU without interrupts (and automatically use UART_P...
Florent Kermarrec [Mon, 27 Apr 2020 17:06:16 +0000 (19:06 +0200)]
soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case).

4 years agoMerge pull request #473 from fjullien/memusage
enjoy-digital [Mon, 27 Apr 2020 16:24:43 +0000 (18:24 +0200)]
Merge pull request #473 from fjullien/memusage

bios: print memory usage

4 years agobios: print memory usage
Franck Jullien [Sat, 25 Apr 2020 21:22:38 +0000 (23:22 +0200)]
bios: print memory usage

Print memory usage during the compilation of bios.elf.

4 years agotools/litex_sim: use similar analyzer configuration than wiki.
Florent Kermarrec [Mon, 27 Apr 2020 13:08:48 +0000 (15:08 +0200)]
tools/litex_sim: use similar analyzer configuration than wiki.

4 years agoMerge pull request #476 from enjoy-digital/serv
enjoy-digital [Mon, 27 Apr 2020 11:59:28 +0000 (13:59 +0200)]
Merge pull request #476 from enjoy-digital/serv

Add SERV support (The SErial RISC-V CPU)

4 years agosoftware/irq: cleanup and make explicit that irqs are not supported with Microwatt...
Florent Kermarrec [Mon, 27 Apr 2020 11:46:12 +0000 (13:46 +0200)]
software/irq: cleanup and make explicit that irqs are not supported with Microwatt and SERV, fix compilation warning.

4 years agoserv: connect reset.
Florent Kermarrec [Mon, 27 Apr 2020 11:26:45 +0000 (13:26 +0200)]
serv: connect reset.

4 years agobuild/icestorm: add verilog_read -defer option to yosys script (changes similar the...
Florent Kermarrec [Mon, 27 Apr 2020 11:17:53 +0000 (13:17 +0200)]
build/icestorm: add verilog_read -defer option to yosys script (changes similar the ones applied to trellis).

4 years agoMerge pull request #475 from gregdavill/read_verilog_defer
enjoy-digital [Mon, 27 Apr 2020 11:13:37 +0000 (13:13 +0200)]
Merge pull request #475 from gregdavill/read_verilog_defer

build/trellis: add verilog_read -defer option to yosys script

4 years agobuild/trellis: add verilog_read -defer option to yosys script
Greg Davill [Mon, 27 Apr 2020 10:40:25 +0000 (20:10 +0930)]
build/trellis: add verilog_read -defer option to yosys script

4 years agoserv: update copyrights (Greg Davill found the typos/issues).
Florent Kermarrec [Mon, 27 Apr 2020 08:27:44 +0000 (10:27 +0200)]
serv: update copyrights (Greg Davill found the typos/issues).

4 years agoserv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :).
Florent Kermarrec [Sun, 26 Apr 2020 19:05:47 +0000 (21:05 +0200)]
serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :).

4 years agoserv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks...
Florent Kermarrec [Sun, 26 Apr 2020 14:26:15 +0000 (16:26 +0200)]
serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill).

4 years agobios/sdram: reduce number of scan loops during cdly scan to speed it up.
Florent Kermarrec [Sat, 25 Apr 2020 10:51:33 +0000 (12:51 +0200)]
bios/sdram: reduce number of scan loops during cdly scan to speed it up.

4 years agotargets/kcu105: use cmd_latency=1.
Florent Kermarrec [Sat, 25 Apr 2020 10:12:27 +0000 (12:12 +0200)]
targets/kcu105: use cmd_latency=1.

4 years agobios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_l...
Florent Kermarrec [Sat, 25 Apr 2020 10:11:10 +0000 (12:11 +0200)]
bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal.

We need to provide enough information to ease support and understand the issue. The write leveling/read leveling
are doing there best to calibrate the DRAM correctly and memtest gives the final result.

4 years agotargets/kc705: manual DDRPHY_CMD_DELAY no longer needed.
Florent Kermarrec [Sat, 25 Apr 2020 09:03:04 +0000 (11:03 +0200)]
targets/kc705: manual DDRPHY_CMD_DELAY no longer needed.

4 years agobios/sdram: review/cleanup Command/Clock calibration, set window at the start instead...
Florent Kermarrec [Sat, 25 Apr 2020 09:00:21 +0000 (11:00 +0200)]
bios/sdram: review/cleanup Command/Clock calibration, set window at the start instead of middle.

Working on KC705 that previously required manual adjustment.

4 years agoMerge pull request #472 from antmicro/jboc/sdram-calibration
enjoy-digital [Sat, 25 Apr 2020 07:59:08 +0000 (09:59 +0200)]
Merge pull request #472 from antmicro/jboc/sdram-calibration

bios/sdram: add automatic cdly calibration during write leveling

4 years agoMerge pull request #470 from antmicro/jboc/sdram-eeprom-timings
enjoy-digital [Sat, 25 Apr 2020 06:27:00 +0000 (08:27 +0200)]
Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings

litex_sim: add option to create SDRAM module from SPD data

4 years agobios/sdram: add automatic cdly calibration during write leveling
Jędrzej Boczar [Thu, 23 Apr 2020 11:52:28 +0000 (13:52 +0200)]
bios/sdram: add automatic cdly calibration during write leveling

4 years agoinitial SERV integration.
Florent Kermarrec [Thu, 23 Apr 2020 06:04:04 +0000 (08:04 +0200)]
initial SERV integration.

4 years agosoc/cores/spi: add optional aligned mode.
Florent Kermarrec [Wed, 22 Apr 2020 11:15:07 +0000 (13:15 +0200)]
soc/cores/spi: add optional aligned mode.

In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.

4 years agocores/spi: simplify.
Florent Kermarrec [Wed, 22 Apr 2020 10:20:23 +0000 (12:20 +0200)]
cores/spi: simplify.

4 years agobuild/lattice/common: add specific LatticeiCE40SDROutputImpl/LatticeiCE40SDRTristateI...
Florent Kermarrec [Wed, 22 Apr 2020 09:50:55 +0000 (11:50 +0200)]
build/lattice/common: add specific LatticeiCE40SDROutputImpl/LatticeiCE40SDRTristateImpl (thanks @tnt).

4 years agoxilinx/common: use a common SDRTristate implementation for Spartan6, 7-Series and...
Florent Kermarrec [Wed, 22 Apr 2020 08:41:50 +0000 (10:41 +0200)]
xilinx/common: use a common SDRTristate implementation for Spartan6, 7-Series and Ultrascale.

4 years agobuild/xilinx/common: add 7-Series/Ultrascale SDROutput/Input.
Florent Kermarrec [Wed, 22 Apr 2020 08:33:22 +0000 (10:33 +0200)]
build/xilinx/common: add 7-Series/Ultrascale SDROutput/Input.

4 years agolattice/common: add LatticeECP5DDRInput.
Florent Kermarrec [Wed, 22 Apr 2020 08:13:28 +0000 (10:13 +0200)]
lattice/common: add LatticeECP5DDRInput.

4 years agolattice/common: cleanup instances, simplify tritates.
Florent Kermarrec [Wed, 22 Apr 2020 06:45:32 +0000 (08:45 +0200)]
lattice/common: cleanup instances, simplify tritates.

4 years agolattice/common: add LatticeiCE40DDRInput, LatticeiCE40SDROutput and LatticeiCE40SDRInput.
Florent Kermarrec [Wed, 22 Apr 2020 06:41:17 +0000 (08:41 +0200)]
lattice/common: add LatticeiCE40DDRInput, LatticeiCE40SDROutput and LatticeiCE40SDRInput.

4 years agoplatforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables.
Florent Kermarrec [Sat, 18 Apr 2020 09:38:24 +0000 (11:38 +0200)]
platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables.

4 years agotools/remote/etherbone: update import.
Florent Kermarrec [Fri, 17 Apr 2020 19:30:33 +0000 (21:30 +0200)]
tools/remote/etherbone: update import.

4 years agolitex_sim: add option to create SDRAM module from SPD data
Jędrzej Boczar [Fri, 17 Apr 2020 12:52:53 +0000 (14:52 +0200)]
litex_sim: add option to create SDRAM module from SPD data

4 years agotargets: manual define of the SDRAM PHY no longer needed.
Florent Kermarrec [Thu, 16 Apr 2020 09:26:59 +0000 (11:26 +0200)]
targets: manual define of the SDRAM PHY no longer needed.

4 years agobios/sdram: update/simplify with new exported LiteDRAM parameters.
Florent Kermarrec [Thu, 16 Apr 2020 08:23:31 +0000 (10:23 +0200)]
bios/sdram: update/simplify with new exported LiteDRAM parameters.

4 years agolitex_sim: add phytype to PhySettings.
Florent Kermarrec [Thu, 16 Apr 2020 08:22:43 +0000 (10:22 +0200)]
litex_sim: add phytype to PhySettings.

4 years agobuild/generic_programmer: move requests import to do it only when needed.
Florent Kermarrec [Thu, 16 Apr 2020 06:44:36 +0000 (08:44 +0200)]
build/generic_programmer: move requests import to do it only when needed.

4 years agobios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4.
Florent Kermarrec [Wed, 15 Apr 2020 17:30:23 +0000 (19:30 +0200)]
bios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4.

Bitslip software control is now used on ECP5 to move dqs_read.

4 years agosetup.py/install_requires: add requests.
Florent Kermarrec [Wed, 15 Apr 2020 07:27:26 +0000 (09:27 +0200)]
setup.py/install_requires: add requests.

4 years agobuild/generic_programmer: add automatic search/download of flash_proxy in repositorie...
Florent Kermarrec [Wed, 15 Apr 2020 06:59:03 +0000 (08:59 +0200)]
build/generic_programmer: add automatic search/download of flash_proxy in repositories if not available locally.

4 years agoMerge pull request #467 from antmicro/region_type_fix
enjoy-digital [Wed, 15 Apr 2020 05:56:48 +0000 (07:56 +0200)]
Merge pull request #467 from antmicro/region_type_fix

soc_core: Fix region type generation

4 years agosoc_core: Fix region type generation
Mateusz Holenko [Tue, 14 Apr 2020 19:43:58 +0000 (21:43 +0200)]
soc_core: Fix region type generation

Include information about being a linker region.

4 years agostream/AsyncFIFO: add default depth (useful when used for CDC).
Florent Kermarrec [Tue, 14 Apr 2020 15:34:57 +0000 (17:34 +0200)]
stream/AsyncFIFO: add default depth (useful when used for CDC).

4 years agobuild/sim/core/Makefile: add -p to mkdir modules.
Florent Kermarrec [Tue, 14 Apr 2020 10:38:02 +0000 (12:38 +0200)]
build/sim/core/Makefile: add -p to mkdir modules.

4 years agoMerge pull request #464 from mithro/litex-sim-fixes
enjoy-digital [Tue, 14 Apr 2020 10:16:21 +0000 (12:16 +0200)]
Merge pull request #464 from mithro/litex-sim-fixes

Improve the litex_sim Makefiles

4 years agolitex_setup: raise exception on update if repository has been been initialized.
Florent Kermarrec [Sun, 12 Apr 2020 17:46:56 +0000 (19:46 +0200)]
litex_setup: raise exception on update if repository has been been initialized.

4 years agoRemove trailing whitespace.
Tim 'mithro' Ansell [Sun, 12 Apr 2020 17:29:13 +0000 (10:29 -0700)]
Remove trailing whitespace.

4 years agocores: add External Memory Interface (EMIF) Wishbone bridge.
Florent Kermarrec [Sun, 12 Apr 2020 14:34:33 +0000 (16:34 +0200)]
cores: add External Memory Interface (EMIF) Wishbone bridge.

Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.

4 years agoMerge pull request #462 from ironsteel/trellis-12k
enjoy-digital [Sun, 12 Apr 2020 13:49:49 +0000 (15:49 +0200)]
Merge pull request #462 from ironsteel/trellis-12k

Add support for ecp5 12k device in trellis.py

4 years agoboards/targets/ulx3s.py: Update --device option help message
Rangel Ivanov [Sun, 12 Apr 2020 08:51:08 +0000 (11:51 +0300)]
boards/targets/ulx3s.py: Update --device option help message

Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
4 years agobuild/lattice/trellis.py: Add 12k device
Rangel Ivanov [Sun, 12 Apr 2020 08:46:44 +0000 (11:46 +0300)]
build/lattice/trellis.py: Add 12k device

nextpnr adds the --12k option which is the same like
the --25k but with the correct idcode for the 12k devices

Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
4 years agolitex_sim: Find tapcfg from pythondata module.
Tim 'mithro' Ansell [Sun, 12 Apr 2020 01:34:29 +0000 (18:34 -0700)]
litex_sim: Find tapcfg from pythondata module.

4 years agoRemove directories from submodules from MANIFEST.in file.
Tim 'mithro' Ansell [Thu, 9 Apr 2020 06:17:41 +0000 (23:17 -0700)]
Remove directories from submodules from MANIFEST.in file.

4 years agoRename litex-data-XXX-YYY to pythondata-XXX-YYY
Tim 'mithro' Ansell [Mon, 6 Apr 2020 18:16:57 +0000 (11:16 -0700)]
Rename litex-data-XXX-YYY to pythondata-XXX-YYY

4 years agoOnly allow fast-forward pulls.
Tim 'mithro' Ansell [Mon, 30 Mar 2020 00:36:06 +0000 (17:36 -0700)]
Only allow fast-forward pulls.

4 years agoFixing mor1kx data finding.
Tim 'mithro' Ansell [Mon, 30 Mar 2020 00:28:46 +0000 (17:28 -0700)]
Fixing mor1kx data finding.

4 years agoFix typo in error message.
Tim 'mithro' Ansell [Mon, 30 Mar 2020 00:28:20 +0000 (17:28 -0700)]
Fix typo in error message.

4 years agoFix the libcompiler_rt path.
Tim 'mithro' Ansell [Mon, 24 Feb 2020 01:04:47 +0000 (17:04 -0800)]
Fix the libcompiler_rt path.

4 years agoRemove submodules.
Tim 'mithro' Ansell [Mon, 24 Feb 2020 00:06:51 +0000 (16:06 -0800)]
Remove submodules.

4 years agoFix import for data.
Tim 'mithro' Ansell [Sun, 23 Feb 2020 23:29:46 +0000 (15:29 -0800)]
Fix import for data.

4 years agoUse the current directory you are running.
Tim 'mithro' Ansell [Sun, 23 Feb 2020 22:58:45 +0000 (14:58 -0800)]
Use the current directory you are running.

4 years agoMake litex a namespace.
Tim 'mithro' Ansell [Sun, 23 Feb 2020 22:56:51 +0000 (14:56 -0800)]
Make litex a namespace.

4 years agoAdding missing vexriscv CPU.
Tim 'mithro' Ansell [Sun, 23 Feb 2020 22:54:07 +0000 (14:54 -0800)]
Adding missing vexriscv CPU.

4 years agoAdding missing comma.
Tim 'mithro' Ansell [Sun, 23 Feb 2020 22:19:12 +0000 (14:19 -0800)]
Adding missing comma.

4 years agoAdding litex-data-software-compiler_rt as a required package.
Tim 'mithro' Ansell [Sun, 23 Feb 2020 21:39:45 +0000 (13:39 -0800)]
Adding litex-data-software-compiler_rt as a required package.

4 years agoFixed quotes in `litex_setup.py`
Tim 'mithro' Ansell [Sun, 23 Feb 2020 21:38:05 +0000 (13:38 -0800)]
Fixed quotes in `litex_setup.py`

4 years agoConverting litex to use Python modules.
Tim 'mithro' Ansell [Sun, 23 Feb 2020 14:54:48 +0000 (06:54 -0800)]
Converting litex to use Python modules.

4 years agolitex_sim: Rework Makefiles to put output files in gateware directory.
Tim 'mithro' Ansell [Sun, 12 Apr 2020 01:26:15 +0000 (18:26 -0700)]
litex_sim: Rework Makefiles to put output files in gateware directory.

4 years agolitex_sim: Better error messages on failure to load module.
Tim 'mithro' Ansell [Sun, 12 Apr 2020 01:23:40 +0000 (18:23 -0700)]
litex_sim: Better error messages on failure to load module.

4 years agoREADME: LiteDRAM moved to travis-ci.com as others repositories.
Florent Kermarrec [Fri, 10 Apr 2020 17:11:21 +0000 (19:11 +0200)]
README: LiteDRAM moved to travis-ci.com as others repositories.

4 years agoaltera/common: add DDROutput, DDRInput, SDROutput, SDRInput.
Florent Kermarrec [Fri, 10 Apr 2020 13:50:35 +0000 (15:50 +0200)]
altera/common: add DDROutput, DDRInput, SDROutput, SDRInput.

4 years agotargets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
Florent Kermarrec [Fri, 10 Apr 2020 12:41:01 +0000 (14:41 +0200)]
targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.

4 years agobuild/xilinx/common: add Spartan6 specialized DDRInput, SDROutput, SDRInput and SDRTr...
Florent Kermarrec [Fri, 10 Apr 2020 12:38:22 +0000 (14:38 +0200)]
build/xilinx/common: add Spartan6 specialized DDRInput, SDROutput, SDRInput and SDRTristate.

4 years agobuild/io: add SDR Tristate (with infered version) and remove multi-bits support on...
Florent Kermarrec [Fri, 10 Apr 2020 12:37:29 +0000 (14:37 +0200)]
build/io: add SDR Tristate (with infered version) and remove multi-bits support on SDRIO.

4 years agobuild/lattice/common: remove multi-bits support on SDRInput/Output.
Florent Kermarrec [Fri, 10 Apr 2020 12:36:13 +0000 (14:36 +0200)]
build/lattice/common: remove multi-bits support on SDRInput/Output.