mesa.git
9 years agoi965/fs: Allow an execution size of 32.
Matt Turner [Sat, 4 Apr 2015 00:44:06 +0000 (17:44 -0700)]
i965/fs: Allow an execution size of 32.

In a few commits, we'll start emitting an add(32) instruction on some
platforms.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965: Make type_sz() return unsigned.
Matt Turner [Sat, 11 Apr 2015 21:49:50 +0000 (14:49 -0700)]
i965: Make type_sz() return unsigned.

Avoids annoying warnings when comparing with sizeof(...).

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965: Replace guess_execution_size with something simpler.
Matt Turner [Tue, 14 Apr 2015 19:40:34 +0000 (12:40 -0700)]
i965: Replace guess_execution_size with something simpler.

guess_execution_size() does two things:

   1. Cope with small destination registers.
   2. Cope with SIMD8 vs SIMD16 mode.

This patch replaces the first with a simple if block in brw_set_dest: if
the destination register width is less than 8, you probably want the
execution size to match.  (I didn't put this in the 3src block because
it doesn't seem to matter.)

Since only the FS compiler cares about SIMD16 mode, it's easy to just
set the default execution size there.

This pattern was already been proven in the Gen8+ generator, but we
didn't port it back to the existing generator when we combined the two.

This is based on a patch from Ken from about a year ago. I've rebased it
and and fixed a few bugs.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Ensure delta_x/y are even-aligned registers on Gen6.
Matt Turner [Thu, 2 Apr 2015 23:57:10 +0000 (16:57 -0700)]
i965/fs: Ensure delta_x/y are even-aligned registers on Gen6.

The BSpec says this applies to Gen6 as well.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agomain: remove __FUNCTION__ defined because it is obsolete
Marius Predut [Thu, 16 Apr 2015 10:36:07 +0000 (13:36 +0300)]
main: remove __FUNCTION__ defined because it is obsolete

Consistently just use C99's __func__ everywhere.
No functional changes.

Signed-off-by: Marius Predut <marius.predut@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
9 years agoradeon: replace __FUNCTION__ with __func__
Marius Predut [Thu, 16 Apr 2015 10:35:50 +0000 (13:35 +0300)]
radeon: replace __FUNCTION__ with __func__

Consistently just use C99's __func__ everywhere.
No functional changes.

Signed-off-by: Marius Predut <marius.predut@intel.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
9 years agomesa: add missing break in switch statement
Tapani Pälli [Tue, 21 Apr 2015 05:26:03 +0000 (08:26 +0300)]
mesa: add missing break in switch statement

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-By: Martin Peres <martin.peres@linux.intel.com>
9 years agoglsl: add fallthrough comment on switch
Tapani Pälli [Tue, 21 Apr 2015 05:25:16 +0000 (08:25 +0300)]
glsl: add fallthrough comment on switch

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-By: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: fix UBO queries for active uniforms
Tapani Pälli [Mon, 20 Apr 2015 12:41:06 +0000 (15:41 +0300)]
mesa: fix UBO queries for active uniforms

Commit 34df5eb introduced regression to GetActiveUniformBlockiv
when querying one of the following properties:

   GL_UNIFORM_BLOCK_ACTIVE_UNIFORMS
   GL_UNIFORM_BLOCK_ACTIVE_UNIFORM_INDICES

Implementation counted all uniforms in ubo directly while query should
check first if the uniform in question is _active_.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90109
Reviewed-By: Martin Peres <martin.peres@linux.intel.com>
9 years agoi965/skl: Fix the qpitch value
Neil Roberts [Wed, 18 Feb 2015 18:41:58 +0000 (18:41 +0000)]
i965/skl: Fix the qpitch value

On Skylake the qpitch value is uploaded as part of the surface state
so we don't need to add the extra rows that are done for other
generations. However for 3D textures it needs to be aligned to the
tile height and for depth/stencil textures it needs to be a multiple
of 8. Unlike previous generations the qpitch is measured as a multiple
of the block size for compressed surfaces. When the horizontal mipmap
layout is used for 1D textures then the qpitch is measured in pixels
instead of rows.

v2: Align the depth/stencil textures to a multiple of 8
v3: Add an assert that ALL_SLICES_AT_EACH_LOD is not used. Ignore the
    vertical alignment when picking the qpitch for 1D_ARRAY textures.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
9 years agoi965/skl: Don't use ALL_SLICES_AT_EACH_LOD
Neil Roberts [Fri, 20 Feb 2015 19:11:46 +0000 (19:11 +0000)]
i965/skl: Don't use ALL_SLICES_AT_EACH_LOD

The render surface state command for Skylake doesn't have the surface
array spacing bit so it's not possible to select this layout. I think
it was only used in order to make it pick a tightly-packed qpitch
value that doesn't include space for the mipmaps. However this won't
be necessary after the next patch because it will automatically pick a
packed qpitch value whenever first_level==last_level. It is better to
remove this layout entirely on Gen8+ because although it can
effectively be implemented with a small qpitch value when there are no
mipmaps it isn't possible to support the case where there are mipmaps
because in that case the layout is very different.

It could be good to make a similar change for Gen8 if we also change
the layouting code to pick the qpitch value in a similar way.

v2: Make the commit message and comments more convincing

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Ben Widawsky <ben@bwidawsk.net>
9 years agoclover: remove pre llvm 3.5.0 compatibility code
EdB [Sun, 19 Apr 2015 08:50:19 +0000 (10:50 +0200)]
clover: remove pre llvm 3.5.0 compatibility code

Acked-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
9 years agoclover: make llvm >= 3.5.0 and c++11 mandatory
EdB [Mon, 20 Apr 2015 18:28:09 +0000 (20:28 +0200)]
clover: make llvm >= 3.5.0 and c++11 mandatory

Clover not longer compile with llvm <= 3.5.0 since e1d363b3.
e1d363b3 implies c++11 and llvm 3.5.0 CXXFLAGS provided it.
No one seems to have noticed it, it's now official.

Acked-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
9 years agodocs/GL3.txt: update ARB_shader_subroutine status
Dave Airlie [Mon, 20 Apr 2015 08:41:52 +0000 (18:41 +1000)]
docs/GL3.txt: update ARB_shader_subroutine status

Admit to having started working on this, I don't admit to ever finishing it

Signed-off-by: Dave Airlie <airlied@redhat.com>
9 years agogallivm: Fix build against LLVM 3.7 SVN r235265
Nick Sarnie [Mon, 20 Apr 2015 03:51:26 +0000 (23:51 -0400)]
gallivm: Fix build against LLVM 3.7 SVN r235265

LLVM removed JITEmitDebugInfo from TargetOptions since they weren't used

v2: Be consistent with the LLVM version check (Aaron Watry)

Signed-off-by: Nick Sarnie <commendsarnex@gmail.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agodoc: Add GL_ARB_shader_image_size dependency for OpenGL ES 3.1
Ian Romanick [Thu, 16 Apr 2015 19:17:19 +0000 (12:17 -0700)]
doc: Add GL_ARB_shader_image_size dependency for OpenGL ES 3.1

imageSize() is in the GLSL ES 3.1 spec.  Trivial.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
9 years agoindices: fix provoking vertex for quads/quadstrips
Ilia Mirkin [Tue, 7 Apr 2015 05:42:05 +0000 (01:42 -0400)]
indices: fix provoking vertex for quads/quadstrips

This allows drivers to provide consistent flat shading for quads.
Otherwise a driver that only supported tris would have to force last
provoking vertex when drawing quads (and would have to say that quads
don't follow the provoking vertex convention).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
9 years agoprimconvert: select pv convention only from flatshade_first
Ilia Mirkin [Tue, 7 Apr 2015 15:43:52 +0000 (11:43 -0400)]
primconvert: select pv convention only from flatshade_first

This should match to how drivers program hardware. flatshade relates to
whether color inputs are interpolated, not the provoking vertex
convention.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/a3xx: enable polymode setting with non-fill modes
Ilia Mirkin [Tue, 7 Apr 2015 04:57:34 +0000 (00:57 -0400)]
freedreno/a3xx: enable polymode setting with non-fill modes

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno/a3xx: fix integer and 32-bit float border colors
Ilia Mirkin [Mon, 6 Apr 2015 05:15:09 +0000 (01:15 -0400)]
freedreno/a3xx: fix integer and 32-bit float border colors

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno/a3xx: add support for float R/RG render targets
Ilia Mirkin [Mon, 6 Apr 2015 01:38:57 +0000 (21:38 -0400)]
freedreno/a3xx: add support for float R/RG render targets

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agomesa: add .mesa-install-links files to gitignore
Connor Abbott [Fri, 17 Apr 2015 16:53:53 +0000 (12:53 -0400)]
mesa: add .mesa-install-links files to gitignore

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agomesa/main: add autogenerated format-info.c to gitignore
Connor Abbott [Fri, 17 Apr 2015 16:50:30 +0000 (12:50 -0400)]
mesa/main: add autogenerated format-info.c to gitignore

v2: move to right after format-info.h

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agoi965: Issue perf_debug messages for unsynchronized maps on !LLC systems.
Kenneth Graunke [Wed, 25 Feb 2015 05:34:30 +0000 (21:34 -0800)]
i965: Issue perf_debug messages for unsynchronized maps on !LLC systems.

We haven't implemented proper unsynchronized map support on !LLC systems
(pre-SNB, Atom).  MapBufferRange with GL_MAP_UNSYNCHRONIZE_BIT will
actually do a synchronized map, probably killing performance.

Also warn on BufferSubData, when we should be doing an unsynchronized
upload, but instead have to do a synchronous map.

v2: Only complain if the buffer is actually busy - we use unsynchronized
    maps internally for vertex upload and such, but expect those to not
    be busy.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Ben Widawsky <ben@bwidawsk.net>
9 years agoi965: Make shader_time store names/ids instead of referencing shaders.
Kenneth Graunke [Wed, 15 Apr 2015 09:16:47 +0000 (02:16 -0700)]
i965: Make shader_time store names/ids instead of referencing shaders.

Jason noticed that shader_time was bumping the reference count on the
gl_shader_program and gl_program structures, in code called during
compilation.

Not only were these never unreferenced, but it meant fragment shaders
might be referenced twice (SIMD8 and SIMD16)...or only once.

We don't actually need the programs.  We just need their numeric ID and
their language (GLSL/ARB/FF) or KHR_debug label.  If there's a label, we
have to strdup it since the underlying program could be deleted.

To be fair, we're not exactly cleaning that up either, but we at least
ralloc it out of the shader_time arrays, so if we ever bother cleaning
those up, they'll go away properly.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
9 years agoi965: Delete some unnecessary code in brw_report_shader_time().
Kenneth Graunke [Wed, 15 Apr 2015 09:04:17 +0000 (02:04 -0700)]
i965: Delete some unnecessary code in brw_report_shader_time().

It is true that a gl_shader_program with ID 0 will be a fixed-function
fragment program; a gl_program with ID 0 but NULL gl_shader_program
means that it's a fixed-function vertex shader.

But that's not terribly interesting or relevant to what we're doing.
We just need to know that ID 0 means "fixed function".

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
9 years agoi965: Make shader_time use 0 instead of -1 for "no meaningful ID".
Kenneth Graunke [Wed, 15 Apr 2015 08:57:52 +0000 (01:57 -0700)]
i965: Make shader_time use 0 instead of -1 for "no meaningful ID".

0 is not a valid GLSL shader or ARB program ID.  For some reason,
shader_time used -1 instead...so we had code to detect 0, then override
it to -1.

We can just delete that.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
9 years agoadjust a couple of ifdefs to handle NetBSD correctly
Tobias Nygren [Fri, 17 Apr 2015 18:27:55 +0000 (20:27 +0200)]
adjust a couple of ifdefs to handle NetBSD correctly

Acked-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Tobias Nygren <tnn@NetBSD.org>
9 years agoconfigure.ac: fix bashism
Tobias Nygren [Fri, 17 Apr 2015 18:18:48 +0000 (20:18 +0200)]
configure.ac: fix bashism

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Tobias Nygren <tnn@NetBSD.org>
9 years agoi965: Render R16G16B16X16 as R16G16B16A16
Anuj Phogat [Fri, 10 Apr 2015 11:35:24 +0000 (04:35 -0700)]
i965: Render R16G16B16X16 as R16G16B16A16

This enables using _mesa_meta_pbo_TexSubImage() to upload data
to R16G16B16X16 texture. Earlier it fell back to slower paths.

Jenkins run shows no piglit regressions.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965: Update the comment about platforms supporting blorp
Anuj Phogat [Mon, 13 Apr 2015 17:20:29 +0000 (10:20 -0700)]
i965: Update the comment about platforms supporting blorp

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
9 years agonir: Allow abs/neg in select peephole pass.
Matt Turner [Thu, 2 Apr 2015 17:21:16 +0000 (10:21 -0700)]
nir: Allow abs/neg in select peephole pass.

total instructions in shared programs: 4314531 -> 4308949 (-0.13%)
instructions in affected programs:     429085 -> 423503 (-1.30%)
helped:                                1680
HURT:                                  0
GAINED:                                0
LOST:                                  111

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Change SEL and MOV types as needed to propagate source modifiers
Jason Ekstrand [Fri, 3 Apr 2015 18:07:47 +0000 (11:07 -0700)]
i965/fs: Change SEL and MOV types as needed to propagate source modifiers

SEL and MOV instructions, as long as they don't have source modifiers, are
just copying bits around.  This commit adds support to copy propagation to
switch the type of a SEL or MOV instruction as needed so that it can
propagate source modifiers.  This is needed because NIR generates integer
SEL and MOV instructions whenver it doesn't know what else to generate.

shader-db results with NIR:
total FS instructions in shared programs: 4360910 -> 4360186 (-0.02%)
FS instructions in affected programs:     59094 -> 58370 (-1.23%)
helped:                                   341
HURT:                                     0
GAINED:                                   2
LOST:                                     0

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/fs: Use the source type when looking for UD negations in copy prop
Jason Ekstrand [Fri, 3 Apr 2015 19:15:48 +0000 (12:15 -0700)]
i965/fs: Use the source type when looking for UD negations in copy prop

There can be problems with floats and conditional modifiers when
copy-propagating a negated UD source.  The problem arises when a source
modifier is applied to a UD value.  In this case, a 33-bit representation
is internally used.  If you do the following:

   1: mov foo:UD 7U
   2: mov bar:UD -foo:UD
   3: mov out:F bar:UD

the out register will have the value (float)(unt32_t)-7 which is some very
large floating-point number.  However, if we allow copy-propagation of the
second mov, we get

   1: mov foo:UD 7U
   3: mov out:f -bar:UD

and, since the negation is computed in 33-bits, we get a value of -7.0f
which is clearly not the same.  This is a similar problem if the
instruction has a conditional modifier where the 33-bit value is used in
the comparison and not the 32-bit version.

Previously, we checked the source to be copied for the negate and then
checked the source being propagated to for the type.  This isn't quite what
we want because we are really just looking for negated UD sources.  A check
later in the file ensures that both ends of the propagate have the right
type so it works.  However, if we relax the restriction that both ends of
the propagation have the same type, it ends up causing us to bail early in
cases we don't want.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agofreedreno/ir3/nir: few little fixes
Rob Clark [Thu, 16 Apr 2015 19:35:50 +0000 (15:35 -0400)]
freedreno/ir3/nir: few little fixes

isaml needs to scale up coords based on LoD.  Also fix bogus bary.f
varying # when there are non-bary frag shader inputs.  And use sub.s of
a positive immediate rather than add.s of negative (since CP is better
about figuring out that those can be collapsed into the cat2 instr).

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3/nir: lower if/else
Rob Clark [Wed, 15 Apr 2015 14:16:31 +0000 (10:16 -0400)]
freedreno/ir3/nir: lower if/else

For now, completely flatten if/else blocks.  That will almost certainly
change once we have flow control.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/a4xx: support for large shaders
Rob Clark [Sun, 12 Apr 2015 16:58:52 +0000 (12:58 -0400)]
freedreno/a4xx: support for large shaders

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno: update generated headers
Rob Clark [Sun, 12 Apr 2015 18:25:29 +0000 (14:25 -0400)]
freedreno: update generated headers

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3/nir: UBO support
Rob Clark [Sun, 12 Apr 2015 13:47:40 +0000 (09:47 -0400)]
freedreno/ir3/nir: UBO support

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3: move out helper
Rob Clark [Sun, 12 Apr 2015 13:46:34 +0000 (09:46 -0400)]
freedreno/ir3: move out helper

We'll also want it in NIR f/e for implementing UBO support.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/a4xx: sysvals and UBOs
Rob Clark [Sat, 11 Apr 2015 16:15:17 +0000 (12:15 -0400)]
freedreno/a4xx: sysvals and UBOs

Basically just sync up the cmdstream emit parts to match the changes
already done on a3xx.

Also, fix scheduling for mem instructions.  This is needed on a4xx, and
I am a bit surprised it isn't needed for a3xx.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agonir/builder: add nir_builder_insert_after_instr()
Rob Clark [Wed, 15 Apr 2015 19:49:15 +0000 (15:49 -0400)]
nir/builder: add nir_builder_insert_after_instr()

For lowering if/else, I need a way to insert at the end of the previous
block.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agogallium/ttn: fix TXF
Rob Clark [Thu, 16 Apr 2015 19:16:12 +0000 (15:16 -0400)]
gallium/ttn: fix TXF

There is a level param stashed away in the .w component of the first
src.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agogallium/ttn: add UBO support
Rob Clark [Sun, 12 Apr 2015 12:15:33 +0000 (08:15 -0400)]
gallium/ttn: add UBO support

v2: move ishl into ttn (instead of driver backend) to keep the units
    consistent between immediate and indirect offsets

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agogallium/ttn: minor cleanup
Rob Clark [Sat, 11 Apr 2015 19:25:58 +0000 (15:25 -0400)]
gallium/ttn: minor cleanup

v2: also use ttn_src_for_indirect() everywhere for addr access, rather
    than open-coding it for INPUT/CONST srcs
v3: move ralloc out of ttn_src_for_indirect() into the one call site
    that needs a ptr

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agogallium/ttn: add support for TXL2
Rob Clark [Sat, 11 Apr 2015 15:37:12 +0000 (11:37 -0400)]
gallium/ttn: add support for TXL2

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agogallium/ttn: add support for texture offsets
Rob Clark [Sat, 11 Apr 2015 15:35:29 +0000 (11:35 -0400)]
gallium/ttn: add support for texture offsets

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agomesa/st: Free st_translate with FREE macro.
Brian Paul [Fri, 17 Apr 2015 14:14:23 +0000 (15:14 +0100)]
mesa/st: Free st_translate with FREE macro.

To match CALLOC_STRUCT macro.

Fixes memory corruption on Windows when u_memory's memory debugging is
enabled.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
9 years agolibgl-gdi: Prevent "pure virtual method called" error when.
Jose Fonseca [Thu, 16 Apr 2015 12:08:56 +0000 (13:08 +0100)]
libgl-gdi: Prevent "pure virtual method called" error when.

When running piglit w/ llvmpipe on Windows several tests terminate
abnormally just when the test exits.

The problem was that LLVMContextDispose was being called
after LLVM global destructors.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
9 years agoi965: Add marketing names for CHV
Ville Syrjälä [Thu, 16 Apr 2015 16:21:07 +0000 (19:21 +0300)]
i965: Add marketing names for CHV

All CHV devices will be branded as "Intel(r) HD Graphics".

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
9 years agonir: Convert the if-test for num_inputs == 2 to an assertion
Ian Romanick [Wed, 15 Apr 2015 22:20:57 +0000 (15:20 -0700)]
nir: Convert the if-test for num_inputs == 2 to an assertion

Suggested by Jason on a different patch after some comments /
questions by Ilia.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Connor Abbott <cwabott0@gmail.com>
9 years agoconfigure.ac: print LLVM_LDFLAGS
Marek Olšák [Mon, 13 Apr 2015 19:44:02 +0000 (21:44 +0200)]
configure.ac: print LLVM_LDFLAGS

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Emil Velikov <emil.l.velilkov@gmail.com>
9 years agoglsl_to_tgsi: only associate the uniform storage once at link time
Marek Olšák [Sat, 11 Apr 2015 18:05:41 +0000 (20:05 +0200)]
glsl_to_tgsi: only associate the uniform storage once at link time

This hack is no longer needed. (see the previous commit)

Reviewed-by: Brian Paul <brianp@vmware.com>
9 years agoglsl_to_tgsi: add STATE_FB_WPOS_Y_TRANSFORM at link time
Marek Olšák [Sat, 11 Apr 2015 18:01:22 +0000 (20:01 +0200)]
glsl_to_tgsi: add STATE_FB_WPOS_Y_TRANSFORM at link time

This will allow removing the uniform storage re-association during
TGSI generation at draw time.

Reviewed-by: Brian Paul <brianp@vmware.com>
9 years agoglsl_to_tgsi: add assertions for detecting out-of-bounds immediates access
Marek Olšák [Sat, 11 Apr 2015 12:40:09 +0000 (14:40 +0200)]
glsl_to_tgsi: add assertions for detecting out-of-bounds immediates access

Reviewed-by: Brian Paul <brianp@vmware.com>
9 years agoglsl_to_tgsi: don't use a potentially-undefined immediate for ir_query_levels
Marek Olšák [Sat, 11 Apr 2015 12:55:26 +0000 (14:55 +0200)]
glsl_to_tgsi: don't use a potentially-undefined immediate for ir_query_levels

Cc: 10.4 10.5 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
9 years agoglsl_to_tgsi: fix out-of-bounds constant access and crash for uniforms
Marek Olšák [Sat, 11 Apr 2015 11:49:38 +0000 (13:49 +0200)]
glsl_to_tgsi: fix out-of-bounds constant access and crash for uniforms

This fixes piglit shaders@glsl-fs-uniform-array-loop-unroll with immediate
shader compilation - it's a compiler test, so it has never been translated
to TGSI before.

Cc: 10.4 10.5 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
9 years agoglsl_to_tgsi: cleanup includes
Marek Olšák [Wed, 18 Mar 2015 11:38:19 +0000 (12:38 +0100)]
glsl_to_tgsi: cleanup includes

Reviewed-by: Brian Paul <brianp@vmware.com>
9 years agomesa/program: remove dead code
Marek Olšák [Sat, 11 Apr 2015 17:35:40 +0000 (19:35 +0200)]
mesa/program: remove dead code

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoradeonsi: add a debug option to compile shaders when they're created
Marek Olšák [Fri, 10 Apr 2015 21:58:34 +0000 (23:58 +0200)]
radeonsi: add a debug option to compile shaders when they're created

Tested-by: Tom Stellard <thomas.stellard@amd.com>
9 years agost/mesa: add a debug option to compile shaders at link time
Marek Olšák [Fri, 10 Apr 2015 21:58:34 +0000 (23:58 +0200)]
st/mesa: add a debug option to compile shaders at link time

v2: fix crashes

Tested-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
9 years agoi965: Rewrite ir_tex to ir_txl with lod 0 for vertex shaders
Kristian Høgsberg [Tue, 14 Apr 2015 15:02:18 +0000 (15:02 +0000)]
i965: Rewrite ir_tex to ir_txl with lod 0 for vertex shaders

The ir_tex opcode turns into a sample or sample_c message, which will try to
compute derivatives to determine the lod. This produces garbage for
non-fragment shaders where the sample coordinates don't correspond to
subspans.

We fix this by rewriting the opcode from ir_tex to ir_txl and setting the
lod to 0.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89457
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kristian Høgsberg <kristian.h.kristensen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
9 years agoradeonsi: remove bogus r600-- triple
Emil Velikov [Wed, 8 Apr 2015 18:27:02 +0000 (19:27 +0100)]
radeonsi: remove bogus r600-- triple

As mentioned by Michel Dänzer for LLVM >= 3.6 we create the
LLVMTargetMachine (with triple amdgcn--), as we setup the radeonsi
context. For older LLVM or hardware (r600) the triple is always r600--
and is created at a later stage - radeon_llvm_compile()

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agoi965/skl: Add the header for constant loads outside of the generator
Neil Roberts [Tue, 24 Mar 2015 15:52:20 +0000 (15:52 +0000)]
i965/skl: Add the header for constant loads outside of the generator

Commit 5a06ee738 added a step to the generator to set up the message
header when generating the VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
instruction. That pseudo opcode is implemented in terms of multiple
actual opcodes, one of which writes to one of the source registers in
order to set up the message header. This causes problems because the
scheduler isn't aware that the source register is written to and it
can end up reorganising the instructions incorrectly such that the
write to the source register overwrites a needed value from a previous
instruction. This problem was presenting itself as a rendering error
in the weapon in Enemy Territory: Quake Wars.

Since commit 588859e1 there is an additional problem that the double
register allocated to include the message header would end up being
split into two. This wasn't happening previously because the code to
split registers was explicitly avoided for instructions that are
sending from the GRF.

This patch fixes both problems by splitting the code to set up the
message header into a new pseudo opcode so that it will be done
outside of the generator. This new opcode has the header register as a
destination so the scheduler can recognise that the register is
written to. This has the additional benefit that the scheduler can
optimise the message header slightly better by moving the mov
instructions further away from the send instructions.

On Skylake it appears to fix the following three Piglit tests without
causing any regressions:

 gs-float-array-variable-index
 gs-mat3x4-row-major
 gs-mat4x3-row-major

I think we actually may need to do something similar for the fs
backend and possibly for message headers from regular texture sampling
but I'm not entirely sure.

v2: Make sure the exec-size is retained as 8 for the mov instruction
    to initialise the header from g0. This was accidentally lost
    during a rebase on top of 07c571a39fa1.
    Split the patch into two so that the helper function is a separate
    change.
    Fix emitting the MOV instruction on Gen7.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89058
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
9 years agoi965/vec4: Add a helper function to emit VS_OPCODE_PULL_CONSTANT_LOAD
Neil Roberts [Wed, 15 Apr 2015 13:28:26 +0000 (14:28 +0100)]
i965/vec4: Add a helper function to emit VS_OPCODE_PULL_CONSTANT_LOAD

There were three places in the visitor that had a similar chunk of
code to emit the VS_OPCODE_PULL_CONSTANT_LOAD opcode using a register
for the offset. This patch combines the chunks into a helper function
to reduce the code duplication. It will also be useful in the next
patch to expand what happens on Gen9+. This shouldn't introduce any
functional changes.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
9 years agomesa,glsl: rename `interface` to `programInterface`.
Jose Fonseca [Thu, 16 Apr 2015 09:19:57 +0000 (10:19 +0100)]
mesa,glsl: rename `interface` to `programInterface`.

`interface` is a define on Windows -- an alias for `struct` keyword,
used when declaring COM interfaces in C or C++.

So use instead `programInterface`, therefore matching the name used
in GL_ARB_program_interface_query spec/headers, which was renamed exactly
for the same reason:

  "Revision 10, May 10, 2012 (pbrown)
     - Rename the formal parameter <interface> used by the functions in this
       extension to <programInterface>.  Certain versions of the Microsoft
       C/C++ compiler and/or its headers cause "interface" to be treated as a
       reserved keyword."

Trivial.

9 years agogbm: Add GBM_BO_USE_LINEAR flag
Flora Cui [Tue, 24 Mar 2015 10:34:29 +0000 (18:34 +0800)]
gbm: Add GBM_BO_USE_LINEAR flag

Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
9 years agomesa: refactor GetUniformBlockIndex
Tapani Pälli [Fri, 13 Mar 2015 06:53:23 +0000 (08:53 +0200)]
mesa: refactor GetUniformBlockIndex

Use _mesa_program_resource_index to get index.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: refactor GetUniformIndices
Tapani Pälli [Thu, 12 Mar 2015 12:37:20 +0000 (14:37 +0200)]
mesa: refactor GetUniformIndices

Use _mesa_program_resource_index to get indices.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: refactor GetUniformLocation
Tapani Pälli [Thu, 12 Mar 2015 12:31:15 +0000 (14:31 +0200)]
mesa: refactor GetUniformLocation

Use _mesa_program_resource_location to get location.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: refactor GetActiveUniformBlockName
Tapani Pälli [Thu, 12 Mar 2015 11:33:25 +0000 (13:33 +0200)]
mesa: refactor GetActiveUniformBlockName

Use _mesa_get_program_resource_name to get name.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: remove unused _mesa_get_uniform_name
Tapani Pälli [Thu, 12 Mar 2015 11:53:07 +0000 (13:53 +0200)]
mesa: remove unused _mesa_get_uniform_name

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: refactor GetActiveUniformName
Tapani Pälli [Thu, 12 Mar 2015 11:22:16 +0000 (13:22 +0200)]
mesa: refactor GetActiveUniformName

Use _mesa_get_program_resource_name to get name.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: refactor GetActiveUniform
Tapani Pälli [Thu, 12 Mar 2015 10:55:18 +0000 (12:55 +0200)]
mesa: refactor GetActiveUniform

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: refactor GetTransformFeedbackVarying
Tapani Pälli [Thu, 12 Mar 2015 10:08:56 +0000 (12:08 +0200)]
mesa: refactor GetTransformFeedbackVarying

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: refactor GetActiveUniformsiv, use _mesa_program_resource_prop
Tapani Pälli [Thu, 12 Mar 2015 08:17:09 +0000 (10:17 +0200)]
mesa: refactor GetActiveUniformsiv, use _mesa_program_resource_prop

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agomesa: mesa_bufferiv utility function for buffer objects
Tapani Pälli [Thu, 12 Mar 2015 05:58:48 +0000 (07:58 +0200)]
mesa: mesa_bufferiv utility function for buffer objects

Patch adds new function 'mesa_bufferiv' and refactors existing
GetActiveUniformBlockiv and GetActiveAtomicCounterBufferiv to
use it.

corresponding Piglit tests:
   arb_uniform_buffer_object*
   arb_shader_atomic_counters*

(Many tests hit the corresponding queries.)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: refactor GetFragDataIndex
Tapani Pälli [Thu, 12 Mar 2015 13:14:31 +0000 (15:14 +0200)]
mesa: refactor GetFragDataIndex

Use _mesa_program_resource_location_index to fetch index.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: refactor GetFragDataLocation
Tapani Pälli [Thu, 12 Mar 2015 13:13:30 +0000 (15:13 +0200)]
mesa: refactor GetFragDataLocation

Use program_resource_location to fetch location.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: refactor GetAttribLocation
Tapani Pälli [Thu, 12 Mar 2015 13:11:04 +0000 (15:11 +0200)]
mesa: refactor GetAttribLocation

Use program_resource_location to fetch location.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: refactor GetActiveAttrib
Tapani Pälli [Wed, 11 Mar 2015 07:05:47 +0000 (09:05 +0200)]
mesa: refactor GetActiveAttrib

Instead of iterating IR, retrieve required information through
the new program resource functions.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agomesa: enable GL_ARB_program_interface_query extension
Tapani Pälli [Tue, 7 Apr 2015 09:07:03 +0000 (12:07 +0300)]
mesa: enable GL_ARB_program_interface_query extension

(and mark it as DONE in docs/GL3.txt + 10.6.0 relnotes)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: implementation of glGetProgramResourceiv
Tapani Pälli [Tue, 10 Mar 2015 11:11:14 +0000 (13:11 +0200)]
mesa: implementation of glGetProgramResourceiv

Patch adds required helper functions to shaderapi.h and
the actual implementation.

The property query functionality can be tested with tests for
following functions that are refactored by later patches:

   GetActiveAtomicCounterBufferiv
   GetActiveUniformBlockiv
   GetActiveUniformsiv

v2: code cleanup (Ilia Mirkin)
    add bufSize < 0 check and error out
    fix is_resource_referenced to return bool
    check for propCount and bufSize, fixes in buffer_prop

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: glGetProgramResourceLocationIndex
Tapani Pälli [Thu, 12 Mar 2015 12:08:38 +0000 (14:08 +0200)]
mesa: glGetProgramResourceLocationIndex

Patch adds required helper functions to shaderapi.h and
the actual implementation.

The added functionality can be tested by tests for following
functions that are refactored by later patches:

   GetFragDataIndex

v2: return -1 if output not referenced by fragment stage
    (Ilia Mirkin)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: glGetProgramResourceLocation
Tapani Pälli [Thu, 12 Mar 2015 11:45:22 +0000 (13:45 +0200)]
mesa: glGetProgramResourceLocation

Patch adds required helper functions to shaderapi.h and
the actual implementation.

corresponding Piglit test:
   arb_program_interface_query-resource-location

The added functionality can be tested by tests for following
functions that are refactored by later patches:

   GetAttribLocation
   GetUniformLocation
   GetFragDataLocation

v2: code cleanup, changes to array element
    syntax checking (Ilia Mirkin)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa: glGetProgramResourceName
Tapani Pälli [Tue, 10 Mar 2015 08:33:20 +0000 (10:33 +0200)]
mesa: glGetProgramResourceName

Patch adds required helper functions to shaderapi.h and
the actual implementation.

Name generation copied from '_mesa_get_uniform_name' which can
be removed later by refactoring functions to use resource list.

The added functionality can be tested by tests for following
functions that are refactored by later patches:

   GetActiveUniformName
   GetActiveUniformBlockName

v2: no index for geometry shader inputs (Ilia Mirkin)
    add bufSize < 0 check and error out
    validate enum

corresponding Piglit test:
   arb_program_interface_query-getprogramresourcename

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.org>
9 years agomesa: glGetProgramResourceIndex
Tapani Pälli [Tue, 10 Mar 2015 07:30:30 +0000 (09:30 +0200)]
mesa: glGetProgramResourceIndex

Patch adds required helper functions to shaderapi.h and
the actual implementation.

v2: code cleanup (Ilia Mirkin)

corresponding Piglit test:
   arb_program_interface_query-getprogramresourceindex

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.org>
9 years agomesa: glGetProgramInterfaceiv
Tapani Pälli [Fri, 6 Mar 2015 13:05:51 +0000 (15:05 +0200)]
mesa: glGetProgramInterfaceiv

Patch adds required helper functions to shaderapi.h and
the actual implementation.

v2: code cleanup (Ilia Mirkin)
    fix array size fo xfb varyings
    validate programInterface and throw error

v3: put GL_MAX_NUM_COMPATIBLE_SUBROUTINES where
    it belongs

corresponding Piglit test:
   arb_program_interface_query-getprograminterfaceiv

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agomesa/glsl: build list of program resources during linking
Tapani Pälli [Fri, 6 Mar 2015 07:14:49 +0000 (09:14 +0200)]
mesa/glsl: build list of program resources during linking

Patch adds ProgramResourceList to gl_shader_program structure.
List contains references to active program resources and is
constructed during linking phase.

This list will be used by follow-up patches to implement hooks
for GL_ARB_program_interface_query. It can be also used to
implement any of the older shader program query APIs.

v2: code cleanups + note for SSBO and subroutines (Ilia Mirkin)
v3: code cleanups + assert(MESA_SHADER_STAGES < 8) (Martin Peres)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agoglapi: add GL_ARB_program_interface_query skeleton
Tapani Pälli [Mon, 16 Feb 2015 12:15:36 +0000 (14:15 +0200)]
glapi: add GL_ARB_program_interface_query skeleton

v2: update dispatch_sanity test (Jason Ekstrand)
    + small code cleanups

v3: xml and Makefile fixes (Ilia Mirkin, Matt Turner)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agolinker: fix varying linking if SSO program has only gs and fs
Tapani Pälli [Tue, 17 Mar 2015 11:58:57 +0000 (13:58 +0200)]
linker: fix varying linking if SSO program has only gs and fs

Previously linker did not take in to account case where one would
have only gs and fs (with SSO), patch adds the case by refactoring
code around assign_varying_locations. This makes sure locations for
gs get populated correctly.

This was found with some of the SSO subtests of Martin's upcoming
GetProgramInterfaceiv Piglit test which passes with the patch, no
Piglit regressions.

v2: code cleanups (Martin Peres)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
9 years agor600g/sb: Skip empty ALU clause while scheduling
Glenn Kennard [Wed, 8 Apr 2015 09:30:37 +0000 (11:30 +0200)]
r600g/sb: Skip empty ALU clause while scheduling

Fixes assert triggered by
ext_transform_feedback-intervening-read output use_gs
piglit test.

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
9 years agonir: Try commutative sources in CSE
Ian Romanick [Mon, 13 Apr 2015 23:16:10 +0000 (16:16 -0700)]
nir: Try commutative sources in CSE

Shader-db results:

GM45 NIR:
total instructions in shared programs: 4082044 -> 4081919 (-0.00%)
instructions in affected programs:     27609 -> 27484 (-0.45%)
helped:                                44

Iron Lake NIR:
total instructions in shared programs: 5678776 -> 5678646 (-0.00%)
instructions in affected programs:     27406 -> 27276 (-0.47%)
helped:                                45

Sandy Bridge NIR:
total instructions in shared programs: 7329995 -> 7329096 (-0.01%)
instructions in affected programs:     142035 -> 141136 (-0.63%)
helped:                                406
HURT:                                  19

Ivy Bridge NIR:
total instructions in shared programs: 6769314 -> 6768359 (-0.01%)
instructions in affected programs:     140820 -> 139865 (-0.68%)
helped:                                423
HURT:                                  2

Haswell NIR:
total instructions in shared programs: 6183693 -> 6183298 (-0.01%)
instructions in affected programs:     96538 -> 96143 (-0.41%)
helped:                                303
HURT:                                  4

Broadwell NIR:
total instructions in shared programs: 7501711 -> 7498170 (-0.05%)
instructions in affected programs:     266403 -> 262862 (-1.33%)
helped:                                705
HURT:                                  5
GAINED:                                4

v2: Rebase on top of Connor's fix.

v3: Convert the if-test for num_inputs == 2 to an assertion.  Suggested
by Jason after some comments / questions by Ilia.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> [v1]
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: Connor Abbott <cwabbott0@gmail.com>
9 years agoglx: Create proper server dependency for GLX_EXT_create_context_es2_profile
Ian Romanick [Tue, 14 Apr 2015 16:24:06 +0000 (09:24 -0700)]
glx: Create proper server dependency for GLX_EXT_create_context_es2_profile

Previously GLX_EXT_create_context_es2_profile was marked as "direct
only" so that it would not depend on server support.  Since the
extension required functions that are part of
GLX_ARB_create_context_profile, support for the EXT was disabled if the
ARB was not supported.

This was complete rubbish.  If the server supported the ARB but not the
EXT, sending a request with GLX_CONTEXT_ES2_PROFILE_BIT_EXT would result
in GLXBadProfileARB.

Instead of the misguided hack, make GLX_EXT_create_context_es2_profile
properly depend on server support by not marking it as "direct only."

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
9 years agovc4: Don't try to use color load/stores to blit across format changes.
Eric Anholt [Wed, 15 Apr 2015 05:01:55 +0000 (22:01 -0700)]
vc4: Don't try to use color load/stores to blit across format changes.

We could potentially support the right combination of 8888 to 565, but the
important thing for now is to not mix up our orderings of 8888.  Fixes
fbo-copyteximage regressions.

9 years agovc4: Don't try to use color load/stores to do depth/stencil blits.
Eric Anholt [Wed, 15 Apr 2015 04:59:46 +0000 (21:59 -0700)]
vc4: Don't try to use color load/stores to do depth/stencil blits.

Fixes regressions in fbo-generatemipmap-formats on depth/stencil (which
does blits to work around baselevel/lastlevel).

9 years agovc4: Update the shadow texture for public textures on every draw.
Eric Anholt [Tue, 14 Apr 2015 18:31:11 +0000 (11:31 -0700)]
vc4: Update the shadow texture for public textures on every draw.

We don't know who else has written to it, so we'd better update it every
time.  This makes the gears spin in X again.

9 years agovc4: Hook up VC4_DEBUG=perf to some useful printfs.
Eric Anholt [Tue, 14 Apr 2015 18:24:00 +0000 (11:24 -0700)]
vc4: Hook up VC4_DEBUG=perf to some useful printfs.

9 years agost/mesa: log shaders, GLSL info log with _mesa_log()
Brian Paul [Tue, 14 Apr 2015 16:54:34 +0000 (10:54 -0600)]
st/mesa: log shaders, GLSL info log with _mesa_log()

As with previous patch.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
9 years agomesa: log shaders, GLSL info log with _mesa_log()
Brian Paul [Tue, 14 Apr 2015 16:41:56 +0000 (10:41 -0600)]
mesa: log shaders, GLSL info log with _mesa_log()

Now, if we set MESA_LOG_FILE and MESA_GLSL=dump, all the shader info
will get logged to the named file instead of stderr.

Reviewed-by: José Fonseca <jfonseca@vmware.com>