Gabe Black [Thu, 28 Dec 2006 19:27:45 +0000 (14:27 -0500)]
Implement a stub nnpc for alpha that is read only as npc+4.
--HG--
extra : convert_revision :
d08b740d32757fa5471c9bcde9084d59a1d8102d
Gabe Black [Thu, 28 Dec 2006 19:23:30 +0000 (14:23 -0500)]
Fixed NumMiscArchRegs. This is still a magic number, and it should be set automatically by the miscreg enum. I need to figure out how to do that without including the whole miscregfile.hh and making header spaghetti.
--HG--
extra : convert_revision :
eb640c9ef10a188b96f6a079f91abc8f67b9d38c
Gabe Black [Fri, 22 Dec 2006 01:42:40 +0000 (20:42 -0500)]
Stub for SE mode gdb support for MIPS.
--HG--
extra : convert_revision :
2166b511c3615f7a2355f058a624e9ffe8259e65
Gabe Black [Thu, 21 Dec 2006 03:14:40 +0000 (22:14 -0500)]
Fixes to get MIPS_SE to compile.
--HG--
extra : convert_revision :
d173f212841341e436e9a38dcd3006d27886c1b8
Gabe Black [Thu, 21 Dec 2006 01:44:06 +0000 (20:44 -0500)]
Fixes to get ALPHA_FS and ALPHA_SE to compile again.
--HG--
extra : convert_revision :
6e0913903d4cbda6f31bec3b5d725b9c08dc1419
Gabe Black [Wed, 20 Dec 2006 23:39:40 +0000 (18:39 -0500)]
Initial work to make remote gdb available in SE mode. This is completely untested.
--HG--
extra : convert_revision :
3ad9a3368961d5e9e71f702da84ffe293fe8adc8
Gabe Black [Wed, 20 Dec 2006 20:44:37 +0000 (15:44 -0500)]
Make sure the "stack_min" variable is page aligned.
--HG--
extra : convert_revision :
e78c53778de83bdb2eca13d98d418b17b386ab29
Gabe Black [Mon, 18 Dec 2006 23:20:13 +0000 (18:20 -0500)]
Fix a place where the wrong width parameter was used, and set the nextNPC correctly on memory squashes.
--HG--
extra : convert_revision :
7914a48ea953607c48f93984e3b043098f0d7c62
Gabe Black [Mon, 18 Dec 2006 23:18:37 +0000 (18:18 -0500)]
Make sure you only handle branch delay slots specially when there actually was a branch.
--HG--
extra : convert_revision :
ea6d33b1b9c2ba5c24225af4b10a9bd25558f1dd
Gabe Black [Mon, 18 Dec 2006 23:17:30 +0000 (18:17 -0500)]
Fixing the extended twin format to go with the new isa parser interface.
--HG--
extra : convert_revision :
f41183cfa011b21e7ab8cbcdef0ac1d464692362
Gabe Black [Mon, 18 Dec 2006 17:19:30 +0000 (12:19 -0500)]
Merge zizzer.eecs.umich.edu:/.automount/zower/eecshome/m5/newmem
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/sparco3
--HG--
extra : convert_revision :
f17800685609d8353ec14676f45fbb123fc4e6c3
Steve Reinhardt [Mon, 18 Dec 2006 07:09:36 +0000 (23:09 -0800)]
Minor cleanup of new snippet/subst code.
--HG--
extra : convert_revision :
d81e0d1356f3433e8467e407d66d4afb95614748
Steve Reinhardt [Mon, 18 Dec 2006 03:27:50 +0000 (19:27 -0800)]
Convert Alpha (and finish converting MIPS) to new
InstObjParam interface.
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/fp.isa:
src/arch/alpha/isa/int.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/isa/mem.isa:
src/arch/alpha/isa/pal.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/util.isa:
Get rid of CodeBlock calls to adapt to new InstObjParam interface.
src/arch/isa_parser.py:
Check template code for operands (in addition to snippets).
src/cpu/o3/alpha/dyn_inst.hh:
Add (read|write)MiscRegOperand calls to Alpha DynInst.
--HG--
extra : convert_revision :
332caf1bee19b014cb62c1ed9e793e793334c8ee
Gabe Black [Sun, 17 Dec 2006 16:55:24 +0000 (11:55 -0500)]
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/operands.isa:
Hand Merge
--HG--
extra : convert_revision :
4c54544e5c7a61f055ea9b00ccf5f8510df0e6c2
Gabe Black [Sun, 17 Dec 2006 16:16:04 +0000 (11:16 -0500)]
Compilation fixes.
--HG--
extra : convert_revision :
4932ab507580e0c9f7012398e71921ce58fc3c4e
Gabe Black [Sun, 17 Dec 2006 16:15:37 +0000 (11:15 -0500)]
Added in the extended twin load format
src/arch/sparc/isa/decoder.isa:
Added the extended twin load instructions
src/arch/sparc/isa/formats/mem/blockmem.isa:
Added stuff to implement the extended twin loads. This created alot of duplication which I'll deal with later.
--HG--
extra : convert_revision :
5d8bdaacbfe83d21d3a396ce30ace90aeefc54d8
Gabe Black [Sun, 17 Dec 2006 15:54:17 +0000 (10:54 -0500)]
Started removing "CodeBlock" objects from the mips isa description.
--HG--
extra : convert_revision :
2e174ecfce8c86732e1addfc23e961429b86a570
Gabe Black [Sun, 17 Dec 2006 15:53:10 +0000 (10:53 -0500)]
Compilation fix after messy merge.
--HG--
extra : convert_revision :
bf650dfe401377ce1b4c952aa8bfe3708c865472
Gabe Black [Sat, 16 Dec 2006 17:55:55 +0000 (12:55 -0500)]
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/sparcfs
--HG--
extra : convert_revision :
c8718b3df72b8c951c24742e8ce517a93bc23fe9
Gabe Black [Sat, 16 Dec 2006 17:55:15 +0000 (12:55 -0500)]
Merge zizzer:/bk/sparcfs/
into zower.eecs.umich.edu:/eecshome/m5/sparcfs
--HG--
extra : convert_revision :
2764b356ef01d1fcb6ed272e4ef96179cd651d4e
Gabe Black [Sat, 16 Dec 2006 17:54:28 +0000 (12:54 -0500)]
Support for twin loads.
src/arch/sparc/isa/decoder.isa:
Changed the names of the twin loads to match the 2005 spec. They still use the old format though.
src/arch/sparc/isa/formats/mem/blockmem.isa:
Added code to generate twin loads
src/arch/sparc/isa/formats/mem/util.isa:
Added an alignment check for twin loads
src/arch/sparc/isa/operands.isa:
Comment explaining twin load operands.
--HG--
extra : convert_revision :
ad42821a97dcda17744875b1e5dc00a9642e59b7
Gabe Black [Sat, 16 Dec 2006 17:53:01 +0000 (12:53 -0500)]
Compiler error fix.
--HG--
extra : convert_revision :
39e2638a10bf3e821e8f3d4d8c664008c98fc921
Gabe Black [Sat, 16 Dec 2006 16:35:40 +0000 (11:35 -0500)]
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem
src/arch/isa_parser.py:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/cpu/o3/iew_impl.hh:
Hand Merge
--HG--
extra : convert_revision :
ae1b25cde85ab8ec275a09d554acd372887d4d47
Gabe Black [Sat, 16 Dec 2006 14:35:09 +0000 (09:35 -0500)]
Switch the endianness of data that's forwarded. This is the same sort of problem that was happening when stores went all the way to memory and back.
--HG--
extra : convert_revision :
09fece7ae934f542e51046d33505df3f7ec0b919
Gabe Black [Sat, 16 Dec 2006 14:34:20 +0000 (09:34 -0500)]
Make fetch detect when a branch is happening, rather than trying to compute when.
--HG--
extra : convert_revision :
1a8edc004570abb48e6c4cdf1b43c5699866838e
Gabe Black [Sat, 16 Dec 2006 12:47:33 +0000 (07:47 -0500)]
Accidently "cleaned" away the NPC parameter to the constructor.
--HG--
extra : convert_revision :
46670ee86000dfb171d327eb8f58555a4afb2360
Gabe Black [Sat, 16 Dec 2006 12:39:44 +0000 (07:39 -0500)]
Don't have "predict" set the predicted target of the instruction. Do that explicitly when you use predict.
--HG--
extra : convert_revision :
8b613bb365b31ffaef1cea9fd789abe46219bdcf
Gabe Black [Sat, 16 Dec 2006 12:37:33 +0000 (07:37 -0500)]
Add in constants which let you explicitly check if endian conversion would do anything. This was needed for a case where a piece of data was within a larger data type. When the larger data type was swapped, the location of the smaller data type would move.
--HG--
extra : convert_revision :
4c904c964678529c72b8f1044dfcb400604f6654
Gabe Black [Sat, 16 Dec 2006 12:35:56 +0000 (07:35 -0500)]
Add in capability to return to unblocking after a squash. This is needed because if you don't squash -all- the instructions, you need to keep clearing out whatever is left in the skid buffer.
--HG--
extra : convert_revision :
7308eda27f4366348cf5fce71ddfa4b217bc172d
Gabe Black [Sat, 16 Dec 2006 12:34:34 +0000 (07:34 -0500)]
Make sure endian conversion is done on the memory data when it's just set to an existing buffer.
--HG--
extra : convert_revision :
5a890091b6a31b5414acbf68f19e28d7122a98d7
Gabe Black [Sat, 16 Dec 2006 12:33:08 +0000 (07:33 -0500)]
Make the decoder use the new setup in the dyninsts for branch prediction.
--HG--
extra : convert_revision :
9a6d6c93e5b40a55774891df54d290ff557b322c
Gabe Black [Sat, 16 Dec 2006 12:32:06 +0000 (07:32 -0500)]
Made branch delay slots get squashed, and passed back an NPC and NNPC to start fetching from.
--HG--
extra : convert_revision :
a2e4845fedf113b5a2fd92d3d28ce5b006278103
Gabe Black [Sat, 16 Dec 2006 12:22:19 +0000 (07:22 -0500)]
Added a predicted NPC field, explicitly stored whether the instruction was predicted taken or not.
--HG--
extra : convert_revision :
ba668af302ca4d8a3a032e907d5058e1477f462a
Gabe Black [Sat, 16 Dec 2006 12:10:58 +0000 (07:10 -0500)]
Made changes to CWP be non speculative.
--HG--
extra : convert_revision :
43899bc97061c33e67a53179c23e46b079118117
Gabe Black [Sat, 16 Dec 2006 12:10:04 +0000 (07:10 -0500)]
Changes to the isa_parser and affected files to fix an indexing problem with split execute instructions and miscregs aliasing with integer registers.
src/arch/isa_parser.py:
Rearranged things so that classes with more than one execute function treat operands properly.
1. Eliminated the CodeBlock class
2. Created a SubOperandList
3. Redefined how InstObjParams is constructed
To define an InstObjParam, you can either pass in a single code literal which will be named "code", or you can pass in a dictionary of code snippets which will be substituted into the Templates. In order to get this to work, there is a new restriction that each template has only one function in it. These changes should only affect memory instructions which have regular and split execute functions.
Also changed the MiscRegs so that they use the instrunctions srcReg and destReg arrays.
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/branch.isa:
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa/formats/nop.isa:
src/arch/sparc/isa/formats/priv.isa:
src/arch/sparc/isa/formats/trap.isa:
Rearranged to work with new InstObjParam scheme.
src/cpu/o3/sparc/dyn_inst.hh:
Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. Also changed the names of the other accessors so that they have the suffix "Operand" if they use those arrays.
src/cpu/simple/base.hh:
Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays.
--HG--
extra : convert_revision :
c91e1073138b72bcf4113a721e0ed40ec600cf2e
Lisa Hsu [Fri, 15 Dec 2006 23:07:39 +0000 (18:07 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision :
a6a40a3bc2e07bc7828de08fa2ce1c847105483d
Lisa Hsu [Fri, 15 Dec 2006 23:02:23 +0000 (18:02 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision :
68e9bb607fbeb1ed0ea4192411e804dc8e6ddd95
Lisa Hsu [Fri, 15 Dec 2006 22:58:20 +0000 (17:58 -0500)]
small change to eliminate address range overlap.
--HG--
extra : convert_revision :
c8309a8774265a707c87c4f516bec1f81aff4a79
Lisa Hsu [Fri, 15 Dec 2006 22:55:47 +0000 (17:55 -0500)]
little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).
RangeSize as a function takes a start address, and a SIZE, and will make the range (start, start+size-1) for you.
src/cpu/memtest/memtest.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/lsq.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.hh:
Fix RangeSize arguments
src/dev/alpha/tsunami_cchip.cc:
src/dev/alpha/tsunami_io.cc:
src/dev/alpha/tsunami_pchip.cc:
src/dev/baddev.cc:
pioSize indicates SIZE, not a mask
--HG--
extra : convert_revision :
d385521fcfe58f8dffc8622260937e668a47a948
Lisa Hsu [Fri, 15 Dec 2006 18:27:53 +0000 (13:27 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
2f11b5f9fa6356cbf9f98c8cd7d4f6fbfaf9d24d
Lisa Hsu [Fri, 15 Dec 2006 18:06:37 +0000 (13:06 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision :
92a865a90a7c3e251ed1443f79640f761b359c1d
Lisa Hsu [Fri, 15 Dec 2006 18:05:46 +0000 (13:05 -0500)]
some small general fixes to make everythign work nicely with other ISAs, now we can merge back with newmem.
exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
mmaped_ipr.hh:
fix for build
miscregfile.cc:
fixes for HPSTATE access during SE mode
src/arch/sparc/miscregfile.cc:
fixes for HPSTATE access during SE mode
src/arch/mips/mmaped_ipr.hh:
fix for build
src/cpu/exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
--HG--
extra : convert_revision :
c5b9d56ab99018a91d04de47ba1d5ca7768590bb
Lisa Hsu [Fri, 15 Dec 2006 18:01:06 +0000 (13:01 -0500)]
loadstore.isa:
this privilegedString is never used
--HG--
extra : convert_revision :
5e6881d467792b670e0009cee8d5e96bc7a79a95
Lisa Hsu [Fri, 15 Dec 2006 17:58:02 +0000 (12:58 -0500)]
tlb.cc:
fix namespace indentations
src/arch/alpha/tlb.cc:
fix namespace indentations
--HG--
extra : convert_revision :
327d5a1568ba60cab1c1ae4bb3963ea78dfe0176
Ali Saidi [Fri, 15 Dec 2006 06:49:41 +0000 (01:49 -0500)]
Use my range_map to speed up findPort() in the bus. The snoop code could still use some work.
--HG--
extra : convert_revision :
ba0a68bd378d68e4ebd80a101b965d36c8be1db9
Ali Saidi [Fri, 15 Dec 2006 06:48:09 +0000 (01:48 -0500)]
Optimized the TLB translations with some caching
--HG--
extra : convert_revision :
f79f863393f918ff9363b2c261f8c0dfec64312e
Ali Saidi [Fri, 15 Dec 2006 00:01:21 +0000 (19:01 -0500)]
flesh out twinx asis
fix TICK register reads
reduce the number of readmiscreg accesses,
implement tsb pointer stuff
src/arch/sparc/asi.cc:
flesh out twinx asis
src/arch/sparc/miscregfile.cc:
fix TICK register reads
src/arch/sparc/tlb.cc:
reduce the number of readmiscreg accesses,
implement tsb pointer stuff
--HG--
extra : convert_revision :
1995c3b04b7743c6122cbf8ded7c4d5de48fa3c8
Steve Reinhardt [Thu, 14 Dec 2006 06:04:36 +0000 (22:04 -0800)]
Split CachePort class into CpuSidePort and MemSidePort
and push those into derived Cache template class to
eliminate a few layers of virtual functions and
conditionals ("if (isCpuSide) { ... }" etc.).
--HG--
extra : convert_revision :
cb1b88246c95b36aa0cf26d534127d3714ddb774
Lisa Hsu [Wed, 13 Dec 2006 22:52:24 +0000 (17:52 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
8cf3e824e4892249b12ed0fd92bb310748b18fa2
Lisa Hsu [Wed, 13 Dec 2006 22:51:28 +0000 (17:51 -0500)]
fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS.
--HG--
extra : convert_revision :
4fdffe01b8e63e24b97a2e4194c747e6cf5e25ba
Lisa Hsu [Wed, 13 Dec 2006 19:33:59 +0000 (14:33 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
82733f9c7bf833cf6bbfbd2aad292f69f52d21bc
Lisa Hsu [Wed, 13 Dec 2006 19:33:32 +0000 (14:33 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
c6d174716641f0b8286b8478bcb9053b3eec54e3
Lisa Hsu [Wed, 13 Dec 2006 02:19:51 +0000 (21:19 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
6e58629b1e51f1fc493a89f16c3f2e676dc5d191
Gabe Black [Tue, 12 Dec 2006 23:10:00 +0000 (18:10 -0500)]
Merge zizzer:/bk/newmem/
into zower.eecs.umich.edu:/eecshome/m5/newmem
--HG--
extra : convert_revision :
17d6c49ee15af5d192dedf82871159219d4277cd
Kevin Lim [Tue, 12 Dec 2006 22:55:50 +0000 (17:55 -0500)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress
--HG--
extra : convert_revision :
d420ee86454b72b0e5d3a98bac3b496f172c1788
Ali Saidi [Tue, 12 Dec 2006 22:55:27 +0000 (17:55 -0500)]
Fix bugs in tlbmap (and thus rangemap since the code is nearly identical)
Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing)
Fix tcc instruction igoner in legion-lock stuff to be correct in all cases
Have console interrupts warn rather than panicing until we figure out what to do with interrupts
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
add a magic miscreg which reads all the bits the tlb needs in one go
src/arch/sparc/tlb.cc:
initialized the context type and id to reasonable values and handle block init stores
src/arch/sparc/tlb_map.hh:
fix bug in tlb map code
src/base/range_map.hh:
fix bug in rangemap code and add range_multimap
(these are probably useful for bus range stuff)
src/cpu/exetrace.cc:
fixup tcc ignore code to be correct
src/dev/sparc/t1000.cc:
make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out
src/unittest/rangemaptest.cc:
fix up the rangemap unit test to catch the missing case
--HG--
extra : convert_revision :
70604a8b5d0553aa0b0bd7649f775a0cfa8267a5
Kevin Lim [Tue, 12 Dec 2006 22:35:46 +0000 (17:35 -0500)]
Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit).
This fixes a minor bug when multiple FU completions come back out of order (due to the order in which the FUs are freed up), and the oldest redirect isn't recorded properly. The eon benchmark should run now.
src/cpu/o3/iew_impl.hh:
Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit).
--HG--
extra : convert_revision :
b7d202dee1754539ed814f0fac59adb8c6328ee1
Steve Reinhardt [Tue, 12 Dec 2006 17:58:40 +0000 (09:58 -0800)]
Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.
--HG--
extra : convert_revision :
b33ce0ebe2fee86cc791c00a35d8c6e395e1380c
Steve Reinhardt [Tue, 12 Dec 2006 17:54:59 +0000 (09:54 -0800)]
If no tests are specified for regression, just build the binaries
(instead of complaining and exiting).
--HG--
extra : convert_revision :
24ac0bab7fd92d9e74c80847a667f0affcd0473d
Steve Reinhardt [Tue, 12 Dec 2006 07:21:03 +0000 (02:21 -0500)]
Get rid of unused lock code.
--HG--
extra : convert_revision :
a8030132268662ca54f487b8d32d09ba224317a8
Kevin Lim [Tue, 12 Dec 2006 04:51:21 +0000 (23:51 -0500)]
Fix up in case a req hasn't yet been generated for this instruction (if there was a fault prior to translation).
--HG--
extra : convert_revision :
43f4ea5e6a234cc6071006eab72135c11b8523c8
Kevin Lim [Tue, 12 Dec 2006 04:47:30 +0000 (23:47 -0500)]
Fix for fetch to use the icache's block size to generate proper access size.
--HG--
extra : convert_revision :
0f292233ac05b584f527c32f80e3ca3d40a6a2c1
Steve Reinhardt [Sun, 10 Dec 2006 07:05:33 +0000 (02:05 -0500)]
Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache3
--HG--
extra : convert_revision :
c961d1bf2acaae6807870b78f444a4a606be65cc
Steve Reinhardt [Sun, 10 Dec 2006 07:04:53 +0000 (02:04 -0500)]
Reorder CacheTags members for better cache performance.
--HG--
extra : convert_revision :
cac6e9d447675805e3fcc4342e3bfdbef179fbf5
Steve Reinhardt [Sun, 10 Dec 2006 06:52:18 +0000 (01:52 -0500)]
Get rid of dummy 'hello world' outputs.
--HG--
extra : convert_revision :
e03634b5ec6b3c855c463618968984b5df7782f9
Steve Reinhardt [Sun, 10 Dec 2006 06:50:12 +0000 (01:50 -0500)]
Delete parser reference outputs so that test will no longer be run.
Runtimes are way too long with current inputs.
--HG--
extra : convert_revision :
19323308b40fb7de00c77ee552e39ca6558804b8
Steve Reinhardt [Sun, 10 Dec 2006 06:42:31 +0000 (01:42 -0500)]
Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache3
--HG--
extra : convert_revision :
7c78ae3298645aed2179ed4f2aa361619406f9de
Steve Reinhardt [Sun, 10 Dec 2006 06:42:16 +0000 (01:42 -0500)]
Add '-j' option directly to regress script (passed to scons).
--HG--
extra : convert_revision :
9776806b24da70b815280e47d2d5ec8674c82669
Steve Reinhardt [Sun, 10 Dec 2006 06:05:30 +0000 (22:05 -0800)]
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2
--HG--
extra : convert_revision :
e1ed5c8edb95e99200b4d26317f55f71338a96df
Ali Saidi [Sat, 9 Dec 2006 23:27:54 +0000 (18:27 -0500)]
fix lisa's hand merge
--HG--
extra : convert_revision :
d25604156ae0b2cf29d92fb960b8f5d77427985b
Ali Saidi [Sat, 9 Dec 2006 23:00:49 +0000 (18:00 -0500)]
Merge zizzer:/bk/sparcfs
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
c51fd95f7acd7cffb3ea705d7216772f0a801844
Ali Saidi [Sat, 9 Dec 2006 23:00:40 +0000 (18:00 -0500)]
Allocate the correct number of global registers
Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data
src/arch/sparc/faults.cc:
Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
cleanup/fix page table code
src/arch/sparc/tlb.cc:
implement more mmaped iprs, fix numbered insertion code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.
--HG--
extra : convert_revision :
d7d771900f6f25219f3dc6a6e51986d342a32e03
Lisa Hsu [Fri, 8 Dec 2006 20:07:26 +0000 (15:07 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
src/arch/sparc/ua2005.cc:
hand merge
--HG--
extra : convert_revision :
5157fa5d7053cb93f73241c63871eaae6f58b8a6
Lisa Hsu [Fri, 8 Dec 2006 19:37:31 +0000 (14:37 -0500)]
mostly implemented SOFTINT relevant interrupt stuff.
src/arch/sparc/interrupts.hh:
add in thread_context.hh to get access to tc.
get rid of stubs that don't make sense right now.
implement checking and get softint interrupts
src/arch/sparc/miscregfile.cc:
softint should be OR-ed on a write.
src/arch/sparc/miscregfile.hh:
add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs.
src/arch/sparc/ua2005.cc:
implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write.
--HG--
extra : convert_revision :
d12d1147b508121075ee9be4599693554d4b9eae
Gabe Black [Fri, 8 Dec 2006 00:00:46 +0000 (19:00 -0500)]
Fixed to take into account the misc regs that became int regs.
--HG--
extra : convert_revision :
b4f78f6e48fdd2f1774ba63b28615e0d2556b7b9
Ali Saidi [Thu, 7 Dec 2006 23:50:33 +0000 (18:50 -0500)]
get legion/m5 to first tlb miss fault
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
add sparc error asi
src/arch/sparc/faults.cc:
put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
add sparc error register code that just does nothing
fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
fix implementation of HPSTATE write
src/cpu/exetrace.cc:
let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
add l2 error status register fake devices
--HG--
extra : convert_revision :
ed5dfdfb28633bf36e5ae07d244f7510a02874ca
Gabe Black [Thu, 7 Dec 2006 23:49:10 +0000 (18:49 -0500)]
Compilation fixes
--HG--
extra : convert_revision :
974e91a960251a35d5ebb76c7e6c7ac330339896
Gabe Black [Thu, 7 Dec 2006 23:47:33 +0000 (18:47 -0500)]
Fix for squashing during a serializing instruction.
--HG--
extra : convert_revision :
04f9131258bfb7cca1654e00273edb29bde2366b
Gabe Black [Thu, 7 Dec 2006 23:45:30 +0000 (18:45 -0500)]
Make branches handle the lack of a symbol table or the lack of a symbol gracefully.
--HG--
extra : convert_revision :
7bb16405999b86f9fa082a6d44da43d346edc182
Gabe Black [Thu, 7 Dec 2006 23:43:55 +0000 (18:43 -0500)]
Change how Page Faults work in SPARC. It now prints the faulting address, and panics instead of fatals. This isn't technically what it should do, but it makes gdb stop at the panic rather than letting m5 exit.
--HG--
extra : convert_revision :
3b14c99edaf649e0809977c9579afb2b7b0d72e9
Steve Reinhardt [Thu, 7 Dec 2006 19:41:56 +0000 (14:41 -0500)]
Change detault regression build from opt to fast.
--HG--
extra : convert_revision :
b6db0254b73a97ab6e3685c90cc9cd30ea274d4f
Ali Saidi [Thu, 7 Dec 2006 00:25:53 +0000 (19:25 -0500)]
Handle access to ASI_QUEUE
Add function for interrupt ASIs
add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
Add function for interrupt ASIs
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
Add QUEUE asi/misc registers
src/arch/sparc/regfile.cc:
add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/tlb.cc:
Handle access to ASI_QUEUE
--HG--
extra : convert_revision :
7a14450485816e6ee3bc8c80b462a13e1edf0ba0
Ali Saidi [Wed, 6 Dec 2006 19:29:10 +0000 (14:29 -0500)]
Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts
getting touched.
configs/common/FSConfig.py:
Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
Fix AsiIsNucleus spelling with respect to header file
Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
Flesh out priviledgedString with hypervisor checks
Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
add an IPR traceflag
src/mem/request.hh:
Fix a bad assert() in request
--HG--
extra : convert_revision :
1e11aa004e8f42c156e224c1d30d49479ebeed28
Kevin Lim [Wed, 6 Dec 2006 19:23:31 +0000 (14:23 -0500)]
Fix for MIPS_SE/m5.fast compile.
--HG--
extra : convert_revision :
dbb893250974ac6db7b6c1ba67263fd35098ca43
Gabe Black [Wed, 6 Dec 2006 16:40:41 +0000 (11:40 -0500)]
Use the renamed register index, rather than the flattened one.
--HG--
extra : convert_revision :
599650c408667bb1b8db20a6847b9e697f7b49e4
Gabe Black [Wed, 6 Dec 2006 16:39:49 +0000 (11:39 -0500)]
Got rid of some typedefs and moved the tlbs into the base o3 cpu.
--HG--
extra : convert_revision :
dcd1d2a64fd91aded15c8c763a78b4eebf421870
Gabe Black [Wed, 6 Dec 2006 16:38:39 +0000 (11:38 -0500)]
Use the setSyscallReturn defined in arch rather than duplicating it here.
--HG--
extra : convert_revision :
862ece59aa253b52b6744a0a76738d5ee19561b3
Gabe Black [Wed, 6 Dec 2006 16:37:39 +0000 (11:37 -0500)]
Moved the RegIdx arrays to the base dyninst.
--HG--
extra : convert_revision :
d705cde25c2cf1add20669e99d086add49141518
Gabe Black [Wed, 6 Dec 2006 16:36:40 +0000 (11:36 -0500)]
Got rid of some typedefs, moved the tlbs to the base o3 cpu, and called the architecture defined setSyscallReturn function instead of a duplicate copy.
src/cpu/o3/alpha/cpu.hh:
Got rid of some typedefs, and moved the tlbs to the base o3 cpu.
src/cpu/o3/alpha/thread_context.hh:
src/cpu/o3/cpu.cc:
Moved the tlbs to the base o3 cpu.
--HG--
extra : convert_revision :
1805613aa230b8974a226ee3d2584c85f7a578aa
Gabe Black [Wed, 6 Dec 2006 16:33:37 +0000 (11:33 -0500)]
Made the alpha setSyscallReturn take a ThreadContext pointer instead of a RegFile *.
--HG--
extra : convert_revision :
021a1fe6760df1daf6299d46060371a5310f008a
Gabe Black [Wed, 6 Dec 2006 16:30:41 +0000 (11:30 -0500)]
Added a flattenIntIndex function for Alpha.
--HG--
extra : convert_revision :
5ed79ed18e443118a28d6890327c55a6a3fcd325
Gabe Black [Wed, 6 Dec 2006 11:05:28 +0000 (06:05 -0500)]
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem
src/cpu/o3/commit_impl.hh:
Hand Merge
--HG--
extra : convert_revision :
6984db90d5b5ec71c31f1c345f5a77eed540059e
Gabe Black [Wed, 6 Dec 2006 11:02:13 +0000 (06:02 -0500)]
Added a DPRINTF to print out the actual value pulled from memory.
--HG--
extra : convert_revision :
18780f753a7e98f8de3047dd6781b944b0826b4e
Gabe Black [Wed, 6 Dec 2006 11:00:04 +0000 (06:00 -0500)]
Flattening and syscallReturn fixes
src/cpu/o3/thread_context_impl.hh:
Use flattened indices
src/cpu/simple_thread.hh:
Use flattened indices, and pass a thread context to setSyscallReturn rather than a register file.
src/cpu/thread_context.hh:
The SyscallReturn class is no longer in arch/syscallreturn.hh
--HG--
extra : convert_revision :
ed84bb8ac5ef0774526ecd0d7270b0c60cd3708e
Gabe Black [Wed, 6 Dec 2006 10:58:07 +0000 (05:58 -0500)]
Don't panic, but this needs to be fixed.
--HG--
extra : convert_revision :
7a4aed238d437dbb2cc5946b3045d53697070a27
Gabe Black [Wed, 6 Dec 2006 10:56:34 +0000 (05:56 -0500)]
Make syscalls flatten their register indices, and also call into the ISA's setSyscallReturn function rather than having a duplicated one.
--HG--
extra : convert_revision :
1e83ef629a7fd143f2e35e68abaa56f81d6b9d9e
Gabe Black [Wed, 6 Dec 2006 10:55:23 +0000 (05:55 -0500)]
Change rename to rename the flattened register index instead of the architectural one.
--HG--
extra : convert_revision :
757866ad7a3c8be7382e1ffa71c60bc00c861f6f
Gabe Black [Wed, 6 Dec 2006 10:54:16 +0000 (05:54 -0500)]
Added in endianness conversion on memory accesses as the data goes out. This will break the checker!
--HG--
extra : convert_revision :
b8191cab09ab8f3ced05693293f058382319ed8e
Gabe Black [Wed, 6 Dec 2006 10:51:18 +0000 (05:51 -0500)]
Change how optional delay slot instructions are detected and squashed.
--HG--
extra : convert_revision :
ffd019d4adc2fbbc0a663d8dc6ef73edce12511b
Gabe Black [Wed, 6 Dec 2006 10:48:59 +0000 (05:48 -0500)]
Get rid of some typedefs which were hardly used, and move some stuff back here that shouldn't be in the architecture specific DynInst classes.
--HG--
extra : convert_revision :
dad0d7191acf773c16dc3ed9dd911f5e8bfc08b3