Gabe Black [Wed, 19 Jul 2006 06:07:00 +0000 (02:07 -0400)]
Cleaned things up a little.
--HG--
extra : convert_revision :
7091b0d02e5b7c80be43b5ab1ac003dc89c4c136
Gabe Black [Tue, 18 Jul 2006 22:23:23 +0000 (18:23 -0400)]
Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem
--HG--
extra : convert_revision :
516c357f98c7a571c70362babd3fa162fbc2ed5a
Korey Sewell [Mon, 17 Jul 2006 20:50:20 +0000 (16:50 -0400)]
update test3
--HG--
extra : convert_revision :
e41feeee87d1da348604a37f7349900dcbd3a4d9
Korey Sewell [Fri, 14 Jul 2006 17:22:35 +0000 (13:22 -0400)]
forgot tid
--HG--
extra : convert_revision :
272ef8f9cd0802770edc4dcef2c26dc44de71e47
Korey Sewell [Fri, 14 Jul 2006 17:06:37 +0000 (13:06 -0400)]
For now, halt context is the same as deallocating.
suspend context will now take the thread off the activeThread list.
src/arch/mips/isa_traits.cc:
add in copy MiscRegs unimplemented function
--HG--
extra : convert_revision :
3ed5320b3786f84d4bb242e3a32b6f415339c3ba
Korey Sewell [Fri, 14 Jul 2006 08:52:08 +0000 (04:52 -0400)]
MIPS specific fixes ... the main thing is that SMT threads get their own stack space instead of all stacks start to space
src/arch/mips/isa_traits.hh:
MaxAddr is defined in config.py now
src/arch/mips/process.cc:
adjust process so SMT threads get their own stack space
src/arch/mips/process.hh:
add stack_start static variable
--HG--
extra : convert_revision :
73fdf3da9831d86536651835d209806c7f0d59da
Ali Saidi [Thu, 13 Jul 2006 19:50:09 +0000 (15:50 -0400)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
src/python/m5/main.py:
merge two help fixes
--HG--
extra : convert_revision :
b5c4a88bb84b726bebd3e357a4ef29acc0d95600
Ali Saidi [Thu, 13 Jul 2006 19:48:41 +0000 (15:48 -0400)]
fix help when no arguments are passed to m5
--HG--
extra : convert_revision :
ee6614166fd5814654309298abe5a706ff02c4c2
Ali Saidi [Thu, 13 Jul 2006 19:48:17 +0000 (15:48 -0400)]
add system.mem_mode = ['timing', 'atomic']
update scripts acordingly
configs/test/SysPaths.py:
new syspaths from nate, this one allows you to set script, binary, and disk paths like
system.dir = 'aouaou' in your script
configs/test/fs.py:
update for system mem_mode
Put small checkpoint example
Make clock 1THz
configs/test/test.py:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/system.cc:
src/arch/alpha/tru64/system.cc:
src/arch/sparc/system.cc:
src/python/m5/objects/System.py:
src/sim/system.cc:
src/sim/system.hh:
update for system mem_mode
src/dev/io_device.cc:
Use time returned from sendAtomic to delay
--HG--
extra : convert_revision :
67eedb3c84ab2584613faf88a534e793926fc92f
Kevin Lim [Thu, 13 Jul 2006 17:12:51 +0000 (13:12 -0400)]
Move Dcache port creation from LSQUnit to LSQ in order to support Ron's recent changes, and using the O3CPU in SMT mode.
src/cpu/o3/lsq.hh:
Update to have LSQ work with only one dcache port for all LSQ Units. LSQ has the dcache port, and the LSQ Units must tell the LSQ if the cache has become blocked.
src/cpu/o3/lsq_impl.hh:
Updates to have the LSQ work with only one dcache port for all LSQUnits.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
Update for LSQ to create dcache port instead of LSQUnits. Now LSQUnits are given the dcache port from the LSQ, and also must check the LSQ if the cache is blocked prior to accessing the cache.
--HG--
extra : convert_revision :
2708adbf323f4e7647dc0c1e31ef5bb4596b89f8
Kevin Lim [Thu, 13 Jul 2006 17:09:29 +0000 (13:09 -0400)]
Fix for bug when squashing and the fetching. Now fetch checks if the cache data is valid.
--HG--
extra : convert_revision :
07b8eda3e90bbbb3ed470c8cc3cf1b63371ab529
Kevin Lim [Thu, 13 Jul 2006 17:08:58 +0000 (13:08 -0400)]
Update for changes to draining.
--HG--
extra : convert_revision :
5038dd8be72827f40cf89318db0b2bb4f9bbd864
Kevin Lim [Thu, 13 Jul 2006 16:21:21 +0000 (12:21 -0400)]
Fix help message printing. Might need to clean up the handling of the sys.exit() call, as right now it prints out "None" at the end (not sure why).
src/python/m5/main.py:
Fix help message printing.
--HG--
extra : convert_revision :
6906234101eb7ff7df7933e9aede0362b5a991bd
Ali Saidi [Thu, 13 Jul 2006 00:22:07 +0000 (20:22 -0400)]
memory mode information now contained in system object
States are now running, draining, or drained. memory state information moved into system object
system parameter is not fs only for cpus
Implement drain() support in devices
Update for drain() call that returns number of times drain_event->process() will be called
Break O3 CPU! No sense in putting in a hack change that kevin is going to remove in a few minutes i imagine
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
Since se mode has a system, allow access to it
Verify that the atomic cpu is connected to an atomic system on resume
src/cpu/simple/base.cc:
Since se mode has a system, allow access to it
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Update for new drain() call that returns number of times drain_event->process() will be called and memory state being moved into the system
Since se mode has a system, allow access to it
Verify that the timing cpu is connected to an timing system on resume
src/dev/ide_disk.cc:
src/dev/io_device.cc:
src/dev/io_device.hh:
src/dev/ns_gige.cc:
src/dev/ns_gige.hh:
src/dev/pcidev.cc:
src/dev/pcidev.hh:
src/dev/sinic.cc:
src/dev/sinic.hh:
Implement drain() support in devices
src/python/m5/config.py:
Allow drain to return number of times drain_event->process() will be called. Normally 0 or 1 but things like O3 cpu or devices with multiple ports may want to call it many times
src/python/m5/objects/BaseCPU.py:
move system parameter out of fs to everyone
src/sim/sim_object.cc:
src/sim/sim_object.hh:
States are now running, draining, or drained. memory state information moved into system object
src/sim/system.cc:
src/sim/system.hh:
memory mode information now contained in system object
--HG--
extra : convert_revision :
1389c77e66ee6d9710bf77b4306fb47e107b21cf
Kevin Lim [Wed, 12 Jul 2006 19:25:34 +0000 (15:25 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
src/cpu/o3/fetch_impl.hh:
Hand merge.
--HG--
extra : convert_revision :
820dab2bc921cbadecaca51cd069327f984f5c74
Kevin Lim [Wed, 12 Jul 2006 19:24:27 +0000 (15:24 -0400)]
Track the PC of the cache data stored in fetch so it doesn't access memory multiple times if information is already in fetch.
--HG--
extra : convert_revision :
00b160b255e998cf99286bcc21894110c7642624
Nathan Binkert [Wed, 12 Jul 2006 19:21:23 +0000 (15:21 -0400)]
Add --pdb
src/python/m5/main.py:
Add a command line option to invoke pdb on your script
--HG--
extra : convert_revision :
ef5a2860bd3f6e479fa80eccaae0cb5541a20b50
Nathan Binkert [Wed, 12 Jul 2006 19:19:08 +0000 (15:19 -0400)]
Merge m5.eecs.umich.edu:/bk/newmem
into iceaxe.:/Volumes/work/research/m5/current
--HG--
extra : convert_revision :
842a23da034c40c75364b76ca75de076da776ac6
Nathan Binkert [Wed, 12 Jul 2006 19:18:49 +0000 (15:18 -0400)]
Fix __file__ for scripts
src/python/m5/main.py:
set __file__ to the script, not the m5 binary.
--HG--
extra : convert_revision :
a0bbd059d2fd321ae8ff68225abc8a7bb5c410ed
Ron Dreslinski [Tue, 11 Jul 2006 20:03:42 +0000 (16:03 -0400)]
Add a cache version of FS (should really make this an option in original)
Now to work on caches in FS, first steps:
1) LL/SC support (Top Level Cache Hooks)
2) Snooping in the bus (CSHR's for DMA Invalidates)
--HG--
extra : convert_revision :
b4e7984712f7dcd42649070c5ca538c87461e179
Ron Dreslinski [Tue, 11 Jul 2006 19:42:49 +0000 (15:42 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem
--HG--
extra : convert_revision :
3be1aa4892aa8bbd458bdc5538bbcbd6c1ebe299
Ron Dreslinski [Tue, 11 Jul 2006 19:42:31 +0000 (15:42 -0400)]
Fix ordering issue with squashed Icache Fetches and Static data in packet.
Now hello world works with 2 levels of cache with O3 CPU(multiple outstanding requests).
src/cpu/o3/fetch_impl.hh:
Fix ordering issue with squashed Icache Fetches and Static data in packet.
--HG--
extra : convert_revision :
a6adb87540b007ead0b4982cb3f31da8199fb5ca
Kevin Lim [Tue, 11 Jul 2006 17:43:30 +0000 (13:43 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
--HG--
extra : convert_revision :
c565fd7cebaa4058ba510b3db50a9c76bf301228
Nathan Binkert [Tue, 11 Jul 2006 15:28:59 +0000 (11:28 -0400)]
Fix option parsing.
src/python/m5/main.py:
Don't allow interspersed arguments, it messes things up
--HG--
extra : convert_revision :
8f1bcf4391f570741d92bf5420879862a48f6016
Nathan Binkert [Tue, 11 Jul 2006 03:00:13 +0000 (23:00 -0400)]
Migrate most of main() and and all option parsing to python
configs/test/fs.py:
configs/test/test.py:
update for the new way that m5 deals with options
src/python/SConscript:
Compile AUTHORS, LICENSE, README, and RELEASE_NOTES into the
python stuff.
src/python/m5/__init__.py:
redo the way options work.
Move them all to main.py
src/sim/main.cc:
Migrate more functionality for main() into python.
Namely option parsing
src/python/m5/attrdict.py:
A dictionary object that overrides attribute access to
do item access.
src/python/m5/main.py:
The new location for M5's option parsing, and the main()
routine to set up the simulation.
--HG--
extra : convert_revision :
c86b87a9f508bde1994088e23fd470c7753ee4c1
Ron Dreslinski [Mon, 10 Jul 2006 21:19:54 +0000 (17:19 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem
--HG--
extra : convert_revision :
c811eb9eacc480b14862f8074af80c56ec1e07f1
Ron Dreslinski [Mon, 10 Jul 2006 21:16:15 +0000 (17:16 -0400)]
Some fixes so that MSHR's are matched and we don't issue overlapping requests with detailed cpu
src/mem/cache/base_cache.cc:
If we still have outstanding requests, need to schedule event again
src/mem/cache/miss/miss_queue.cc:
Need to use block size so overlapping requests match in the MSHR's
src/mem/cache/miss/mshr.cc:
Actually save the address, otherwise we can't match MSHR's
--HG--
extra : convert_revision :
f0f018b89c2fb99f3ce8d6eafc0712ee8edeeda8
Kevin Lim [Mon, 10 Jul 2006 20:31:42 +0000 (16:31 -0400)]
Minor fixes.
src/cpu/checker/thread_context.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
Change functions to match Korey's changes.
src/cpu/ozone/lw_back_end.hh:
Fix compile error.
--HG--
extra : convert_revision :
fb11ac2d6db3a75c1cdbad2c1c02f921ad7344a6
Kevin Lim [Mon, 10 Jul 2006 19:41:35 +0000 (15:41 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
0e4c7684879b8552908e0b64a00b4824de807244
Kevin Lim [Mon, 10 Jul 2006 19:41:28 +0000 (15:41 -0400)]
Some minor cleanups.
src/cpu/SConscript:
Change the error message to be slightly nicer.
src/cpu/o3/commit.hh:
Remove old code.
src/cpu/o3/commit_impl.hh:
Remove old unused code.
--HG--
extra : convert_revision :
48aa430e1f3554007dd5e4f3d9e89b5e4f124390
Kevin Lim [Mon, 10 Jul 2006 19:40:28 +0000 (15:40 -0400)]
Add parameters for backwards and forwards sizes for time buffers.
src/base/timebuf.hh:
Add a function to return the size of the time buffer.
--HG--
extra : convert_revision :
8ffacd8b9013eb76264df065244e00dc1460efd4
Ron Dreslinski [Mon, 10 Jul 2006 16:42:35 +0000 (12:42 -0400)]
Update config for a system with an L2
--HG--
extra : convert_revision :
c73a532ad6ad8d5115bda81fa778a4b97fbab713
Ron Dreslinski [Mon, 10 Jul 2006 16:35:18 +0000 (12:35 -0400)]
Fix offset calculation. Now L2's work with timing&atomic.
src/mem/packet.hh:
Offset is based on packet, not request.
--HG--
extra : convert_revision :
d85af5838370541328ca35072c612d8198020625
Ron Dreslinski [Mon, 10 Jul 2006 16:07:21 +0000 (12:07 -0400)]
Update FS configs to use cpu connectors for ports
--HG--
extra : convert_revision :
1e2e503401f92c1f30e2e487d7aeed1c7c5b7ee4
Ron Dreslinski [Mon, 10 Jul 2006 16:03:13 +0000 (12:03 -0400)]
Fix cpu in full system to match SE.
--HG--
extra : convert_revision :
95e422221ff5bab6104925d50a8882d31729b0f5
Korey Sewell [Fri, 7 Jul 2006 23:02:12 +0000 (19:02 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision :
9098d989832e2a5818b80771e3c02170c5c8cd5b
Kevin Lim [Fri, 7 Jul 2006 22:24:13 +0000 (18:24 -0400)]
Support for recent port changes.
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/python/m5/objects/OzoneCPU.py:
Support Ron's recent port changes.
src/cpu/ozone/lw_back_end_impl.hh:
Support Ron's recent port changes. Also support handling faults in SE.
--HG--
extra : convert_revision :
aa1ba5111b70199c052da3e13bae605525a69891
Kevin Lim [Fri, 7 Jul 2006 21:33:24 +0000 (17:33 -0400)]
Support Ron's changes for hooking up ports.
src/cpu/checker/cpu.hh:
Now that BaseCPU is a MemObject, the checker must define this function.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_unit.hh:
Implement getPort function so the connector can connect the ports properly.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
The connector handles connecting the ports now.
src/python/m5/objects/O3CPU.py:
Add ports to the parameters.
--HG--
extra : convert_revision :
0b1a216b9a5d0574e62165d7c6c242498104d918
Kevin Lim [Fri, 7 Jul 2006 20:48:44 +0000 (16:48 -0400)]
Fix for bug when draining and a memory access is outstanding.
--HG--
extra : convert_revision :
1af782cf023ae74c2a3ff9f7aefcea880bc87936
Kevin Lim [Fri, 7 Jul 2006 20:47:28 +0000 (16:47 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
e8933f852352164f4e50444f94cc6ee260e06766
Kevin Lim [Fri, 7 Jul 2006 20:46:08 +0000 (16:46 -0400)]
Take the name of the checkpoint directory in when calling checkpoint() or restoreCheckpoint().
src/sim/main.cc:
src/sim/serialize.cc:
src/sim/serialize.hh:
Take in the directory name when checkpointing.
--HG--
extra : convert_revision :
040e828622480f1051e2156f4439e24864c38d45
Korey Sewell [Fri, 7 Jul 2006 20:19:13 +0000 (16:19 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision :
be8b295ebf54a7c6bf720a20ab6aa9f02aee8060
Ron Dreslinski [Fri, 7 Jul 2006 20:02:22 +0000 (16:02 -0400)]
Fix address range calculation. Still need bus to handle snoop ranges.
On the way towards multi-level caches (L2)
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
Fix address range calculation. Still need bus to handle snoop ranges.
--HG--
extra : convert_revision :
800078d88aab5e563f4a9bb599f91cd44f36e625
Korey Sewell [Fri, 7 Jul 2006 19:58:22 +0000 (15:58 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision :
f97469b7d19c82deb3d068f80546d729757c25e3
Korey Sewell [Fri, 7 Jul 2006 19:58:03 +0000 (15:58 -0400)]
Minor fix for SMT Hello Worlds to finish correctly.
Still, there is a problem with the LSQ and indexing out of range in the buffer.
I havent nailed down the fix yet, but it's coming ...
src/cpu/o3/commit_impl.hh:
add space to DPRINT
src/cpu/o3/cpu.cc:
add newline to DPRINT
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
Each thread needs it's own squashedSeqNum for the case where they are both squashing at the same time and they dont
write over each other's squash number.
--HG--
extra : convert_revision :
2155421a8b5b20e4544eea3d3c53d3e715465fa6
Kevin Lim [Fri, 7 Jul 2006 19:38:15 +0000 (15:38 -0400)]
Switch out fixes for CPUs.
src/cpu/o3/cpu.cc:
Fix up keeping proper state when switched out and drained.
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Keep track of the event we use to schedule fetch initially and upon resume. We may have to cancel the event if the CPU is switched out.
--HG--
extra : convert_revision :
60a2a1bd2cdc67bd53ca4a67aa77166c826a4c8c
Ron Dreslinski [Fri, 7 Jul 2006 19:16:41 +0000 (15:16 -0400)]
Remove hack now that ports work properly
--HG--
extra : convert_revision :
43c22294867d7cbbc67ae66ec41a1d1c89f5a59d
Ron Dreslinski [Fri, 7 Jul 2006 19:15:11 +0000 (15:15 -0400)]
Update cpus to use the getPort function to use a connector object to connect the I/D cache ports to memory
configs/test/test.py:
Update to use new cpu getPort functionality
src/cpu/base.cc:
Make cpu's a memObject to expose getPort interface
src/cpu/base.hh:
Make cpu's a memObject to export getPort interface
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Now use the connector via getPort interface
src/mem/cache/base_cache.cc:
Make sure the cache recognizes all port names
--HG--
extra : convert_revision :
dbfefa978ec755bc8aa6f962ae158acf32dafe61
Korey Sewell [Fri, 7 Jul 2006 08:07:00 +0000 (04:07 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision :
90717b492139428e0c48be35a6bda45960c61086
Korey Sewell [Fri, 7 Jul 2006 08:06:26 +0000 (04:06 -0400)]
Fix so that O3CPU doesnt segfault on exit.
Major thing was to not execute commit if there are no active threads in CPU.
src/cpu/o3/alpha/thread_context.hh:
call deallocate instead of deallocateContext
src/cpu/o3/commit_impl.hh:
dont run commit stage if there are no instructions
src/cpu/o3/cpu.cc:
add deallocate event, deactivateThread function, and edit deallocateContext.
src/cpu/o3/cpu.hh:
add deallocate event and add optional delay to deallocateContext
src/cpu/o3/thread_context.hh:
optional delay for deallocate
src/cpu/o3/thread_context_impl.hh:
edit DPRINTFs to say Thread Context instead of Alpha TC
src/cpu/thread_context.hh:
optional delay
src/sim/syscall_emul.hh:
name stuff
--HG--
extra : convert_revision :
f4033e1f66b3043d30ad98dcc70d8b193dea70b6
Kevin Lim [Fri, 7 Jul 2006 03:20:44 +0000 (23:20 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
942c43e2fdd68cde7aaaba5e88a667f80feab162
Kevin Lim [Fri, 7 Jul 2006 03:16:22 +0000 (23:16 -0400)]
Be sure to call resume after restoring from a checkpoint.
--HG--
extra : convert_revision :
4d672917038779a23f4ce7eb5d4e3039c1f5d726
Kevin Lim [Fri, 7 Jul 2006 03:13:38 +0000 (23:13 -0400)]
Support serializing and unserializing in the O3 CPU. Also a few small fixes for draining/switching CPUs.
src/cpu/o3/commit_impl.hh:
Fix to clear drainPending variable on call to resume.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
Support serializing and unserializing in the O3 CPU.
src/cpu/o3/lsq_impl.hh:
Be sure to say we have no stores to write back if the active thread list is empty.
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
Slightly change how SimpleThread is used to copy from other ThreadContexts.
--HG--
extra : convert_revision :
92a5109b3783a989d5b451036061ef82c56d3121
Kevin Lim [Thu, 6 Jul 2006 21:57:20 +0000 (17:57 -0400)]
Fix the O3CPU to support the multi-pass method for checking if the system has fully drained.
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
Return a value so that the CPU can instantly return from draining if the pipeline is already drained.
src/cpu/o3/cpu.cc:
Use values returned from pipeline stages so that the CPU can instantly return from draining if the pipeline is already drained.
--HG--
extra : convert_revision :
d8ef6b811644ea67c8b40c4719273fa224105811
Kevin Lim [Thu, 6 Jul 2006 21:53:26 +0000 (17:53 -0400)]
Various serialization changes to make it possible for the O3CPU to checkpoint.
src/arch/alpha/regfile.hh:
Define serialize/unserialize functions on MiscRegFile itself.
src/cpu/o3/regfile.hh:
Remove old commented code.
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
Push common serialization code to ThreadState level. Also allow the SimpleThread to be used for checkpointing by other models.
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
Move common serialization code into ThreadState.
--HG--
extra : convert_revision :
ef64ef515355437439af967eda2e610e8c1b658b
Ron Dreslinski [Thu, 6 Jul 2006 20:52:05 +0000 (16:52 -0400)]
Timing cache works for hello world test.
Still need
1) detailed CPU (blocking ability in cache)
1a) Multiple outstanding requests (need to keep track of times for events)
2)Multi-level support
3)MP coherece support
4)LL/SC support
5)Functional path needs to be correctly implemented (temporarily works without multiple outstanding requests (simple cpu))
src/cpu/simple/timing.cc:
Temp hack because timing cpu doesn't export ports properly so single I/D cache communicates only through the Icache port.
src/mem/cache/base_cache.cc:
Handle marking MSHR's in service
Add support for getting CSHR's
src/mem/cache/base_cache.hh:
Make these functions visible at the base cache level
src/mem/cache/cache.hh:
make the functions virtual
src/mem/cache/cache_impl.hh:
Rename the function to make sense
src/mem/packet.hh:
Accidentally clearing the needsResponse field when sending a response back.
--HG--
extra : convert_revision :
2325d4e0b77e470fa9da91490317dc8ed88b17e2
Kevin Lim [Thu, 6 Jul 2006 20:51:50 +0000 (16:51 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
--HG--
extra : convert_revision :
7c7fc8a2f9579d443786e86dbcf906b355de69fc
Kevin Lim [Thu, 6 Jul 2006 20:26:44 +0000 (16:26 -0400)]
Two minor FS compile fixes.
src/dev/tsunami_pchip.hh:
Need ULL() for 32-bit hosts.
src/sim/pseudo_inst.cc:
Forgot to remove sampler include from here.
--HG--
extra : convert_revision :
6ab6bdc721290167b4c2b78da3d28a4992eb24d5
Kevin Lim [Thu, 6 Jul 2006 20:06:00 +0000 (16:06 -0400)]
Fixes for draining.
src/cpu/simple/timing.cc:
Update for changed return values.
src/python/m5/__init__.py:
Loop in order to make sure all objects are really drained. Objects may become undrained as other objects become drained (e.g. a bus-bridge has a packet, while a bus is empty, and the first drain() will cause the bus-bridge to give the packet to the bus).
The only case we know every object is actually drained is if they all return immediately that they are drained.
--HG--
extra : convert_revision :
80057a1d6d30381bd0b67b23549bd202f447c5cb
Ron Dreslinski [Thu, 6 Jul 2006 19:16:15 +0000 (15:16 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem
--HG--
extra : convert_revision :
507eefde3514c35ca8420408cc89590d83cc6fc6
Ron Dreslinski [Thu, 6 Jul 2006 19:15:37 +0000 (15:15 -0400)]
Now timing reads work in single level of cache with simple cpu
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
Changes to handle timing reads in Simple CPU (blocking buffers)
--HG--
extra : convert_revision :
a2e7d4287d7cdfd1bbf9c929ecbeafde499a5b9f
Kevin Lim [Thu, 6 Jul 2006 18:54:09 +0000 (14:54 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
0c4fbbe0826358a6a58f844bec34ce830ffd4ced
Ali Saidi [Thu, 6 Jul 2006 18:41:09 +0000 (14:41 -0400)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
4669e87d29fa3e0ca9009f6b9dce72113220d7bc
Ali Saidi [Thu, 6 Jul 2006 18:41:01 +0000 (14:41 -0400)]
Add default responder to bus
Update configuration for new default responder on bus
Update to devices to handle their own pci config space without pciconfigall
Remove most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for
Remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same
bus:dev:func and interrupt
Remove pciconfigspace from pci devices, and py files
Add calcConfigAddr that returns address for config space based on bus/dev/function + offset
configs/test/fs.py:
Update configuration for new default responder on bus
src/dev/ide_ctrl.cc:
src/dev/ide_ctrl.hh:
src/dev/ns_gige.cc:
src/dev/ns_gige.hh:
src/dev/pcidev.cc:
src/dev/pcidev.hh:
Update to handle it's own pci config space without pciconfigall
src/dev/io_device.cc:
src/dev/io_device.hh:
change naming for pio port
break out recvTiming into two functions to reuse code
src/dev/pciconfigall.cc:
src/dev/pciconfigall.hh:
removing most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for
src/dev/pcireg.h:
add a max size for PCI config space (per PCI spec)
src/dev/platform.cc:
src/dev/platform.hh:
remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same
bus:dev:func and interrupt
src/dev/sinic.cc:
remove pciconfigspace as it's no longer a needed parameter
src/dev/tsunami.cc:
src/dev/tsunami.hh:
src/dev/tsunami_pchip.cc:
src/dev/tsunami_pchip.hh:
add calcConfigAddr that returns address for config space based on bus/dev/function + offset (per PCI spec)
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
add idea of default responder to bus
src/python/m5/objects/Pci.py:
add config port for pci devices
add latency, bus and size parameters for pci config all (min is 8MB, max is 256MB see pci spec)
--HG--
extra : convert_revision :
99db43b0a3a077f86611d6eaff6664a3885da7c9
Kevin Lim [Thu, 6 Jul 2006 17:59:13 +0000 (13:59 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
00f8eecf99c771ae8943ed1d3a652bfbcfe1c6bc
Kevin Lim [Thu, 6 Jul 2006 17:59:02 +0000 (13:59 -0400)]
Support for draining, and the new method of switching out. Now switching out happens after the pipeline has been drained, deferring the three way handshake to the normal drain mechanism. The calls of switchOut() and takeOverFrom() both take action immediately.
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
Support for draining, new method of switching out.
--HG--
extra : convert_revision :
05bf8b271ec85b3e2c675c3bed6c42aeba21f465
Kevin Lim [Thu, 6 Jul 2006 17:57:21 +0000 (13:57 -0400)]
Change the return value of drain. False means the object wasn't able to drain yet.
src/python/m5/config.py:
Invert the return value.
src/sim/sim_object.cc:
Invert the return value of drain.
src/sim/sim_object.hh:
Change the return value of drain.
--HG--
extra : convert_revision :
41bb122c6f29302d8b3815d7bd6a2ea8fba64df9
Korey Sewell [Thu, 6 Jul 2006 16:29:34 +0000 (12:29 -0400)]
Had to add this because for some reason gcc wasnt recognizing "THE_ISA == ALPHA_ISA"... wierd but OK
--HG--
extra : convert_revision :
f847d6c01212e32200a319c16596b8e1c1d15c7d
Korey Sewell [Thu, 6 Jul 2006 16:19:29 +0000 (12:19 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision :
2f08ea52ef54118d42aa590c0d86aa0cc7988713
Korey Sewell [Thu, 6 Jul 2006 16:18:55 +0000 (12:18 -0400)]
Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst.
src/cpu/cpu_models.py:
Use O3DynInst
src/cpu/o3/dyn_inst.hh:
declare O3DynInst here based off of ISA ... this must be updated for each ISA.
src/cpu/static_inst.hh:
take out O3 forward declarations here and include header file to keep this file clean
--HG--
extra : convert_revision :
0d65463479c3cfc2d1154935b1032dae32c5efd0
Korey Sewell [Thu, 6 Jul 2006 15:25:44 +0000 (11:25 -0400)]
more steps toward O3 SMT
src/arch/mips/isa/formats/fp.isa:
Adjust for newmem
src/cpu/cpu_models.py:
Use O3DynInst instead of convoluted way
src/cpu/o3/alpha/impl.hh:
take out O3DynInst typedef here ...
src/cpu/o3/cpu.cc:
open up the SMT functions in the O3CPU
src/cpu/static_inst.hh:
Add O3DynInst
src/cpu/o3/dyn_inst.hh:
Use to get ISA-specific O3DynInst
--HG--
extra : convert_revision :
3713187ead93e336e80889e23a1f1d2f36d664fe
Kevin Lim [Thu, 6 Jul 2006 03:38:11 +0000 (23:38 -0400)]
For now using the checkpoint or switchcpu pseudo instructions will return control to Python, returning the cause to be the instruction name. The user's script must then interpret the reason for exiting the simulation loop and handle the action accordingly. This may change in the future.
src/sim/pseudo_inst.cc:
Exit sim loop with a specific string to indicate to Python what caused the exit. The user's script needs to interpret the exit events and handle them as desired.
--HG--
extra : convert_revision :
8eb4a42285dacb3ada3a791173c605b5acb78598
Kevin Lim [Thu, 6 Jul 2006 01:14:36 +0000 (21:14 -0400)]
Remove sampler and serializer. Now they are handled through C++ interacting with Python.
src/SConscript:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/sim/pseudo_inst.cc:
Remove sampler.
src/sim/sim_object.cc:
Remove serializer.
--HG--
extra : convert_revision :
ce7616189440f3dc70040148da6d07309a386008
Kevin Lim [Wed, 5 Jul 2006 21:59:33 +0000 (17:59 -0400)]
Rename quiesce to drain to avoid confusion with the pseudo instruction.
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/python/m5/__init__.py:
src/python/m5/config.py:
src/sim/main.cc:
src/sim/sim_events.cc:
src/sim/sim_events.hh:
src/sim/sim_object.cc:
src/sim/sim_object.hh:
Rename quiesce to drain.
--HG--
extra : convert_revision :
fc3244a3934812e1edb8050f1f51f30382baf774
Kevin Lim [Wed, 5 Jul 2006 21:25:37 +0000 (17:25 -0400)]
Checker ignores any faults that occur in syscall emulation mode for now.
src/cpu/checker/cpu_impl.hh:
The only fault we handle in SE causes troubles when invoked with the Checker. This is because it changes state within the process, and not the checker, so the state isn't correct when the main CPU calls invoke. It's safe to just ignore the fault in the Checker and continue.
--HG--
extra : convert_revision :
5000d763a75009c7a6011646a6790ac5b23df6bb
Kevin Lim [Wed, 5 Jul 2006 20:54:24 +0000 (16:54 -0400)]
Fix up some merge problems.
src/base/traceflags.py:
Remove BaseCPU traceflag.
src/cpu/o3/alpha/params.hh:
Move non-Alpha specific parameters out of this params class.
src/cpu/o3/params.hh:
Move non-Alpha specific params into this params class.
--HG--
extra : convert_revision :
e5b652adb47a240376733400e6054c66c50bd514
Kevin Lim [Wed, 5 Jul 2006 20:08:18 +0000 (16:08 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
src/base/traceflags.py:
src/cpu/SConscript:
Hand merge.
src/cpu/o3/alpha/params.hh:
Hand merge. This needs to get changed.
--HG--
rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh
rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py
extra : convert_revision :
581f338f5bce35288f7d15d95cbd0ac3a9135e6a
Kevin Lim [Wed, 5 Jul 2006 20:01:38 +0000 (16:01 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
--HG--
extra : convert_revision :
f5b6daa2d512f38153246fc9a39cc6560d939ebc
Kevin Lim [Wed, 5 Jul 2006 19:57:02 +0000 (15:57 -0400)]
Need to change state upon quiescing.
--HG--
extra : convert_revision :
25e3b0a463a0191cab9290665409d0abca6a179a
Kevin Lim [Wed, 5 Jul 2006 19:55:45 +0000 (15:55 -0400)]
Alphabetize traceflags, rename FullCPUAll flag to O3CPUAll.
--HG--
extra : convert_revision :
f558966154376223674c82d513afc2dad6591426
Kevin Lim [Wed, 5 Jul 2006 19:53:22 +0000 (15:53 -0400)]
Split off files that are shared across the O3 and Ozone models.
--HG--
extra : convert_revision :
023e84660d5cee5162d39548f87e5ca8ec68115f
Kevin Lim [Wed, 5 Jul 2006 19:51:36 +0000 (15:51 -0400)]
Add some different parameters. The main change is that the writeback count is now limited so that it doesn't overflow the buffer.
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_params.hh:
Add in dispatchWidth, wbWidth, wbDepth parameters. wbDepth is the number of cycles of wbWidth instructions that can be buffered.
src/cpu/o3/iew.hh:
Include separate parameter for dispatch width.
Also limit the number of outstanding writebacks so the writeback buffer isn't overflowed. The IQ must make sure with the IEW stage that it can issue instructions prior to issuing.
src/cpu/o3/iew_impl.hh:
Include separate parameter for dispatch width.
Also limit the number of outstanding writebacks so the writeback buffer isn't overflowed.
src/cpu/o3/inst_queue_impl.hh:
IQ needs to check with the IEW to make sure it can issue instructions, and increments the IEW wb counter each time there is an outstanding instruction that will writeback.
src/cpu/o3/lsq_unit_impl.hh:
Be sure to decrement the writeback counter if there's a squashed load that returned.
src/python/m5/objects/AlphaO3CPU.py:
Change the parameters to include dispatch width, writeback width, and writeback depth.
--HG--
extra : convert_revision :
31c8cc495273e3c481b79055562fc40f71291fc4
Ron Dreslinski [Wed, 5 Jul 2006 19:13:27 +0000 (15:13 -0400)]
Fix some unset values in the request in the timing CPU.
Properly implement the MSHR allocate function.
src/cpu/simple/timing.cc:
Set the thread context in the CPU.
Need to do this properly, currently I just set it to Cpu=0 Thread=0. This will just cause all the stats in the cache based on these to just yield totals and not a distribution.
src/mem/cache/miss/mshr.cc:
Properly implement the allocate function for the MSHR.
--HG--
extra : convert_revision :
bcece518e54ed1404db3196f996a77b4dd5c1c1e
Kevin Lim [Wed, 5 Jul 2006 17:22:46 +0000 (13:22 -0400)]
Merge ktlim@zamp:/z/ktlim2/clean/newmem-merge
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
--HG--
extra : convert_revision :
20e45bec8c3911a6389a89e2d193aa1de867c89e
Korey Sewell [Mon, 3 Jul 2006 16:19:35 +0000 (12:19 -0400)]
Fix for FS O3CPU compile ... missing forward class declaration/header file after files got split for ISA-independence
src/cpu/o3/alpha/thread_context.hh:
Use 'this' when accessing cpu
src/cpu/o3/cpu.hh:
add numActiveThreds function
src/cpu/o3/thread_context.hh:
forward class declarations
src/cpu/o3/thread_context_impl.hh:
add quiesce event header file
src/cpu/thread_context.hh:
add exit() function to thread context (read comments in file)
src/sim/syscall_emul.cc:
adjust exitFunc syscall
--HG--
extra : convert_revision :
323dc871e2b4f4ee5036be388ceb6634cd85a83e
Korey Sewell [Mon, 3 Jul 2006 05:10:19 +0000 (01:10 -0400)]
Added hook to check for SMT workloads. SMT is identified by adding a semicolon between
the workloads.
Now SMT on the O3CPU can be invoked by "/ALPHA_SE/m5.debug ../configs/test/test.py -d --cmd="hello;hello" -i="file1;file2"
I think I am a novice python magician now!!!!....
configs/test/test.py:
Added hook to check for SMT workloads. SMT is identified by adding a semicolon between
the workloads.
Now SMT on the O3CPU can be invoked by "/ALPHA_SE/m5.debug ../configs/test/test.py -d --cmd="hello;hello" --input="file1;file2"
(btw, We are back to working for this double hello world case)
I am a novice python magician now!!!!....
--HG--
extra : convert_revision :
b55e10dce33f5a9dc4c78f90409ec0912bad4292
Korey Sewell [Mon, 3 Jul 2006 03:27:13 +0000 (23:27 -0400)]
typo ... change 'single_thread' to 'round_robin_policy'
--HG--
extra : convert_revision :
a4a5cb90557f786d42c6178bc6e268312c5ecbee
Korey Sewell [Mon, 3 Jul 2006 03:11:24 +0000 (23:11 -0400)]
Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads)
Edit Test3 for newmem
src/base/traceflags.py:
Add O3CPU flag
src/cpu/base.cc:
for some reason adding a BaseCPU flag doesnt work so just go back to old way...
src/cpu/o3/alpha/cpu_builder.cc:
Determine number threads by workload size instead of solely by parameter.
Default SMT fetch policy to RoundRobin if it's not specified in Config file
src/cpu/o3/commit.hh:
only use nextNPC for !ALPHA
src/cpu/o3/commit_impl.hh:
add FetchTrapPending as condition for commit
src/cpu/o3/cpu.cc:
panic if active threads is more than Impl::MaxThreads
src/cpu/o3/fetch.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
name stuff
src/cpu/o3/fetch_impl.hh:
fatal if try to use SMT branch count, that's unimplemented right now
src/python/m5/config.py:
make it clearer that a parameter is not valid within a configuration class
--HG--
extra : convert_revision :
55069847304e40e257f9225f0dc3894ce6491b34
Korey Sewell [Sat, 1 Jul 2006 23:02:43 +0000 (19:02 -0400)]
traceflag stuff
src/base/traceflags.py:
add BaseCPU flag, O3CPUAll flag grouping
src/cpu/base.cc:
Use BaseCPU flag instead of FullCPU flag
--HG--
extra : convert_revision :
32f737a2f58eb936634799f1f809e07cbba90179
Korey Sewell [Sat, 1 Jul 2006 22:52:02 +0000 (18:52 -0400)]
fix cpu builder to build the correct name...
add activateThread event and functions
src/cpu/o3/alpha/cpu_builder.cc:
Have CPU builder build a DerivO3CPU not a DerivAlphaO3CPU
src/cpu/o3/cpu.cc:
add activateThread Event
add activateThread function
adjust activateContext to schedule a thread to activate within the
CPU instead of activating thread right away. This will lead to stages
trying to use threads that arent ready yet and wasting execution time & possibly
performance.
src/cpu/o3/cpu.hh:
add activateThread Event
add activateThread function
add schedule/descheculed activate thread event
--HG--
extra : convert_revision :
236d30dc160910507ad36f7f527ab185ed38dc04
Korey Sewell [Sat, 1 Jul 2006 00:51:07 +0000 (20:51 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision :
3c1405d8b4831c6240e02ba65a72043ca55f4a46
Korey Sewell [Sat, 1 Jul 2006 00:49:31 +0000 (20:49 -0400)]
now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
src/cpu/o3/alpha/cpu.cc:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/impl.hh:
filenames
src/cpu/o3/alpha/thread_context.hh:
public
src/cpu/o3/base_dyn_inst.cc:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/commit.cc:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode.cc:
src/cpu/o3/fetch.cc:
src/cpu/o3/iew.cc:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/lsq.cc:
src/cpu/o3/lsq_unit.cc:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/rename.cc:
src/cpu/o3/rob.cc:
use O3CPUImpl ... not Alpha
src/cpu/o3/checker_builder.cc:
filename
--HG--
extra : convert_revision :
6eb739909699ade1e2a9d63637b182413ceebc69
Korey Sewell [Fri, 30 Jun 2006 23:52:08 +0000 (19:52 -0400)]
Make O3CPU model independent of the ISA
Use O3CPU when building instead of AlphaO3CPU.
I could use some better python magic in the cpu_models.py file!
AUTHORS:
add middle initial
SConstruct:
change from AlphaO3CPU to O3CPU
src/cpu/SConscript:
edits to build O3CPU instead of AlphaO3CPU
src/cpu/cpu_models.py:
change substitution template to use proper CPU EXEC CONTEXT For O3CPU Model...
Actually, some Python expertise could be used here. The 'env' variable is not
passed to this file, so I had to parse through the ARGV to find the ISA...
src/cpu/o3/base_dyn_inst.cc:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/commit.cc:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.cc:
src/cpu/o3/fetch.cc:
src/cpu/o3/iew.cc:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/lsq.cc:
src/cpu/o3/lsq_unit.cc:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/rename.cc:
src/cpu/o3/rob.cc:
use isa_specific.hh
src/sim/process.cc:
only initi NextNPC if not ALPHA
src/cpu/o3/alpha/cpu.cc:
alphao3cpu impl
src/cpu/o3/alpha/cpu.hh:
move AlphaTC to it's own file
src/cpu/o3/alpha/cpu_impl.hh:
Move AlphaTC to it's own file ...
src/cpu/o3/alpha/dyn_inst.cc:
src/cpu/o3/alpha/dyn_inst.hh:
src/cpu/o3/alpha/dyn_inst_impl.hh:
include paths
src/cpu/o3/alpha/impl.hh:
include paths, set default MaxThreads to 2 instead of 4
src/cpu/o3/alpha/params.hh:
set Alpha Specific Params here
src/python/m5/objects/O3CPU.py:
add O3CPU class
src/cpu/o3/SConscript:
include isa-specific build files
src/cpu/o3/alpha/thread_context.cc:
NEW HOME of AlphaTC
src/cpu/o3/alpha/thread_context.hh:
new home of AlphaTC
src/cpu/o3/isa_specific.hh:
includes ISA specific files
src/cpu/o3/params.hh:
base o3 params
src/cpu/o3/thread_context.hh:
base o3 thread context
src/cpu/o3/thread_context_impl.hh:
base o3 thead context impl
--HG--
rename : src/cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha/cpu.cc
rename : src/cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha/cpu.hh
rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : src/cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha/cpu_impl.hh
rename : src/cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha/dyn_inst.cc
rename : src/cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha/dyn_inst.hh
rename : src/cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha/dyn_inst_impl.hh
rename : src/cpu/o3/alpha_impl.hh => src/cpu/o3/alpha/impl.hh
rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh
rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py
extra : convert_revision :
d377d6417452ac337bc502f28b2fde907d6b340e
Ron Dreslinski [Fri, 30 Jun 2006 21:21:58 +0000 (17:21 -0400)]
AtomicSimpleCPU with a cache now runs the hello world! test program.
Need to clean up a bunch of flags/hacks in the code. Then onto Timming mode.
Functional accesses also work properly, although not exactly how we wanted them. I'll need to clean that up as well.
src/cpu/simple/atomic.cc:
Atomic CPU needs to set thread context so stats work in cache. Temporarily just use CPU=0 ThreadID=0
src/mem/cache/cache_impl.hh:
Need to return success/failure properly still
Physical memory object doesn't assert SATISFIED anymore, need to remove that flag
src/mem/cache/tags/lru.cc:
Doesn't work if the REQ doesn't set it's ASID. Temporary fix use 0 always
--HG--
extra : convert_revision :
d06a39684af593db699b64df9a29f80c61d8d050
Ron Dreslinski [Fri, 30 Jun 2006 20:25:35 +0000 (16:25 -0400)]
First pass, now compiles with current head of tree.
Compile and initialization work, still working on functionality.
src/mem/cache/base_cache.cc:
Temp fix for cpu's use of getPort functionality. CPU's will need to be ported to the new connector objects.
Also, all packets have to have data or the delete fails.
src/mem/cache/cache.hh:
Fix function prototypes so overloading works
src/mem/cache/cache_impl.hh:
fix functions to match virtual base class
src/mem/cache/miss/miss_queue.cc:
Packets havve to have data, or delete fails
src/python/m5/objects/BaseCache.py:
Update for newmem
--HG--
extra : convert_revision :
2b6ad1e9d8ae07ace9294cd257e2ccc0024b7fcb
Ron Dreslinski [Fri, 30 Jun 2006 15:34:27 +0000 (11:34 -0400)]
Fix the packet data allocation methods. Small fixes from changesets after my initial work.
This now compiles.
src/mem/cache/base_cache.cc:
Fix getPort function that changed
src/mem/cache/base_cache.hh:
Fix get port function, provide default implementations of virtual functions in the base class
src/mem/cache/cache.hh:
Fix virtual function declerations
src/mem/cache/cache_builder.cc:
Fix params
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
Properly allocate data in packet
--HG--
extra : convert_revision :
dedf8b0f76ab90b06b60f8fe079c0ae361f91a48
Ron Dreslinski [Fri, 30 Jun 2006 14:25:50 +0000 (10:25 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmem
--HG--
extra : convert_revision :
6eefb4a3ee472f2f2c86ed823c70fc9e5625818f
Ron Dreslinski [Fri, 30 Jun 2006 14:25:25 +0000 (10:25 -0400)]
All files compile in the mem directory except cache_builder
Missing some functionality (like split caches and copy support)
src/SConscript:
Typo
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/ghb_prefetcher.hh:
src/mem/cache/prefetch/stride_prefetcher.hh:
src/mem/cache/prefetch/tagged_prefetcher_impl.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
src/mem/packet.hh:
src/mem/request.hh:
Fix so it compiles
--HG--
extra : convert_revision :
0d87d84f6e9445bab655c0cb0f8541bbf6eab904
Kevin Lim [Fri, 30 Jun 2006 01:38:16 +0000 (21:38 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
0756f7f1f63fae472e0ef1d20e9eb38e56de78c8
Kevin Lim [Fri, 30 Jun 2006 01:34:01 +0000 (21:34 -0400)]
Remove function that no longer can be used. We should figure out if we want to allow the m5checkpoint pseudoinstruction or not.
src/sim/pseudo_inst.cc:
Remove the setup function from Checkpoint. I'm not sure what we want to do with this pseudoinst.
src/sim/serialize.hh:
Remove setup function.
--HG--
extra : convert_revision :
5ff494d816e2d8a7fe65a3d13037608003388d8f