Eddie Hung [Tue, 25 Jun 2019 01:33:06 +0000 (18:33 -0700)]
Walk through as many muxes as exist for rd_en
Eddie Hung [Tue, 25 Jun 2019 01:32:58 +0000 (18:32 -0700)]
Add test
Eddie Hung [Sat, 22 Jun 2019 03:30:24 +0000 (20:30 -0700)]
Add 'muxcover -dmux=<cost>' and '-nopartial' to CHANGELOG
Eddie Hung [Sat, 22 Jun 2019 00:13:41 +0000 (17:13 -0700)]
Merge pull request #1108 from YosysHQ/clifford/fix1091
Add support for partial matches to muxcover
Clifford Wolf [Fri, 21 Jun 2019 17:25:35 +0000 (19:25 +0200)]
Merge pull request #1123 from mmicko/fix_typo
Fix json frontend loading upto
Clifford Wolf [Fri, 21 Jun 2019 17:24:41 +0000 (19:24 +0200)]
Replace "muxcover -freedecode" with "muxcover -dmux=cost"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Miodrag Milanovic [Fri, 21 Jun 2019 17:09:34 +0000 (19:09 +0200)]
Fix typo
Eddie Hung [Fri, 21 Jun 2019 15:56:56 +0000 (08:56 -0700)]
Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
Improve shregmap to handle case where first flop is common to two chains
Clifford Wolf [Fri, 21 Jun 2019 14:58:12 +0000 (16:58 +0200)]
Merge pull request #1122 from YosysHQ/clifford/jsonports
Added JSON upto and offset
Clifford Wolf [Fri, 21 Jun 2019 13:22:17 +0000 (15:22 +0200)]
Added JSON upto and offset
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 21 Jun 2019 13:07:39 +0000 (15:07 +0200)]
Merge pull request #1121 from YosysHQ/ecp5-ccu2c-inv
ecp5: Improve mapping of $alu when BI is used
David Shah [Fri, 21 Jun 2019 08:44:13 +0000 (09:44 +0100)]
ecp5: Improve mapping of $alu when BI is used
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Fri, 21 Jun 2019 08:13:51 +0000 (10:13 +0200)]
Merge pull request #1117 from bwidawsk/more-home
Add a few more filename rewrites
Clifford Wolf [Fri, 21 Jun 2019 08:13:13 +0000 (10:13 +0200)]
Merge pull request #1119 from YosysHQ/eddie/fix1118
Make genvar a signed type
Clifford Wolf [Fri, 21 Jun 2019 08:12:32 +0000 (10:12 +0200)]
Merge pull request #1116 from YosysHQ/eddie/fix1115
Sign extend unsized 'bx and 'bz values
Clifford Wolf [Fri, 21 Jun 2019 08:02:10 +0000 (10:02 +0200)]
Add "muxcover -freedecode"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Fri, 21 Jun 2019 04:56:02 +0000 (21:56 -0700)]
Fix gcc invalidation behaviour for write_aiger
Clifford Wolf [Thu, 20 Jun 2019 09:30:27 +0000 (11:30 +0200)]
Improvements in muxcover
- Slightly under-estimate cost of decoder muxes
- Prefer larger muxes at tree root at same cost
- Don't double-count input cost for partial muxes
- Add debug log output
Eddie Hung [Wed, 19 Jun 2019 17:15:41 +0000 (10:15 -0700)]
Missing a `clean` and `opt_expr -mux_bool` in test
Eddie Hung [Wed, 19 Jun 2019 17:07:34 +0000 (10:07 -0700)]
Add test
Clifford Wolf [Wed, 19 Jun 2019 11:15:54 +0000 (13:15 +0200)]
Add support for partial matches to muxcover, fixes #1091
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Fri, 21 Jun 2019 00:03:05 +0000 (17:03 -0700)]
Actually, there might not be any harm in updating sigmap...
Eddie Hung [Thu, 20 Jun 2019 23:57:54 +0000 (16:57 -0700)]
Add comment as per @cliffordwolf
Eddie Hung [Thu, 20 Jun 2019 23:07:22 +0000 (16:07 -0700)]
Add test
Eddie Hung [Thu, 20 Jun 2019 23:04:12 +0000 (16:04 -0700)]
Make genvar a signed type
Eddie Hung [Thu, 20 Jun 2019 19:45:40 +0000 (12:45 -0700)]
Add CHANGELOG entry
Eddie Hung [Thu, 20 Jun 2019 19:43:59 +0000 (12:43 -0700)]
Extend sign extension tests
Eddie Hung [Thu, 20 Jun 2019 19:43:39 +0000 (12:43 -0700)]
Maintain "is_unsized" state of constants
Eddie Hung [Thu, 20 Jun 2019 19:40:05 +0000 (12:40 -0700)]
Revert "Fix sign extension when sign is 1'bx"
This reverts commit
0221f3e1c5b427678c5679027ee47ec7c0b8321d.
Ben Widawsky [Thu, 20 Jun 2019 17:27:59 +0000 (10:27 -0700)]
Add a few more filename rewrites
This now allows a full pipeline to work, something such as:
yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v"
Otherwise, you will get something along the lines of:
ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Eddie Hung [Thu, 20 Jun 2019 17:15:04 +0000 (10:15 -0700)]
Remove leftover comment
Eddie Hung [Thu, 20 Jun 2019 17:10:43 +0000 (10:10 -0700)]
Add test
Eddie Hung [Thu, 20 Jun 2019 17:04:42 +0000 (10:04 -0700)]
Fix sign extension when sign is 1'bx
Clifford Wolf [Thu, 20 Jun 2019 13:34:52 +0000 (15:34 +0200)]
Fix typo, fixes #1095
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 20 Jun 2019 13:23:55 +0000 (15:23 +0200)]
Improve shregmap help message, fixes #1113
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 20 Jun 2019 12:27:57 +0000 (14:27 +0200)]
Update some .gitignore files
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 20 Jun 2019 10:23:07 +0000 (12:23 +0200)]
Fix typo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 20 Jun 2019 10:06:58 +0000 (12:06 +0200)]
Merge branch 'towoe-unpacked_arrays'
Clifford Wolf [Thu, 20 Jun 2019 10:06:07 +0000 (12:06 +0200)]
Add proper test for SV-style arrays
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 20 Jun 2019 10:03:00 +0000 (12:03 +0200)]
Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays
Eddie Hung [Wed, 19 Jun 2019 22:30:50 +0000 (15:30 -0700)]
Merge pull request #1111 from acw1251/help_summary_fixes
Fixed the help summary line for a few commands
acw1251 [Wed, 19 Jun 2019 20:39:46 +0000 (16:39 -0400)]
Fixed small typo in ice40_unlut help summary
acw1251 [Wed, 19 Jun 2019 19:27:04 +0000 (15:27 -0400)]
Fixed the help summary line for a few commands
Eddie Hung [Wed, 19 Jun 2019 16:51:11 +0000 (09:51 -0700)]
Fix bug in #1078, add entry to CHANGELOG
Clifford Wolf [Wed, 19 Jun 2019 15:25:39 +0000 (17:25 +0200)]
Merge pull request #1109 from YosysHQ/clifford/fix1106
Add "read_verilog -pwires" feature
Clifford Wolf [Wed, 19 Jun 2019 12:38:50 +0000 (14:38 +0200)]
Add "read_verilog -pwires" feature, closes #1106
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 19 Jun 2019 11:53:07 +0000 (13:53 +0200)]
Merge pull request #1105 from YosysHQ/clifford/fixlogicinit
Improve handling of initial/default values
Tobias Wölfel [Wed, 19 Jun 2019 10:47:48 +0000 (12:47 +0200)]
Unpacked array declaration using size
Allows fixed-sized array dimension specified by a single number.
This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560.
But is split out of the original work.
Clifford Wolf [Wed, 19 Jun 2019 10:20:35 +0000 (12:20 +0200)]
Make tests/aiger less chatty
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 19 Jun 2019 10:12:08 +0000 (12:12 +0200)]
Add defvalue test, minor autotest fixes for .sv files
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 19 Jun 2019 09:49:20 +0000 (11:49 +0200)]
Use input default values in hierarchy pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 19 Jun 2019 09:37:11 +0000 (11:37 +0200)]
Add defaultvalue attribute
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 19 Jun 2019 09:25:11 +0000 (11:25 +0200)]
Fix handling of "logic" variables with initial value
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 19 Jun 2019 08:52:59 +0000 (10:52 +0200)]
Merge pull request #1100 from bwidawsk/home
Support ~ in filename parsing
Clifford Wolf [Wed, 19 Jun 2019 08:50:32 +0000 (10:50 +0200)]
Merge pull request #1104 from whitequark/case-semantics
Clarify switch/case semantics in RTLIL
whitequark [Wed, 19 Jun 2019 05:22:40 +0000 (05:22 +0000)]
Explain exact semantics of switch and case rules in the manual.
whitequark [Wed, 19 Jun 2019 05:22:13 +0000 (05:22 +0000)]
In RTLIL::Module::check(), check process invariants.
Ben Widawsky [Mon, 17 Jun 2019 21:45:48 +0000 (14:45 -0700)]
Support filename rewrite in backends
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Ben Widawsky [Mon, 17 Jun 2019 21:45:11 +0000 (14:45 -0700)]
Support ~ for home directory
This is tested on Linux only
v2:
Wrap functioanlity in ifndef _WIN32 (eddiehung)
Find '~/' instead of '~' (cliffordwolf)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Clifford Wolf [Tue, 18 Jun 2019 14:52:08 +0000 (16:52 +0200)]
Merge pull request #1086 from udif/pr_elab_sys_tasks2
Fixed broken $error()/$info/$warning() on non-generate blocks (within always/initial blocks)
Clifford Wolf [Sun, 16 Jun 2019 21:12:03 +0000 (23:12 +0200)]
Add timescale and generated-by header to yosys-smtbmc MkVcd
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Serge Bazanski [Thu, 13 Jun 2019 10:14:37 +0000 (12:14 +0200)]
Merge pull request #829 from abdelrahmanhosny/master
Dockerfile for Yosys
Eddie Hung [Wed, 12 Jun 2019 15:34:06 +0000 (08:34 -0700)]
Add shregmap -tech xilinx test
Eddie Hung [Tue, 11 Jun 2019 23:05:42 +0000 (16:05 -0700)]
Revert "Try way that doesn't involve creating a new wire"
This reverts commit
2f427acc9ed23c77e89386f4fbf53ac580bf0f0b.
Eddie Hung [Tue, 11 Jun 2019 22:48:20 +0000 (15:48 -0700)]
Try way that doesn't involve creating a new wire
Udi Finkelstein [Mon, 10 Jun 2019 23:52:06 +0000 (02:52 +0300)]
Fixed brojen $error()/$info/$warning() on non-generate blocks
(within always/initial blocks)
Eddie Hung [Mon, 10 Jun 2019 23:16:40 +0000 (16:16 -0700)]
If d_bit already in sigbit_chain_next, create extra wire
Eddie Hung [Mon, 10 Jun 2019 23:16:26 +0000 (16:16 -0700)]
Add test
Eddie Hung [Mon, 10 Jun 2019 17:27:55 +0000 (10:27 -0700)]
Add some more comments
David Shah [Mon, 10 Jun 2019 14:12:23 +0000 (15:12 +0100)]
Merge pull request #1082 from corecode/u4k
ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k
Simon Schubert [Mon, 10 Jun 2019 09:49:08 +0000 (11:49 +0200)]
ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k
Clifford Wolf [Sat, 8 Jun 2019 09:31:19 +0000 (11:31 +0200)]
Merge pull request #1078 from YosysHQ/eddie/muxcover_costs
Allow muxcover costs to be changed
Eddie Hung [Fri, 7 Jun 2019 22:44:57 +0000 (15:44 -0700)]
Fix spacing from spaces to tabs
Clifford Wolf [Fri, 7 Jun 2019 21:13:34 +0000 (23:13 +0200)]
Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger
Fix read_aiger to really get tested, and fix some uncovered read_aiger issues
Eddie Hung [Fri, 7 Jun 2019 20:12:48 +0000 (13:12 -0700)]
Add read_aiger to CHANGELOG
Eddie Hung [Fri, 7 Jun 2019 18:30:36 +0000 (11:30 -0700)]
Fix spacing (entire file is wrong anyway, will fix later)
Eddie Hung [Fri, 7 Jun 2019 18:28:25 +0000 (11:28 -0700)]
Remove unnecessary std::getline() for ASCII
Eddie Hung [Fri, 7 Jun 2019 18:28:05 +0000 (11:28 -0700)]
Test *.aag too, by using *.aig as reference
Eddie Hung [Fri, 7 Jun 2019 18:07:15 +0000 (11:07 -0700)]
Fix read_aiger -- create zero driver, fix init width, parse 'b'
Eddie Hung [Fri, 7 Jun 2019 18:06:57 +0000 (11:06 -0700)]
Use ABC to convert from AIGER to Verilog
Eddie Hung [Fri, 7 Jun 2019 18:05:36 +0000 (11:05 -0700)]
Use ABC to convert AIGER to Verilog, then sat against Yosys
Eddie Hung [Fri, 7 Jun 2019 18:05:25 +0000 (11:05 -0700)]
Add symbols to AIGER test inputs for ABC
Eddie Hung [Fri, 7 Jun 2019 15:30:39 +0000 (08:30 -0700)]
Allow muxcover costs to be changed
Clifford Wolf [Fri, 7 Jun 2019 11:39:46 +0000 (13:39 +0200)]
Merge pull request #1077 from YosysHQ/clifford/pr983
elaboration system tasks
Clifford Wolf [Fri, 7 Jun 2019 11:12:25 +0000 (13:12 +0200)]
Rename implicit_ports.sv test to implicit_ports.v
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 7 Jun 2019 10:41:09 +0000 (12:41 +0200)]
Fixes and cleanups in AST_TECALL handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 7 Jun 2019 10:08:42 +0000 (12:08 +0200)]
Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983
Clifford Wolf [Fri, 7 Jun 2019 09:53:46 +0000 (11:53 +0200)]
Merge branch 'tux3-implicit_named_connection'
Clifford Wolf [Fri, 7 Jun 2019 09:48:33 +0000 (11:48 +0200)]
Merge pull request #1076 from thasti/centos7-build-fix
Fix pyosys-build on CentOS7
Clifford Wolf [Fri, 7 Jun 2019 09:46:16 +0000 (11:46 +0200)]
Cleanup tux3-implicit_named_connection
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 7 Jun 2019 09:41:54 +0000 (11:41 +0200)]
Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection
Stefan Biereigel [Fri, 7 Jun 2019 07:47:33 +0000 (09:47 +0200)]
remove boost/log/exceptions.hpp from wrapper generator
tux3 [Tue, 4 Jun 2019 22:47:54 +0000 (00:47 +0200)]
SystemVerilog support for implicit named port connections
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
Clifford Wolf [Thu, 6 Jun 2019 10:34:05 +0000 (12:34 +0200)]
Merge pull request #1060 from antmicro/parsing_attr_on_port_conn
Added support for parsing attributes on port connections.
David Shah [Thu, 6 Jun 2019 10:22:49 +0000 (11:22 +0100)]
Merge pull request #1073 from whitequark/ecp5-diamond-iob
ECP5: implement most Diamond I/O buffer primitives
whitequark [Thu, 6 Jun 2019 10:03:03 +0000 (10:03 +0000)]
ECP5: implement all Diamond I/O buffer primitives.
Clifford Wolf [Thu, 6 Jun 2019 04:50:12 +0000 (06:50 +0200)]
Merge pull request #1071 from YosysHQ/eddie/fix_1070
Fix typo in opt_rmdff causing register to be incorrectly removed
Clifford Wolf [Thu, 6 Jun 2019 04:49:07 +0000 (06:49 +0200)]
Merge pull request #1072 from YosysHQ/eddie/fix_1069
Error out if no top module given before 'sim'
Eddie Hung [Wed, 5 Jun 2019 21:21:44 +0000 (14:21 -0700)]
Missing doc for -tech xilinx in shregmap
Eddie Hung [Wed, 5 Jun 2019 21:16:24 +0000 (14:16 -0700)]
Error out if no top module given before 'sim'