Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 15:28:43 +0000 (16:28 +0100)]
Re: [libre-riscv-dev] memory interface diagram woes
Jacob Lifshay [Tue, 28 Apr 2020 15:10:57 +0000 (08:10 -0700)]
Re: [libre-riscv-dev] circuitjs
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 15:03:07 +0000 (16:03 +0100)]
Re: [libre-riscv-dev] circuitjs
bugzilla-daemon [Tue, 28 Apr 2020 14:56:28 +0000 (14:56 +0000)]
[libre-riscv-dev] [Bug 293] evaluate an online circuit-editor (with simulator preferably)
Jacob Lifshay [Tue, 28 Apr 2020 14:53:54 +0000 (07:53 -0700)]
[libre-riscv-dev] circuitjs
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 14:43:29 +0000 (15:43 +0100)]
Re: [libre-riscv-dev] memory interface diagram woes
Jacob Lifshay [Tue, 28 Apr 2020 14:38:15 +0000 (07:38 -0700)]
Re: [libre-riscv-dev] memory interface diagram woes
bugzilla-daemon [Tue, 28 Apr 2020 14:27:42 +0000 (14:27 +0000)]
[libre-riscv-dev] [Bug 293] New: evaluate an online circuit-editor (with simulator preferably)
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 14:26:29 +0000 (15:26 +0100)]
Re: [libre-riscv-dev] memory interface diagram woes
whygee [Tue, 28 Apr 2020 13:33:23 +0000 (15:33 +0200)]
Re: [libre-riscv-dev] memory interface diagram woes
bugzilla-daemon [Mon, 27 Apr 2020 20:44:55 +0000 (20:44 +0000)]
[libre-riscv-dev] [Bug 165] Formally verify the FPCMP (FEQ, FLE, FLT) module
bugzilla-daemon [Mon, 27 Apr 2020 20:29:51 +0000 (20:29 +0000)]
[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B
bugzilla-daemon [Mon, 27 Apr 2020 20:45:09 +0000 (20:45 +0000)]
[libre-riscv-dev] [Bug 196] Formal correctness proof needed for the IEEE754 FPU
bugzilla-daemon [Mon, 27 Apr 2020 20:45:08 +0000 (20:45 +0000)]
[libre-riscv-dev] [Bug 163] Formally Verify the FPMAX module
bugzilla-daemon [Mon, 27 Apr 2020 20:44:56 +0000 (20:44 +0000)]
[libre-riscv-dev] [Bug 196] Formal correctness proof needed for the IEEE754 FPU
bugzilla-daemon [Mon, 27 Apr 2020 20:43:56 +0000 (20:43 +0000)]
[libre-riscv-dev] [Bug 196] Formal correctness proof needed for the IEEE754 FPU
bugzilla-daemon [Mon, 27 Apr 2020 20:43:23 +0000 (20:43 +0000)]
[libre-riscv-dev] [Bug 163] Formally Verify the FPMAX module
bugzilla-daemon [Mon, 27 Apr 2020 20:43:11 +0000 (20:43 +0000)]
[libre-riscv-dev] [Bug 165] Formally verify the FPCMP (FEQ, FLE, FLT) module
bugzilla-daemon [Mon, 27 Apr 2020 20:41:57 +0000 (20:41 +0000)]
[libre-riscv-dev] [Bug 162] Formally Verify the FSGNJ module
bugzilla-daemon [Mon, 27 Apr 2020 20:38:34 +0000 (20:38 +0000)]
[libre-riscv-dev] [Bug 211] formal proof of PowerDecoder stage2 needed
bugzilla-daemon [Mon, 27 Apr 2020 20:38:26 +0000 (20:38 +0000)]
[libre-riscv-dev] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC
bugzilla-daemon [Mon, 27 Apr 2020 20:29:51 +0000 (20:29 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
bugzilla-daemon [Mon, 27 Apr 2020 20:28:06 +0000 (20:28 +0000)]
[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B
bugzilla-daemon [Mon, 27 Apr 2020 20:27:49 +0000 (20:27 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
bugzilla-daemon [Mon, 27 Apr 2020 20:26:50 +0000 (20:26 +0000)]
[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B
bugzilla-daemon [Mon, 27 Apr 2020 20:25:12 +0000 (20:25 +0000)]
[libre-riscv-dev] [Bug 272] functions needed in POWER simulator which match 3.0B spec
bugzilla-daemon [Mon, 27 Apr 2020 20:23:05 +0000 (20:23 +0000)]
[libre-riscv-dev] [Bug 189] Create partitioned right shift using the existing partitioned left shift
bugzilla-daemon [Mon, 27 Apr 2020 20:22:52 +0000 (20:22 +0000)]
[libre-riscv-dev] [Bug 171] partitioned comparison operators
bugzilla-daemon [Mon, 27 Apr 2020 20:22:40 +0000 (20:22 +0000)]
[libre-riscv-dev] [Bug 172] partitioned signal add/sub/neg
bugzilla-daemon [Mon, 27 Apr 2020 20:18:38 +0000 (20:18 +0000)]
[libre-riscv-dev] [Bug 173] dynamic partitioned "shift"
bugzilla-daemon [Mon, 27 Apr 2020 20:18:21 +0000 (20:18 +0000)]
[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning
Luke Kenneth Casson Leighton [Mon, 27 Apr 2020 12:38:26 +0000 (13:38 +0100)]
Re: [libre-riscv-dev] memory interface diagram woes
bugzilla-daemon [Mon, 27 Apr 2020 11:56:51 +0000 (11:56 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Luke Kenneth Casson Leighton [Mon, 27 Apr 2020 10:25:57 +0000 (11:25 +0100)]
Re: [libre-riscv-dev] memory interface diagram woes
Luke Kenneth Casson Leighton [Mon, 27 Apr 2020 10:07:45 +0000 (11:07 +0100)]
Re: [libre-riscv-dev] memory interface diagram woes
Jacob Lifshay [Mon, 27 Apr 2020 06:06:10 +0000 (23:06 -0700)]
Re: [libre-riscv-dev] memory interface diagram woes
Luke Kenneth Casson Leighton [Sun, 26 Apr 2020 12:27:12 +0000 (13:27 +0100)]
Re: [libre-riscv-dev] memory interface diagram woes
bugzilla-daemon [Sun, 26 Apr 2020 11:28:04 +0000 (11:28 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Sat, 25 Apr 2020 12:40:46 +0000 (12:40 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Luke Kenneth Casson Leighton [Fri, 24 Apr 2020 20:11:27 +0000 (21:11 +0100)]
Re: [libre-riscv-dev] morphing 6600 code to use power decoder
bugzilla-daemon [Fri, 24 Apr 2020 14:39:12 +0000 (14:39 +0000)]
[libre-riscv-dev] [Bug 292] implement multi-way read/write 6600 signals
bugzilla-daemon [Fri, 24 Apr 2020 14:38:39 +0000 (14:38 +0000)]
[libre-riscv-dev] [Bug 292] implement multi-way read/write 6600 signals
bugzilla-daemon [Fri, 24 Apr 2020 14:38:08 +0000 (14:38 +0000)]
[libre-riscv-dev] [Bug 81] implement 6600-style "precise" out-of-order scoreboard
bugzilla-daemon [Fri, 24 Apr 2020 14:37:59 +0000 (14:37 +0000)]
[libre-riscv-dev] [Bug 292] implement multi-way read/write 6600 signals
bugzilla-daemon [Fri, 24 Apr 2020 14:36:43 +0000 (14:36 +0000)]
[libre-riscv-dev] [Bug 292] New: implement multi-way read/write 6600 signals
Luke Kenneth Casson Leighton [Thu, 23 Apr 2020 17:16:16 +0000 (18:16 +0100)]
Re: [libre-riscv-dev] morphing 6600 code to use power decoder
Luke Kenneth Casson Leighton [Thu, 23 Apr 2020 17:04:39 +0000 (18:04 +0100)]
[libre-riscv-dev] scammers looking for access to NLNet Funds
Luke Kenneth Casson Leighton [Thu, 23 Apr 2020 14:37:32 +0000 (15:37 +0100)]
Re: [libre-riscv-dev] memory interface diagram woes
Luke Kenneth Casson Leighton [Thu, 23 Apr 2020 10:29:22 +0000 (11:29 +0100)]
Re: [libre-riscv-dev] memory interface diagram woes
Luke Kenneth Casson Leighton [Thu, 23 Apr 2020 09:02:18 +0000 (10:02 +0100)]
Re: [libre-riscv-dev] memory interface diagram woes
Jacob Lifshay [Thu, 23 Apr 2020 06:49:25 +0000 (23:49 -0700)]
[libre-riscv-dev] memory interface diagram woes
bugzilla-daemon [Wed, 22 Apr 2020 19:42:49 +0000 (19:42 +0000)]
[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://powerprogress.org/en/
bugzilla-daemon [Wed, 22 Apr 2020 19:14:57 +0000 (19:14 +0000)]
[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://powerprogress.org/en/
bugzilla-daemon [Wed, 22 Apr 2020 19:00:24 +0000 (19:00 +0000)]
[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://powerprogress.org/en/
bugzilla-daemon [Wed, 22 Apr 2020 16:16:38 +0000 (16:16 +0000)]
[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://powerprogress.org/en/
bugzilla-daemon [Wed, 22 Apr 2020 16:00:39 +0000 (16:00 +0000)]
[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://powerprogress.org/en/
bugzilla-daemon [Wed, 22 Apr 2020 15:41:45 +0000 (15:41 +0000)]
[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://powerprogress.org/en/
bugzilla-daemon [Wed, 22 Apr 2020 13:38:01 +0000 (13:38 +0000)]
[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm
bugzilla-daemon [Wed, 22 Apr 2020 13:06:43 +0000 (13:06 +0000)]
[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm
bugzilla-daemon [Wed, 22 Apr 2020 12:49:43 +0000 (12:49 +0000)]
[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://powerprogress.org/en/
bugzilla-daemon [Wed, 22 Apr 2020 12:26:22 +0000 (12:26 +0000)]
[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://powerprogress.org/en/
bugzilla-daemon [Wed, 22 Apr 2020 12:17:07 +0000 (12:17 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Wed, 22 Apr 2020 10:53:04 +0000 (10:53 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Wed, 22 Apr 2020 09:48:47 +0000 (09:48 +0000)]
[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm
bugzilla-daemon [Wed, 22 Apr 2020 08:54:45 +0000 (08:54 +0000)]
[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm
bugzilla-daemon [Wed, 22 Apr 2020 08:39:55 +0000 (08:39 +0000)]
[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm
bugzilla-daemon [Wed, 22 Apr 2020 08:30:51 +0000 (08:30 +0000)]
[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm
bugzilla-daemon [Wed, 22 Apr 2020 02:58:07 +0000 (02:58 +0000)]
[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm
bugzilla-daemon [Tue, 21 Apr 2020 22:21:55 +0000 (22:21 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 21 Apr 2020 22:00:16 +0000 (22:00 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 21 Apr 2020 21:46:10 +0000 (21:46 +0000)]
[libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts
bugzilla-daemon [Tue, 21 Apr 2020 21:42:22 +0000 (21:42 +0000)]
[libre-riscv-dev] [Bug 291] New: HDL Workflow and Coriolis2 chroot automated setup scripts
Cole Poirier [Tue, 21 Apr 2020 21:35:09 +0000 (14:35 -0700)]
Re: [libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page
Luke Kenneth Casson Leighton [Tue, 21 Apr 2020 21:30:23 +0000 (22:30 +0100)]
Re: [libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page
bugzilla-daemon [Tue, 21 Apr 2020 21:28:58 +0000 (21:28 +0000)]
[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page
bugzilla-daemon [Tue, 21 Apr 2020 21:19:55 +0000 (21:19 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 21 Apr 2020 21:15:06 +0000 (21:15 +0000)]
[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page
bugzilla-daemon [Tue, 21 Apr 2020 21:09:22 +0000 (21:09 +0000)]
[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page
bugzilla-daemon [Tue, 21 Apr 2020 21:00:57 +0000 (21:00 +0000)]
[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page
bugzilla-daemon [Tue, 21 Apr 2020 20:43:43 +0000 (20:43 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 21 Apr 2020 20:23:01 +0000 (20:23 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 21 Apr 2020 19:24:56 +0000 (19:24 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 21 Apr 2020 18:05:38 +0000 (18:05 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 21 Apr 2020 17:40:47 +0000 (17:40 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 21 Apr 2020 17:03:08 +0000 (17:03 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 21 Apr 2020 16:55:11 +0000 (16:55 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
Luke Kenneth Casson Leighton [Tue, 21 Apr 2020 16:30:29 +0000 (17:30 +0100)]
Re: [libre-riscv-dev] Yosys cxxrtl
bugzilla-daemon [Tue, 21 Apr 2020 16:16:43 +0000 (16:16 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
Yehowshua Immanuel [Tue, 21 Apr 2020 16:02:49 +0000 (12:02 -0400)]
[libre-riscv-dev] Yosys cxxrtl
bugzilla-daemon [Tue, 21 Apr 2020 15:49:51 +0000 (15:49 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 21 Apr 2020 15:22:10 +0000 (15:22 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 21 Apr 2020 15:12:32 +0000 (15:12 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 21 Apr 2020 14:32:17 +0000 (14:32 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 21 Apr 2020 13:17:16 +0000 (13:17 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 21 Apr 2020 12:12:40 +0000 (12:12 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 21 Apr 2020 11:15:24 +0000 (11:15 +0000)]
[libre-riscv-dev] [Bug 290] import error caused by soc.decoder.isa.all no longer being generated
Jacob Lifshay [Tue, 21 Apr 2020 04:54:15 +0000 (21:54 -0700)]
Re: [libre-riscv-dev] [Bug 290] import error caused by soc.decoder.isa.all no longer being generated
bugzilla-daemon [Tue, 21 Apr 2020 04:48:03 +0000 (04:48 +0000)]
[libre-riscv-dev] [Bug 290] import error caused by soc.decoder.isa.all no longer being generated
bugzilla-daemon [Tue, 21 Apr 2020 04:28:42 +0000 (04:28 +0000)]
[libre-riscv-dev] [Bug 290] import error caused by soc.decoder.isa.all no longer being generated
bugzilla-daemon [Tue, 21 Apr 2020 04:01:00 +0000 (04:01 +0000)]
[libre-riscv-dev] [Bug 290] import error caused by soc.decoder.isa.all no longer being generated
projects / libre-riscv-dev.git / log