Enable X86_TUNE_AVX256_UNALIGNED_{LOAD，STORE}_OPTIMAL in generic tune.

gcc/ChangeLog:

PR target/98172
* config/i386/x86-tune.def (X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL):
Remove m_GENERIC from ~list.
(X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL): Ditto.

Daily bump.

openacc: Tests for character types in derived-type mappings

This patch adds some tests for character types that are components of
derived types used in OpenACC data-movement clauses.

gcc/testsuite/
* gfortran.dg/goacc/derived-chartypes-1.f90: New test.
* gfortran.dg/goacc/derived-chartypes-2.f90: Likewise.
* gfortran.dg/goacc/derived-chartypes-3.f90: Likewise.
* gfortran.dg/goacc/derived-chartypes-4.f90: Likewise.

openacc: Allow strided arrays in update directives

OpenACC 3.0 ("2.14.4. Update Directive") states:

  Noncontiguous subarrays may appear. It is implementation-specific
  whether noncontiguous regions are updated by using one transfer for
  each contiguous subregion, or whether the non-contiguous data is
  packed, transferred once, and unpacked, or whether one or more larger
  subarrays (no larger than the smallest contiguous region that contains
  the specified subarray) are updated.

This patch relaxes some conditions in the Fortran front-end so that
strided accesses are permitted for update directives.

gcc/fortran/
* openmp.c (resolve_omp_clauses): Omit OpenACC update in
contiguity check and stride-specified error.

gcc/testsuite/
* gfortran.dg/goacc/array-with-dt-2.f90: New test.

libgomp/
* testsuite/libgomp.oacc-fortran/array-stride-dt-1.f90: New test.

openacc: Use class_pointer instead of pointer attribute for class types

Elsewhere in the Fortran front-end, the class_pointer attribute is
used for BT_CLASS entities instead of the pointer attribute. This patch
follows suit for OpenACC. I couldn't actually come up with a test case
where this makes a difference (i.e., where "class_pointer" and "pointer"
have different values at this point in the code), but this may nonetheless
fix a latent bug.

gcc/fortran/
* trans-openmp.c (gfc_trans_omp_clauses): Use class_pointer attribute
for BT_CLASS.

openacc: Dereference BT_CLASS data pointers but not BT_DERIVED pointers

The stanza in gfc_trans_omp_clauses that handles derived type members
that are themselves derived type pointers or class pointers now adds
an explicit dereference only for the latter. The former is already
dereferenced transparently in gfc_conv_component_ref.

gcc/fortran/
* trans-openmp.c (gfc_trans_omp_clauses): Fix dereferencing for
BT_DERIVED members.

gcc/testsuite/
* gfortran.dg/goacc/derived-classtypes-1.f95: New test.

testsuite: Fix up pr25376.c on powerpc64-linux and array-quals-1.c on powerpc-linux [PR98325]

The following patch fixes the pr25376.c testcase on powerpc64-linux
and array-quals-1.c on powerpc-linux.
Previously it failed like:
FAIL: gcc.dg/array-quals-1.c scan-assembler-symbol-section symbol ^_?a1\$ (found a1) has section ^\\\\.(const|rodata|srodata)|\\\\[RO\\\\] (found .sdata)
FAIL: gcc.dg/array-quals-1.c scan-assembler-symbol-section symbol ^_?b1\$ (found b1) has section ^\\\\.(const|rodata|srodata)|\\\\[RO\\\\] (found .sdata)
FAIL: gcc.dg/array-quals-1.c scan-assembler-symbol-section symbol ^_?c1\$ (found c1) has section ^\\\\.(const|rodata|srodata)|\\\\[RO\\\\] (found .sdata)
FAIL: gcc.dg/array-quals-1.c scan-assembler-symbol-section symbol ^_?d1\$ (found d1) has section ^\\\\.(const|rodata|srodata)|\\\\[RO\\\\] (found .sdata)
FAIL: gcc.dg/array-quals-1.c scan-assembler-symbol-section symbol ^_?p\$ (found p) has section ^\\\\.(const|rodata|srodata)|\\\\[RW\\\\] (found .sdata)
FAIL: gcc.dg/array-quals-1.c scan-assembler-symbol-section symbol ^_?p1\$ (found p1) has section ^\\\\.(const|rodata|srodata)|\\\\[RW\\\\] (found .sdata)
FAIL: gcc.dg/array-quals-1.c scan-assembler-symbol-section symbol ^_?q\$ (found q) has section ^\\\\.(const|rodata|srodata)|\\\\[RW\\\\] (found .sdata)
FAIL: gcc.dg/array-quals-1.c scan-assembler-symbol-section symbol ^_?q1\$ (found q1) has section ^\\\\.(const|rodata|srodata)|\\\\[RW\\\\] (found .sdata)
FAIL: gcc.dg/array-quals-1.c scan-assembler-symbol-section symbol ^_?r\$ (found r) has section ^\\\\.(const|rodata|srodata)|\\\\[RW\\\\] (found .sdata)
FAIL: gcc.dg/array-quals-1.c scan-assembler-symbol-section symbol ^_?r1\$ (found r1) has section ^\\\\.(const|rodata|srodata)|\\\\[RW\\\\] (found .sdata)
FAIL: gcc.dg/array-quals-1.c scan-assembler-symbol-section symbol ^_?s\$ (found s) has section ^\\\\.(const|rodata|srodata)|\\\\[RW\\\\] (found .sdata)
FAIL: gcc.dg/array-quals-1.c scan-assembler-symbol-section symbol ^_?s1\$ (found s1) has section ^\\\\.(const|rodata|srodata)|\\\\[RW\\\\] (found .sdata)
FAIL: gcc.dg/array-quals-1.c scan-assembler-symbol-section symbol ^_?t\$ (found t) has section ^\\\\.(const|rodata|srodata)|\\\\[RW\\\\] (found .sdata)
FAIL: gcc.dg/array-quals-1.c scan-assembler-symbol-section symbol ^_?t1\$ (found t1) has section ^\\\\.(const|rodata|srodata)|\\\\[RW\\\\] (found .sdata)
FAIL: gcc.dg/pr25376.c scan-assembler-symbol-section symbol simple\$ (found .L.simple) has section ^\\\\.?my_named_section|simple\\\\[DS\\\\]|^\\\\"\\\\.opd\\\\" (found .opd)
FAIL: gcc.dg/pr25376.c scan-assembler-symbol-section symbol simple\$ (found simple) has section ^\\\\.?my_named_section|simple\\\\[DS\\\\]|^\\\\"\\\\.opd\\\\" (found .opd)

The problem with pr25376.c testcase are the ELFv1 function descriptors,
        .section        my_named_section,"ax",@progbits
        .align 2
        .globl simple
        .section        ".opd","aw"
        .align 3
simple:
        .quad   .L.simple,.TOC.@tocbase,0
        .previous
        .type   simple, @function
.L.simple:

so the simple symbol is found in the .opd section rather than in the
my_named_section the test attempts to verify for that symbol.
This patch deals it with two changes, the last two hunks in scanasm.exp
teach it about the behavior of .previous directive and the first hunk
for powerpc if symbol is in .opd section will try section in which the
.L.symbol label is instead.

The array-quals-1.c test fails because on powerpc-linux the symbols
are emitted into .sdata section rather than one of the expected ones.

2021-02-04  Jakub Jelinek  <jakub@redhat.com>

PR testsuite/98325
* lib/scanasm.exp (dg-scan-symbol-section): For powerpc*-*-* targets if
$section is .opd, look at .L.$symbol_name's section.
(parse_section_section_of_symbols): Handle .previous directive.
* gcc.dg/array-quals-1.c: Allow .sdata section.

d: Merge upstream dmd 46133f761, druntime 0fd4364c

D front-end changes:

 - Backported built-in function handling from upstream.

 - Added new intrinsic `byteswap(ushort)`.

Druntime changes:

 - Update intrinsic modules core.bitop, core.checkedint, core.simd,
   core.vararg, and core.volatile.

 - Backport platform-specific fixes for runtime modules core.cpuid,
   core.internal.traits, and rt.lifetime.

 - Backport openbsd fixes for core.stdc.stdio.

 - Backport solaris fixes for core.sys.posix.locale, and
   core.thread.osthread (PR98910).

gcc/d/ChangeLog:

* dmd/MERGE: Merge upstream dmd 46133f761.
* d-builtins.cc (d_build_builtins_module): Set builtins as BUILTINgcc.
(maybe_set_builtin_1): Likewise.
* d-frontend.cc (eval_builtin): Adjust condition for early return.
* intrinsics.cc (maybe_set_intrinsic): Set intrinsics as BUILTINgcc.
(maybe_expand_intrinsic): Add case for INTRINSIC_BSWAP16.
* intrinsics.def (INTRINSIC_BT): Update signature.
(INTRINSIC_BT64): Likewise.
(INTRINSIC_BSWAP16): New intrinsic.
(INTRINSIC_VLOAD8): Update module.
(INTRINSIC_VLOAD16): Likewise.
(INTRINSIC_VLOAD32): Likewise.
(INTRINSIC_VLOAD64): Likewise.
(INTRINSIC_VSTORE8): Likewise.
(INTRINSIC_VSTORE16): Likewise.
(INTRINSIC_VSTORE32): Likewise.
(INTRINSIC_VSTORE64): Likewise.
(INTRINSIC_ADDS): Update signature.
(INTRINSIC_ADDSL): Likewise.
(INTRINSIC_ADDU): Likewise.
(INTRINSIC_ADDUL): Likewise.
(INTRINSIC_SUBS): Likewise.
(INTRINSIC_SUBSL): Likewise.
(INTRINSIC_SUBU): Likewise.
(INTRINSIC_SUBUL): Likewise.
(INTRINSIC_MULS): Likewise.
(INTRINSIC_MULSL): Likewise.
(INTRINSIC_MULU): Likewise.
(INTRINSIC_MULUI): Likewise.
(INTRINSIC_MULUL): Likewise.
(INTRINSIC_NEGS): Likewise.
(INTRINSIC_NEGSL): Likewise.

libphobos/ChangeLog:

PR d/98910
* libdruntime/MERGE: Merge upstream druntime 0fd4364c.
* libdruntime/Makefile.am (DRUNTIME_DSOURCES): Add core/volatile.d.
* libdruntime/Makefile.in: Regenerate.
* testsuite/libphobos.allocations/tls_gc_integration.d: Update test.

gcc/testsuite/ChangeLog:

* gdc.dg/intrinsics.d: Update test.

PR c/97882 - Segmentation Fault on improper redeclaration of function

gcc/c/ChangeLog:

PR c/97882
* c-decl.c (locate_old_decl): Add type to diagnostic output.
(diagnose_mismatched_decls): Same.
(start_function): Introduce temporaries for better readability.
* c-typeck.c (comptypes_internal): Only consider complete enum
types in comparisons with integers.

gcc/testsuite/ChangeLog:

PR c/97882
* gcc.dg/decl-8.c: Adjust text of expected diagnostic.
* gcc.dg/label-decl-4.c: Same.
* gcc.dg/mismatch-decl-1.c: Same.
* gcc.dg/old-style-then-proto-1.c: Same.
* gcc.dg/parm-mismatch-1.c: Same.
* gcc.dg/pr35445.c: Same.
* gcc.dg/redecl-11.c: Same.
* gcc.dg/redecl-12.c: Same.
* gcc.dg/redecl-13.c: Same.
* gcc.dg/redecl-15.c: Same.
* gcc.dg/tls/thr-init-1.c: Same.
* objc.dg/id-1.m: Same.
* objc.dg/tls/diag-3.m: Same.
* gcc.dg/pr97882.c: New test.
* gcc.dg/qual-return-7.c: New test.
* gcc.dg/qual-return-8.c: New test.

c++: Empty args for variadic concept [PR98717]

Nice when fixing a bug is as easy as removing incorrect checks.

gcc/cp/ChangeLog:

PR c++/98717
* constraint.cc (build_concept_check_arguments): Remove assert.
(build_concept_check): Allow empty args.

gcc/testsuite/ChangeLog:

PR c++/98717
* g++.dg/cpp2a/concepts-variadic3.C: New test.

diagnostics: fix excessive range-printing involving macros [PR97932]

PR c/97932 describes a bug in which diagnostic_show_locus prints most
of a source file.

The issue is that it prints a range in which the start and end locations
are part of the same macro map, but the start location is for a token in
the definition of the macro, whereas the end location is for a token in
an argument of the macro.

This patch extends compatible_locations_p to require that range-printing
of macro maps requires the location to either be both for the definition
of the macro, or both for the arguments of the macro (not one of each),
fixing the issue.

gcc/ChangeLog:
PR c/97932
* diagnostic-show-locus.c (compatible_locations_p): Require
locations in the same macro map to be either both from the
macro definition, or both from the macro arguments.

gcc/testsuite/ChangeLog:
PR c/97932
* gcc.dg/pr97932.c: New test.

Correct date value of the __cpp_size_t_suffix macro.

The value of __cpp_size_t_suffix is 202011 not 202006.

gcc/c-family/ChangeLog:

* c-cppbuiltin.c (c_cpp_builtins): __cpp_size_t_suffix=202011L.

gcc/testsuite/ChangeLog:

* g++.dg/cpp23/feat-cxx2b.C: __cpp_size_t_suffix == 202011.

c++, libcpp: Use make_signed_t<size_t> in the 1z diagnostics

The following patch uses make_signed_t<size_t> instead of
make_signed<size_t>::type in the diagnostics, because the former is shorter.
It is true that one can't use make_signed<size_t>::type in C++11 code (which
is why I haven't changed it in the testcase which is c++11 effective
target), but the message talks about C++23 and make_signed_t is a C++14 and
later feature, so I think it is fine.

2021-02-04  Jakub Jelinek  <jakub@redhat.com>

* expr.c (cpp_classify_number): Use make_signed_t<size_t> instead of
make_signed<size_t>::type in the diagnostics.

* g++.dg/warn/Wsize_t-literals.C: Expect make_signed_t<size_t> instead
of make_signed<size_t>::type in the diagnostics.

c++: fix string literal member initializer bug [PR90926]

build_aggr_conv did not correctly handle string literal member initializers.
Extended can_convert_array to handle this case. For the additional check of
compatibility of character types, factored out code from digest_init_r into
a new function.

gcc/cp/ChangeLog:

PR c++/90926
* call.c (can_convert_array): Extend to handle all valid aggregate
initializers of an array; including by string literals, not just by
brace-init-list.
(build_aggr_conv): Call can_convert_array more often, not just in
brace-init-list case.
* typeck2.c (array_string_literal_compatible_p): New function.
(digest_init_r): call array_string_literal_compatible_p
* cp-tree.h: (array_string_literal_compatible_p): Declare.

gcc/testsuite/ChangeLog:

PR c++/90926
* g++.dg/cpp1y/nsdmi-aggr12.C: New test.

aarch64: Use RTL builtins for [su]mull_high_lane[q] intrinsics

Rewrite [su]mull_high_lane[q] Neon intrinsics to use RTL builtins
rather than inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-02-03  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add
[su]mull_hi_lane[q] builtin generator macros.
* config/aarch64/aarch64-simd.md
(aarch64_<su>mull_hi_lane<mode>_insn): Define.
(aarch64_<su>mull_hi_lane<mode>): Define.
(aarch64_<su>mull_hi_laneq<mode>_insn): Define.
(aarch64_<su>mull_hi_laneq<mode>): Define.
* config/aarch64/arm_neon.h (vmull_high_lane_s16): Use RTL
builtin instead of inline asm.
(vmull_high_lane_s32): Likewise.
(vmull_high_lane_u16): Likewise.
(vmull_high_lane_u32): Likewise.
(vmull_high_laneq_s16): Likewise.
(vmull_high_laneq_s32): Likewise.
(vmull_high_laneq_u16): Likewise.
(vmull_high_laneq_u32): Liekwise.

aarch64: Use RTL builtins for [su]mull_high_n intrinsics

Rewrite [su]mull_high_n Neon intrinsics to use RTL builtins rather
than inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-02-03  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add [su]mull_hi_n
builtin generator macros.
* config/aarch64/aarch64-simd.md
(aarch64_<su>mull_hi_n<mode>_insn): Define.
(aarch64_<su>mull_hi_n<mode>): Define.
* config/aarch64/arm_neon.h (vmull_high_n_s16): Use RTL builtin
instead of inline asm.
(vmull_high_n_s32): Likewise.
(vmull_high_n_u16): Likewise.
(vmull_high_n_u32): Likewise.

tree-optimization/98855 - fix some vectorizer cost issues

This fixes us not costing vectorized bswap for SLP as well as
avoiding biasing to the vectorized side when costing single-argument
PHIs.  Instead we assume coalescing here and cost them with zero cost
for both the scalar and vectorized code.

This doesn't fix the PR on its own.

2021-02-04  Richard Biener  <rguenther@suse.de>

PR tree-optimization/98855
* tree-vect-loop.c (vectorizable_phi): Do not cost
single-argument PHIs.
* tree-vect-slp.c (vect_bb_slp_scalar_cost): Likewise.
* tree-vect-stmts.c (vectorizable_bswap): Also perform
costing for SLP operation.

Fortran: OpenMP/OpenACC diagnose substring rejections better

gcc/fortran/ChangeLog:

* openmp.c (resolve_omp_clauses): Explicitly diagnose
substrings as not permitted.

gcc/testsuite/ChangeLog:

* gfortran.dg/goacc/substring.f90: New test.
* gfortran.dg/gomp/substring.f90: New test.

doc: mention -mprefer-vector-width in target attrs

gcc/ChangeLog:

* doc/extend.texi: Mention -mprefer-vector-width in target
attributes.

gcc/testsuite/ChangeLog:

* gcc.target/i386/prefer-vector-width-attr.c: New test.

c++: No aggregate CTAD with explicit dguide [PR98802]

In my implementation of P2082R1 I missed this piece: the aggregate deduction
candidate is not generated if the class has user-written deduction guides.

gcc/cp/ChangeLog:

PR c++/98802
* pt.c (do_class_deduction): No aggregate guide if any_dguides_p.

gcc/testsuite/ChangeLog:

PR c++/98802
* g++.dg/cpp1z/class-deduction78.C: New test.

c++: subst failure in attribute argument [PR95192]

Another SFINAE issue: we weren't propagating substitution failure in
attributes back up.  And tsubst_function_decl needs to check substitution
before register_specialization.  I thought about moving the other error
returns up as well, but they aren't SFINAE cases, so they can stay where
they are.

This change caused pr84630.C to stop giving an error; this was because
partial instantiation of the lambda failed silently, and before the change
that meant error_mark_node passed to decl_attributes, which complained about
there being an argument at all.  With the change the partial instantiation
fails, but no error was ever given, because push_template_decl silently
failed if current_template_parms wasn't set.  So let's set c_t_p
appropriately.  lambda-uneval13.C is a valid testcase to exercise this.

gcc/cp/ChangeLog:

PR c++/95192
* pt.c (tsubst_attribute): Handle error.
(apply_late_template_attributes): Return false on error.
(tsubst_function_decl): Check its return value.
(tsubst_decl): Likewise.
(push_template_decl): Assert current_template_parms.
(tsubst_template_decl): Set current_template_parms.

gcc/testsuite/ChangeLog:

PR c++/95192
* g++.dg/cpp0x/pr84630.C: Call b().
* g++.dg/cpp2a/lambda-uneval13.C: New test.
* g++.dg/ext/attr-expr1.C: New test.

Daily bump.

libcpp: Fix up -fdirectives-only preprocessing [PR98882]

GCC 11 ICEs on all -fdirectives-only preprocessing when the files don't end
with a newline.

The problem is in the assertion, for empty TUs buffer->cur == buffer->rlimit
and so buffer->rlimit[-1] access triggers UB in the preprocessor, for
non-empty TUs it refers to the last character in the file, which can be
anything.
The preprocessor adds a '\n' character (or '\r', in particular if the
user file ends with '\r' then it adds another '\r' rather than '\n'), but
that is added after the limit, i.e. at buffer->rlimit[0].

Now, if the routine handles occassional bumping of pos to buffer->rlimit + 1,
I think it is just the assert that needs changing, usually we read from *pos
if pos < limit and then e.g. if it is '\r', look at the following character
(which could be one of those '\n' or '\r' at buffer->rlimit[0]).  There is
also the case where for '\\' before the limit we read following character
and if it is '\n', do one thing, if it is '\r' read another character.
But in that case if '\\' was the last char in the TU, the limit char will be
'\n', so we are ok.

2021-02-03  Jakub Jelinek  <jakub@redhat.com>

PR preprocessor/98882
* lex.c (cpp_directive_only_process): Don't assert that rlimit[-1]
is a newline, instead assert that rlimit[0] is either newline or
carriage return.  When seeing '\\' followed by '\r', check limit
before accessing pos[1].

* gcc.dg/cpp/pr98882.c: New test.

Fix typo in Fortran manual

gcc/fortran:
* intrinsic.texi (ANINT): Fix typo.

libphobos: Merge upstream druntime 9d0c8364, phobos 9d575282e.

Druntime changes:

 - Add platform-specific bindings for stdlib.h and sys/syctl.h.

 - Add darwin bindings for mach/dyld.h.

 - Fix solaris bindings for locale.h (PR98910).

 - Remove deprecated bindings from the module headers.

Phobos changes:

 - Backport platform-specific fixes for std.conv, std.datetime,
   std.exception, std.experimental.allocator, std.file, std.math,
   std.parallelism, std.socket, std.stdio, and std.system.

Reviewed-on: https://github.com/dlang/druntime/pull/3363
     https://github.com/dlang/phobos/pull/7784

libphobos/ChangeLog:

PR d/98910
* libdruntime/MERGE: Merge upstream druntime 9d0c8364.
* libdruntime/Makefile.am (DRUNTIME_DSOURCES): Add
  core/internal/attributes.d
(DRUNTIME_DSOURCES_BIONIC): Add core/sys/bionic/stdlib.d.
(DRUNTIME_DSOURCES_DARWIN): Add core/sys/darwin/stdlib.d, and
core/sys/darwin/sys/sysctl.d.
(DRUNTIME_DSOURCES_DRAGONFLYBSD): Add
core/sys/dragonflybsd/stdlib.d, and
core/sys/dragonflybsd/sys/sysctl.d.
(DRUNTIME_DSOURCES_FREEBSD): Add core/sys/freebsd/stdlib.d, and
core/sys/freebsd/sys/sysctl.d.
(DRUNTIME_DSOURCES_NETBSD): Add core/sys/netbsd/stdlib.d, and
core/sys/netbsd/sys/sysctl.d.
(DRUNTIME_DSOURCES_OPENBSD): Add core/sys/openbsd/stdlib.d, and
core/sys/openbsd/sys/sysctl.d.
(DRUNTIME_DSOURCES_SOLARIS): Add core/sys/solaris/stdlib.d.
* libdruntime/Makefile.in: Regenerate.
* src/MERGE: Merge upstream phobos 9d575282e.

c++: Mark member functions as const [PR98951]

These member functions look like they could be marked const, since
they don't modify any (non-mutable) class members.

PR c++/98951
* call.c (struct z_candidate): Mark rewritten and reversed as const.
(struct NonPublicField): Mark operator() as const.
(struct NonTrivialField): Likewise.

c++: Fix alias comparison [PR98926]

The comparison of dependent aliases wasn't working here because
processing_template_decl wasn't set, so dependent_alias_template_spec_p was
always returning false.

gcc/cp/ChangeLog:

PR c++/98926
PR c++/98570
* pt.c (spec_hasher::equal): Set processing_template_decl.
* Make-lang.in (check-g++-strict-gc): Add --param
hash-table-verification-limit=10000.

gcc/testsuite/ChangeLog:

* g++.dg/cpp0x/alias-decl-dr1558.C: Pass --param
hash-table-verification-limit=10000.

PR tree-optimization/98937 - pointer_query cache leaks

gcc/ChangeLog:

PR tree-optimization/98937
* tree-ssa-strlen.c (strlen_dom_walker::~strlen_dom_walker): Define.
Flush pointer_query cache.

c++: Implement C++23 P0330 - Literal Suffixes for ptrdiff_t and size_t.

Integer literal suffixes for signed size ('z') and unsigned size
(some permutation od 'zu') are provided as a language addition.

gcc/c-family/ChangeLog:

* c-cppbuiltin.c (c_cpp_builtins): Define __cpp_size_t_suffix.
* c-lex.c (interpret_integer): Set node type for size literal.

libcpp/ChangeLog:

* expr.c (interpret_int_suffix): Detect 'z' integer suffix.
(cpp_classify_number): Compat warning for use of 'z' suffix.
* include/cpplib.h (struct cpp_options): New flag.
(enum cpp_warning_reason): New flag.
(CPP_N_USERDEF): Comment C++0x -> C++11.
(CPP_N_SIZE_T): New flag for cpp_classify_number.
* init.c (cpp_set_lang): Initialize new flag.

gcc/testsuite/ChangeLog:

* g++.dg/cpp0x/udlit-shadow-neg.C: Test for 'z' and 'zu' shadowing.
* g++.dg/cpp23/feat-cxx2b.C: New test.
* g++.dg/cpp23/size_t-literals.C: New test.
* g++.dg/warn/Wsize_t-literals.C: New test.

libgo: install new 1.16 packages

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/289069

testsuite: Add test for already fixed PR [PR97804]

This testcase got fixed with the PR98463
r11-6895-g94ff4c9dd98f39280fba22d1ad0958fb25a5363b fix.

2021-02-03  Jakub Jelinek  <jakub@redhat.com>

PR c++/97804
* g++.dg/cpp2a/no_unique_address11.C: New test.

libstdc++: Fix incorrect test for std::error_code comparisons

The tests for std::error_code comparisons assumed that a default
constructed object uses std::generic_category(). That's true for a
default constructed std::error_condition, but not std::error_code.

Fix the three-way comparisons to correctly depend on the result of
comparing the categories, and add another test for comparing two objects
with the same category and different values.

libstdc++-v3/ChangeLog:

* testsuite/19_diagnostics/error_code/operators/not_equal.cc:
Add comparison with same category and different values.
* testsuite/19_diagnostics/error_code/operators/less.cc:
Likewise. Fix comparison involving different categories.
* testsuite/19_diagnostics/error_code/operators/three_way.cc:
Likewise.
* testsuite/19_diagnostics/error_condition/operators/less.cc:
Add comment.
* testsuite/19_diagnostics/error_condition/operators/three_way.cc:
Likewise.

libstdc++: Improve "find_first/last_set" for NEON

The find_first_set and find_last_set method is not optimal for neon, it
needs to be improved by synthesized with horizontal adds(vaddv) which
will reduce the generated assembly code. In the following cases,
vaddvq_s16 will generate 2 instructions but vpadd_s16 will generate 4
instructions:

 # vaddvq_s16
    vaddvq_s16(__asint);
    //  addv    h0, v1.8h
    //  smov    w1, v0.h[0]
 # vpadd_s16
    vpaddq_s16(vpaddq_s16(vpaddq_s16(__asint, __zero), __zero), __zero)[0]
    // addp v1.8h,v1.8h,v2.8h
    // addp v1.8h,v1.8h,v2.8h
    // addp v1.8h,v1.8h,v2.8h
    // smov    w1, v1.h[0]
 #

libstdc++-v3/ChangeLog:

* include/experimental/bits/simd_neon.h: Replace repeated vpadd
calls with a single vaddv for aarch64.

libstdc++: Work around test failures using -mno-tree-vrp

This is necessary to avoid failures resulting from PR98834.

libstdc++-v3/ChangeLog:

* testsuite/Makefile.am: Warn about the workaround. Add
-fno-tree-vrp to CXXFLAGS passed to the check_simd script.
Improve initial user feedback from make check-simd.
* testsuite/Makefile.in: Regenerated.

libstc++: Implement hmin and hmax

From 9.7.4 in Parallelism TS 2. For some reason I overlooked these two
functions. Implement them via call to _S_reduce.

libstdc++-v3/ChangeLog:

* include/experimental/bits/simd.h: Add __detail::_Minimum and
__detail::_Maximum to use them as _BinaryOperation to _S_reduce.
Add hmin and hmax overloads for simd and const_where_expression.
* include/experimental/bits/simd_scalar.h
(_SimdImplScalar::_S_reduce): Make unused _BinaryOperation
parameter const-ref to allow calling _S_reduce with an rvalue.
* testsuite/experimental/simd/tests/reductions.cc: Add tests for
hmin and hmax. Since the compiler statically determined that all
tests pass, repeat the test after a call to make_value_unknown.

libstdc++: Improve test codegen for interpreting assembly

In many failure cases it is helpful to inspect the instructions leading
up to the test failure. After this change the location is easier to find
and the branch after failure is easier to find.

libstdc++-v3/ChangeLog:

* testsuite/experimental/simd/tests/bits/verify.h (verify): Add
instruction pointer data member. Ensure that the `if (m_failed)`
branch is always inlined into the calling code. The body of the
conditional can still be a function call. Move the get_ip call
into the verify ctor to simplify the ctor calls.
(COMPARE): Don't mention the use of all_of for reduction of a
simd_mask. It only distracts from the real issue.

libstdc++: Support timeout and timeout-factor options

libstdc++-v3/ChangeLog:

* testsuite/experimental/simd/driver.sh: Abstract reading test
options into read_src_option function. Read skip, only,
expensive, and xfail via read_src_option. Add timeout and
timeout-factor options and adjust timeout variable accordingly.
* testsuite/experimental/simd/tests/loadstore.cc: Set
timeout-factor 2.

libstdc++: Abort test after 1000 lines of output

Handle overly large output by aborting the log and thus the test. This
is a similar condition to a timeout.

libstdc++-v3/ChangeLog:

* testsuite/experimental/simd/driver.sh: When handling the pipe
to log (and on verbose to stdout) count the lines. If it exceeds
1000 log the issue and exit 125, which is then handled as a
failure.

libstdc++: Skip testing hypot3 for long double on PPC

std::hypot(a, b, c) is imprecise and makes this test fail even though
the failure is unrelated to simd.

libstdc++-v3/ChangeLog:

* testsuite/experimental/simd/tests/hypot3_fma.cc: Add skip:
markup for long double on powerpc64*.

libstdc++: Fix mask reduction of simd_mask<double> on POWER7

POWER7 does not support __vector long long reductions, making the
generic _S_popcount implementation ill-formed. Specializing _S_popcount
for PPC allows optimization and avoids the issue.

libstdc++-v3/ChangeLog:

* include/experimental/bits/simd.h: Add __have_power10vec
conditional on _ARCH_PWR10.
* include/experimental/bits/simd_builtin.h: Forward declare
_MaskImplPpc and use it as _MaskImpl when __ALTIVEC__ is
defined.
(_MaskImplBuiltin::_S_some_of): Call _S_popcount from the
_SuperImpl for optimizations and correctness.
* include/experimental/bits/simd_ppc.h: Add _MaskImplPpc.
(_MaskImplPpc::_S_popcount): Implement via vec_cntm for POWER10.
Otherwise, for >=int use -vec_sums divided by a sizeof factor.
For <int use -vec_sums(vec_sum4s(...)) to sum all mask entries.

libstdc++: Immediate feedback with -v

libstdc++-v3/ChangeLog:

* testsuite/experimental/simd/driver.sh: Remove executable on
SIGINT. Process compiler and test executable output: In verbose
mode print messages immediately, limited to 1000 lines and
breaking long lines to below $COLUMNS (or 1024 if not set).
Communicating the exit status of the compiler / test with the
necessary pipe is done via a message through stdout/-in.

libstdc++: Fix incorrect display of old test summaries

libstdc++-v3/ChangeLog:

* testsuite/Makefile.am: Ensure .simd.summary is empty before
collecting a new summary.
* testsuite/Makefile.in: Regenerate.

libstdc++: Fix DRIVEROPTS and TESTFLAGS processing

libstdc++-v3/ChangeLog:

* testsuite/experimental/simd/generate_makefile.sh: Use
different variables internally than documented for user
overrides. This makes internal append/prepend work as intended.

libstdc++: Fix several check-simd interaction issues

libstdc++-v3/ChangeLog:

* testsuite/experimental/simd/driver.sh (verify_test): Print
test output on run xfail. Do not repeat lines from the log that
were already printed on stdout.
(test_selector): Make the compiler flags pattern usable as a
substring selector.
(toplevel): Trap on SIGINT and remove the log and sum files.
Call timout with --foreground to quickly terminate on SIGINT.
* testsuite/experimental/simd/generate_makefile.sh: Simplify run
targets via target patterns. Default DRIVEROPTS to -v for run
targets. Remove log and sum files after completion of the run
target (so that it's always recompiled).
Place help text into text file for reasonable 'make help'
performance.

libstdc++: Fix simd_mask<double> on POWER w/o POWER8

libstdc++-v3/ChangeLog:

* include/experimental/bits/simd.h: Remove unnecessary static
assertion. Allow sizeof(8) integer __intrinsic_type to enable
the necessary mask type.

libstdc++: Support -mlong-double-64 on PPC

libstdc++-v3/ChangeLog:

* include/experimental/bits/simd.h: Let __intrinsic_type<long
double, N> be valid if sizeof(long double) == sizeof(double) and
use a __vector double as member type.

libstdc++: Fix NEON intrinsic types usage

Intrinsics types for NEON differ from gnu::vector_size types now. This
requires explicit specializations for __intrinsic_type and a new
__is_intrinsic_type trait.

libstdc++-v3/ChangeLog:

* include/experimental/bits/simd.h (__is_intrinsic_type): New
internal type trait. Alias for __is_vector_type on x86.
(_VectorTraitsImpl): Enable for __intrinsic_type in addition for
__vector_type.
(__intrin_bitcast): Allow casting to & from vector & intrinsic
types.
(__intrinsic_type): Explicitly specialize for NEON intrinsic
vector types.

libstdc++: Support skip, only, expensive, and xfail markers for simd tests

libstdc++-v3/ChangeLog:

* testsuite/experimental/simd/driver.sh: Implement skip, only,
expensive, and xfail markers. They can select on type, ABI tag
subset number, target-triplet, and compiler flags.
* testsuite/experimental/simd/generate_makefile.sh: The summary
now includes lines for unexpected passes and expected failures.
If the skip or only markers are only conditional on the type, do
not generate rules for those types.
* testsuite/experimental/simd/tests/abs.cc: Mark test expensive
for ABI tag subsets 1-9.
* testsuite/experimental/simd/tests/algorithms.cc: Ditto.
* testsuite/experimental/simd/tests/broadcast.cc: Ditto.
* testsuite/experimental/simd/tests/casts.cc: Ditto.
* testsuite/experimental/simd/tests/generator.cc: Ditto.
* testsuite/experimental/simd/tests/integer_operators.cc: Ditto.
* testsuite/experimental/simd/tests/loadstore.cc: Ditto.
* testsuite/experimental/simd/tests/mask_broadcast.cc: Ditto.
* testsuite/experimental/simd/tests/mask_conversions.cc: Ditto.
* testsuite/experimental/simd/tests/mask_implicit_cvt.cc: Ditto.
* testsuite/experimental/simd/tests/mask_loadstore.cc: Ditto.
* testsuite/experimental/simd/tests/mask_operator_cvt.cc: Ditto.
* testsuite/experimental/simd/tests/mask_operators.cc: Ditto.
* testsuite/experimental/simd/tests/mask_reductions.cc: Ditto.
* testsuite/experimental/simd/tests/operator_cvt.cc: Ditto.
* testsuite/experimental/simd/tests/operators.cc: Ditto.
* testsuite/experimental/simd/tests/reductions.cc: Ditto.
* testsuite/experimental/simd/tests/simd.cc: Ditto.
* testsuite/experimental/simd/tests/split_concat.cc: Ditto.
* testsuite/experimental/simd/tests/splits.cc: Ditto.
* testsuite/experimental/simd/tests/where.cc: Ditto.
* testsuite/experimental/simd/tests/fpclassify.cc: Ditto. In
addition replace "test only floattypes" marker by unconditional
"float|double|ldouble" only marker.
* testsuite/experimental/simd/tests/frexp.cc: Ditto.
* testsuite/experimental/simd/tests/hypot3_fma.cc: Ditto.
* testsuite/experimental/simd/tests/ldexp_scalbn_scalbln_modf.cc:
Ditto.
* testsuite/experimental/simd/tests/logarithm.cc: Ditto.
* testsuite/experimental/simd/tests/math_1arg.cc: Ditto.
* testsuite/experimental/simd/tests/math_2arg.cc: Ditto.
* testsuite/experimental/simd/tests/remqo.cc: Ditto.
* testsuite/experimental/simd/tests/trigonometric.cc: Ditto.
* testsuite/experimental/simd/tests/trunc_ceil_floor.cc: Ditto.
* testsuite/experimental/simd/tests/sincos.cc: Ditto. In
addition, xfail on run because the reference data is missing.

Fix earlier commit missing patch review changes

Somehow I lost my fixes based on Segher's review of the p10
logical-logical fusion patch. This commit adds the changes that
should have been there before. Bootstrap/regtest passed.

gcc/ChangeLog:

* config/rs6000/genfusion.pl (gen_2logical): Add missing
fixes based on patch review.
* config/rs6000/fusion.md: Regenerate file.

do not generate fusion.md, update contrib/gcc_update

In a previous fusion-combine patch for rs6000, Segher had asked me to
comment out the automatic regeneration of fusion.md. And more recently
Edelsohn pointed out that gcc_update needed to fix the timestamp of
fusion.md so it didn't get unnecessarily regenerated.

contrib/ChangeLog:

* gcc_update (files_and_dependencies): Add dependency for
gcc/config/rs6000/fusion.md on gcc/config/rs6000/genfusion.md.

gcc/ChangeLog:

* config/rs6000/t-rs6000: Comment out auto generation of
fusion.md for now.

c++: ICE with late parsing of noexcept in nested class [PR98899]

Here we crash with a noexcept-specifier in a nested template class,
because my handling of such deferred-parse noexcept-specifiers was
gronked when we need to instantiate a DEFERRED_PARSE before it was
actually parsed at the end of the outermost class.

In

  struct S {
    template<class> struct B {
      B() noexcept(noexcept(x));
      int x;
    };
    struct A : B<int> {
      A() : B() {}
    };
  };

we call complete_type for B<int> which triggers tsubsting S::B<int>::B()
whose noexcept-specifier still contains a DEFERRED_PARSE.  The trick is
to stash such noexcept-specifiers into DEFPARSE_INSTANTIATIONS so that
we can replace it later when we've finally parsed all deferred
noexcept-specifiers.

In passing, fix missing usage of UNPARSED_NOEXCEPT_SPEC_P.

gcc/cp/ChangeLog:

PR c++/98899
* parser.c (cp_parser_class_specifier_1): Use any possible
DEFPARSE_INSTANTIATIONS to update DEFERRED_NOEXCEPT_PATTERN.
(cp_parser_save_noexcept): Initialize DEFPARSE_INSTANTIATIONS.
* pt.c (tsubst_exception_specification): Stash new_specs into
DEFPARSE_INSTANTIATIONS.
* tree.c (fixup_deferred_exception_variants): Use
UNPARSED_NOEXCEPT_SPEC_P.

gcc/testsuite/ChangeLog:

PR c++/98899
* g++.dg/cpp0x/noexcept65.C: New test.

amdgcn: Add gfx908 support

gcc/

* config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX908.
* config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Add gfx908.
(output_file_start): Add gfx908.
* config/gcn/gcn.opt (gpu_type): Add gfx908.
* config/gcn/t-gcn-hsa (MULTILIB_OPTIONS): Add march=gfx908.
(MULTILIB_DIRNAMES): Add gfx908.
* config/gcn/mkoffload.c (EF_AMDGPU_MACH_AMDGCN_GFX908): New define.
(main): Recognize gfx908.
* config/gcn/t-omp-device: Add gfx908.

libgomp/

* plugin/plugin-gcn.c (EF_AMDGPU_MACH): Add
EF_AMDGPU_MACH_AMDGCN_GFX908.
(gcn_gfx908_s): New constant string.
(isa_hsa_name): Add gfx908.
(isa_code): Add gfx908.

aarch64: Use RTL builtins for [su]mlsl_high_lane[q] intrinsics

Rewrite [su]mlsl_high_lane[q] Neon intrinsics to use RTL builtins
rather than inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-02-02  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add
[su]mlsl_hi_lane[q] builtin macro generators.
* config/aarch64/aarch64-simd.md
(aarch64_<su>mlsl_hi_lane<mode>_insn): Define.
(aarch64_<su>mlsl_hi_lane<mode>): Define.
(aarch64_<su>mlsl_hi_laneq<mode>_insn): Define.
(aarch64_<su>mlsl_hi_laneq<mode>): Define.
* config/aarch64/arm_neon.h (vmlsl_high_lane_s16): Use RTL
builtin instead of inline asm.
(vmlsl_high_lane_s32): Likewise.
(vmlsl_high_lane_u16): Likewise.
(vmlsl_high_lane_u32): Likewise.
(vmlsl_high_laneq_s16): Likewise.
(vmlsl_high_laneq_s32): Likewise.
(vmlsl_high_laneq_u16): Likewise.
(vmlsl_high_laneq_u32): Likewise.
(vmlal_high_laneq_u32): Likewise.

aarch64: Use RTL builtins for [su]mlal_high_lane[q] intrinsics

Rewrite [su]mlal_high_lane[q] Neon intrinsics to use RTL builtins
rather than inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-02-02  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add
[su]mlal_hi_lane[q] builtin generator macros.
* config/aarch64/aarch64-simd.md
(aarch64_<su>mlal_hi_lane<mode>_insn): Define.
(aarch64_<su>mlal_hi_lane<mode>): Define.
(aarch64_<su>mlal_hi_laneq<mode>_insn): Define.
(aarch64_<su>mlal_hi_laneq<mode>): Define.
* config/aarch64/arm_neon.h (vmlal_high_lane_s16): Use RTL
builtin instead of inline asm.
(vmlal_high_lane_s32): Likewise.
(vmlal_high_lane_u16): Likewise.
(vmlal_high_lane_u32): Likewise.
(vmlal_high_laneq_s16): Likewise.
(vmlal_high_laneq_s32): Likewise.
(vmlal_high_laneq_u16): Likewise.
(vmlal_high_laneq_u32): Likewise.

aarch64: Use RTL builtins for [su]mlsl_high_n intrinsics

Rewrite [su]mlsl_high_n Neon intrinsics to use RTL builtins rather
than inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-01-27  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add [su]mlsl_hi_n
builtin generator macros.
* config/aarch64/aarch64-simd.md (aarch64_<su>mlsl_hi_n<mode>_insn):
Define.
(aarch64_<su>mlsl_hi_n<mode>): Define.
* config/aarch64/arm_neon.h (vmlsl_high_n_s16): Use RTL builtin
instead of inline asm.
(vmlsl_high_n_s32): Likewise.
(vmlsl_high_n_u16): Likewise.
(vmlsl_high_n_u32): Likewise.

aarch64: Use RTL builtins for [su]mlal_high_n intrinsics

Rewrite [su]mlal_high_n Neon intrinsics to use RTL builtins rather
than inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-01-27  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add [su]mlal_hi_n
builtin generator macros.
* config/aarch64/aarch64-simd.md (aarch64_<su>mlal_hi_n<mode>_insn):
Define.
(aarch64_<su>mlal_hi_n<mode>): Define.
* config/aarch64/arm_neon.h (vmlal_high_n_s16): Use RTL builtin
instead of inline asm.
(vmlal_high_n_s32): Likewise.
(vmlal_high_n_u16): Likewise.
(vmlal_high_n_u32): Likewise.

aarch64: Use RTL builtins for [su]mlal_high intrinsics

Rewrite [su]mlal_high Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-01-27  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add RTL builtin
generator macros.
* config/aarch64/aarch64-simd.md (*aarch64_<su>mlal_hi<mode>):
Rename to...
(aarch64_<su>mlal_hi<mode>_insn): This.
(aarch64_<su>mlal_hi<mode>): Define.
* config/aarch64/arm_neon.h (vmlal_high_s8): Use RTL builtin
instead of inline asm.
(vmlal_high_s16): Likewise.
(vmlal_high_s32): Likewise.
(vmlal_high_u8): Likewise.
(vmlal_high_u16): Likewise.
(vmlal_high_u32): Likewise.

lra: clear lra_insn_recog_data after simplifying a mem subreg

Suppose we have:

    (insn (set (reg:FPRX2 70) (subreg:FPRX2 (reg/v:TF 63) 0)))

where operand_loc[0] points to r70 and operand_loc[1] points to r63.
If r63 is spilled, remove_pseudos() will change this insn to:

  (insn (set (reg:FPRX2 70)
             (subreg:FPRX2 (mem/c:TF (plus:DI (reg:DI %fp)
                                      (const_int 144))))))

This is fine so far: rtx pointed to by operand_loc[1] has been changed
from (reg) to (mem), but its slot is still under (subreg).  However,
alter_subreg() will simplify this insn to:

  (insn (set (reg:FPRX2 70)
             (mem/c:FPRX2 (plus:DI (reg:DI %fp) (const_int 144)))))

The (subreg) is gone, and therefore operand_loc[1] is no longer valid.
This will prevent process_insn_for_elimination() from updating the spill
slot offset, causing miscompilation: different instructions will refer
to the same spill slot using different offsets.

Fix by clearing all the cached data, and not just used_insn_alternative.

gcc/ChangeLog:

2021-01-13  Ilya Leoshkevich  <iii@linux.ibm.com>

* lra-spills.c (remove_pseudos): Call lra_update_insn_recog_data()
after calling alter_subreg() on a (mem).

Fill up padding in lto_section struct.

gcc/ChangeLog:

PR lto/98912
* lto-streamer-out.c (produce_lto_section): Fill up missing
padding.
* lto-streamer.h (struct lto_section): Add _padding field.

Fix regression with partial rep clause on variant record type

It can yield an incorrect layout when there is a partial representation
clause on a discriminated record type with a variant part.

gcc/ada/
* gcc-interface/decl.c (components_to_record): If the first component
with rep clause is the _Parent field with variable size, temporarily
set it aside when computing the internal layout of the REP part again.
* gcc-interface/utils.c (finish_record_type): Revert to taking the
maximum when merging sizes for all record types with rep clause.
(merge_sizes): Put SPECIAL parameter last and adjust recursive calls.

Assorted LTO fixes for Ada

This polishes a few rough edges visible in LTO mode.

gcc/ada/
* gcc-interface/decl.c (gnat_to_gnu_entity) <E_Array_Type>: Make the
two fields of the fat pointer type addressable, and do not make the
template type read-only.
<E_Record_Type>: If the type has discriminants mark it as may_alias.
* gcc-interface/utils.c (make_dummy_type): Likewise.
(build_dummy_unc_pointer_types): Likewise.

Fortran: Fix Array dependency with local coarrays [PR98913]

gcc/fortran/ChangeLog:

PR fortran/98913
* dependency.c (gfc_dep_resolver): Treat local access
to coarrays like any array access in dependency analysis.

gcc/testsuite/ChangeLog:

PR fortran/98913
* gfortran.dg/coarray/array_temporary.f90: New test.

more memory leak fixes

This fixes more memory leaks as discovered by building 521.wrf_r.

2021-02-03  Richard Biener  <rguenther@suse.de>

* lto-streamer.c (lto_get_section_name): Free temporary
buffer.
* tree-loop-distribution.c
(loop_distribution::merge_dep_scc_partitions): Free edge data.

ifcvt: Avoid ICEs trying to force_operand random RTL [PR97487]

As the testcase shows, RTL ifcvt can throw random RTL (whatever it found in
some insns) at expand_binop or expand_unop and expects it to do something
(and then will check if it created valid insns and punts if not).
These functions in the end if the operands don't match try to
copy_to_mode_reg the operands, which does
if (!general_operand (x, VOIDmode))
  x = force_operand (x, temp);
but, force_operand is far from handling all possible RTLs, it will ICE for
all more unusual RTL codes.  Basically handles just simple arithmetic and
unary RTL operations if they have an optab and
expand_simple_binop/expand_simple_unop ICE on others.

The following patch fixes it by adding some operand verification (whether
there is a hope that copy_to_mode_reg will succeed on those).  It is added
both to noce_emit_move_insn (not needed for this exact testcase,
that function simply tries to recog the insn as is and if it fails,
handles some simple binop/unop cases; the patch performs the verification
of their operands) and noce_try_sign_mask.

2021-02-03  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/97487
* ifcvt.c (noce_can_force_operand): New function.
(noce_emit_move_insn): Use it.
(noce_try_sign_mask): Likewise.  Formatting fix.

* gcc.dg/pr97487-1.c: New test.
* gcc.dg/pr97487-2.c: New test.

lra-constraints: Fix error-recovery for bad inline-asms [PR97971]

The following testcase has ice-on-invalid, it can't be reloaded, but we
shouldn't ICE the compiler because the user typed non-sense.

In current_insn_transform we have:
  if (process_alt_operands (reused_alternative_num))
    alt_p = true;

  if (check_only_p)
    return ! alt_p || best_losers != 0;

  /* If insn is commutative (it's safe to exchange a certain pair of
     operands) then we need to try each alternative twice, the second
     time matching those two operands as if we had exchanged them.  To
     do this, really exchange them in operands.

     If we have just tried the alternatives the second time, return
     operands to normal and drop through.  */

  if (reused_alternative_num < 0 && commutative >= 0)
    {
      curr_swapped = !curr_swapped;
      if (curr_swapped)
        {
          swap_operands (commutative);
          goto try_swapped;
        }
      else
        swap_operands (commutative);
    }

  if (! alt_p && ! sec_mem_p)
    {
      /* No alternative works with reloads??  */
      if (INSN_CODE (curr_insn) >= 0)
        fatal_insn ("unable to generate reloads for:", curr_insn);
      error_for_asm (curr_insn,
                     "inconsistent operand constraints in an %<asm%>");
      lra_asm_error_p = true;
...
and so handle inline asms there differently (and delete/nullify them after
this) - fatal_insn is only called for non-inline asm.
But in process_alt_operands we do:
                /* Both the earlyclobber operand and conflicting operand
                   cannot both be user defined hard registers.  */
                if (HARD_REGISTER_P (operand_reg[i])
                    && REG_USERVAR_P (operand_reg[i])
                    && operand_reg[j] != NULL_RTX
                    && HARD_REGISTER_P (operand_reg[j])
                    && REG_USERVAR_P (operand_reg[j]))
                  fatal_insn ("unable to generate reloads for "
                              "impossible constraints:", curr_insn);
and thus ICE even for inline-asms.

I think it is inappropriate to delete/nullify the insn in
process_alt_operands, as it could be done e.g. in the check_only_p mode,
so this patch just returns false in that case, which results in the
caller have alt_p false, and as inline asm isn't simple move, sec_mem_p
will be also false (and it isn't commutative either), so for check_only_p
it will suggests to the callers it isn't ok and otherwise will emit
error and delete/nullify the inline asm insn.

2021-02-03  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/97971
* lra-constraints.c (process_alt_operands): For inline asm, don't call
fatal_insn, but instead return false.

* gcc.target/i386/pr97971.c: New test.

i386: Remove V1DImode shift expanders [PR98287]

On Tue, Feb 02, 2021 at 02:23:55PM +0100, Richard Biener wrote:
> All I say is that the x86 target
> should either not advertise V1DF shifts or advertise the basic
> ops that reasonable simplification would expect to exist.

The backend has several V1?Imode shifts, but optab only for those V1DImode
ones:

grep '[la]sh[lr]v1[qhsdtox]' tmp-mddump.md
(define_insn ("mmx_ashlv1di3")
(define_insn ("mmx_lshrv1di3")
(define_insn ("avx512bw_ashlv1ti3")
(define_insn ("avx512bw_lshrv1ti3")
(define_insn ("sse2_ashlv1ti3")
(define_insn ("sse2_lshrv1ti3")
(define_expand ("ashlv1di3")
(define_expand ("lshrv1di3")
  emit_insn (gen_sse2_lshrv1ti3 (tmp, gen_lowpart (V1TImode, operands[1]),

I think it has been introduced with
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89021#c13

Before we didn't have any V1DImode expanders (except mov/movmisalign, but
those are needed and are supplied for other V1??mode modes too).

This patch just removes the two V1DImode shift expanders with standard names.

2021-02-03  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/98287
* config/i386/mmx.md (<insn><mode>3): For shifts don't enable expander
for V1DImode.

* gcc.dg/pr98287.c: New test.

slp: Split out patterns away from using SLP_ONLY into their own flag

Previously the SLP pattern matcher was using STMT_VINFO_SLP_VECT_ONLY as a way
to dissolve the SLP only patterns during SLP cancellation.  However it seems
like the semantics for STMT_VINFO_SLP_VECT_ONLY are slightly different than what
I expected.

Namely that the non-SLP path can still use a statement marked
STMT_VINFO_SLP_VECT_ONLY.  One such example is masked loads which are used both
in the SLP and non-SLP path.

To fix this I now introduce a new flag STMT_VINFO_SLP_VECT_ONLY_PATTERN which is
used only by the pattern matcher.

gcc/ChangeLog:

PR tree-optimization/98928
* tree-vect-loop.c (vect_analyze_loop_2): Change
STMT_VINFO_SLP_VECT_ONLY to STMT_VINFO_SLP_VECT_ONLY_PATTERN.
* tree-vect-slp-patterns.c (complex_pattern::build): Likewise.
* tree-vectorizer.h (STMT_VINFO_SLP_VECT_ONLY_PATTERN): New.
(class _stmt_vec_info): Add slp_vect_pattern_only_p.

gcc/testsuite/ChangeLog:

PR tree-optimization/98928
* gcc.target/i386/pr98928.c: New test.

Daily bump.

gotools: for "make check" run "go test embed/internal/embedtest"

* Makefile.am (check-embed): New target.
(check): Depend on check-embed.  Examine embed-testlog.
(mostlyclean-local): Add check-embed-dir.
(.PHONY): Add check-embed.
* Makefile.in: Regenerate.

fix memory leaks

This fixes various vec<> memory leaks as discovered compiling 521.wrf_r.

2021-02-02  Richard Biener  <rguenther@suse.de>

* gimple-loop-interchange.cc (prepare_data_references):
Release vectors.
* gimple-loop-jam.c (tree_loop_unroll_and_jam): Likewise.
* tree-ssa-loop-im.c (hoist_memory_references): Likewise.
* tree-vect-stmts.c (vectorizable_condition): Do not
allocate vectors.
(vectorizable_comparison): Likewise.

Add test-case.

gcc/testsuite/ChangeLog:

PR target/97510
* gcc.target/i386/pr97510.c: New test.

c++: Member fns and deduction guide rewriting [PR98929]

My patch for 96199 had us re-substitute the parameter types of a constructor
in order to rewrite mentions of members into dependent references.  We need
to do that for member functions, too.

gcc/cp/ChangeLog:

PR c++/98929
PR c++/96199
* error.c (dump_expr): Ignore dummy object.
* pt.c (tsubst_baselink): Handle dependent scope.

gcc/testsuite/ChangeLog:

PR c++/98929
* g++.dg/cpp1z/class-deduction-decltype1.C: New test.

aarch64: Reimplement vrsqrte* intrinsics with builtins

Another very simple move from inline asm to builtins.
Only two intrinsics this time.

gcc/ChangeLog:

* config/aarch64/aarch64-simd-builtins.def (ursqrte): Define builtin.
* config/aarch64/aarch64-simd.md (aarch64_ursqrte<mode>): New pattern.
* config/aarch64/arm_neon.h (vrsqrte_u32): Reimplement using builtin.
(vrsqrteq_u32): Likewise.

aarch64: Reimplement vqmovun_high* intrinsics using builtins

Another transition from inline asm to builtin.
Only 3 intrinsics converted this time but they use the "+w" constraint in their inline asm
so are more likely to generate redundant moves so benefit more from reimplementation.

gcc/ChangeLog:

* config/aarch64/aarch64-simd-builtins.def (sqxtun2): Define builtin.
* config/aarch64/aarch64-simd.md (aarch64_sqxtun2<mode>_le): Define.
(aarch64_sqxtun2<mode>_be): Likewise.
(aarch64_sqxtun2<mode>): Likewise.
* config/aarch64/arm_neon.h (vqmovun_high_s16): Reimplement using builtin.
(vqmovun_high_s32): Likewise.
(vqmovun_high_s64): Likewise.
* config/aarch64/iterators.md (UNSPEC_SQXTUN2): Define.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/narrow_high-intrinsics.c: Adjust sqxtun2 scan.

Fortran: Check remains fixed by patch for PRs 96100/101 [PR91862].

2021-02-02  Paul Thomas  <pault@gcc.gnu.org>

gcc/testsuite
PR fortran/91862
* gfortran.dg/pr91862.f90: New test.

aarch64: Update flags for bfloat16 builtins

This patch updates the flags for the bfloat16 builtins.
The bfdot ones aren't affected by the FPCR/FPSR so can be AUTO_FP
whereas the bfmlal ones follow the normal floating-point instructions and get FP.

gcc/ChangeLog:

* config/aarch64/aarch64-simd-builtins.def (bfdot_lane, bfdot_laneq): Use
AUTO_FP flags.
(bfmlalb_lane, bfmlalt_lane, bfmlalb_lane_q, bfmlalt_lane_q): Use FP flags.

aarch64: Relax flags for floating-point builtins to FP where appropriate

This patch relaxes various floating-point builtins to use the FP flags to signify they
made use the FPCR or raise exceptions.

gcc/ChangeLog:

* config/aarch64/aarch64-simd-builtins.def (fcmla_lane0, fcmla_lane90,
fcmla_lane180, fcmla_lane270, fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180,
fcmlaq_lane270, scvtf, ucvtf, fcvtzs, fcvtzu, scvtfsi, scvtfdi, ucvtfsi,
ucvtfdi, fcvtzshf, fcvtzuhf, fmlal_lane_low, fmlsl_lane_low,
fmlal_laneq_low, fmlsl_laneq_low, fmlalq_lane_low, fmlslq_lane_low,
fmlalq_laneq_low, fmlslq_laneq_low, fmlal_lane_high, fmlsl_lane_high,
fmlal_laneq_high, fmlsl_laneq_high, fmlalq_lane_high, fmlslq_lane_high,
fmlalq_laneq_high, fmlslq_laneq_high): Use FP flags.

aarch64: Add and use FLAG_LOAD in builtins

We already have a STORE flag that we use for builtins. This patch introduces a LOAD set
that uses AUTO_FP and FLAG_READ_MEMORY. This allows for more aggressive optimisation of the load
intrinsics.

Turns out we have a great many testcases that do:
float16x4x2_t
f_vld2_lane_f16 (float16_t * p, float16x4x2_t v)
{
  float16x4x2_t res;
  /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
  res = vld2_lane_f16 (p, v, 4);
  /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
  res = vld2_lane_f16 (p, v, -1);
  return res;
}

but since the first res is unused it now gets eliminated early on before we get to give an error
message. Ideally we'd like to warn for both.
This patch takes the conservative approach and doesn't convert the load-lane builtins to LOAD ;
that's something we can improve later.

gcc/ChangeLog:

* config/aarch64/aarch64-builtins.c (FLAG_LOAD): Define.
* config/aarch64/aarch64-simd-builtins.def (ld1x2, ld2, ld3, ld4, ld2r,
ld3r, ld4r, ld1, ld1x3, ld1x4): Use LOAD flags.

aarch64: Relax some builtins to AUTO_FP

This patch relaxes the flags for some builtins to AUTO_FP. These
builtins do permutes and similar, so they shouldn't get the FP flags
when operating on floating-point modes as they don't care about
FPCR/FPSR and exceptions.

gcc/ChangeLog:

* config/aarch64/aarch64-simd-builtins.def (combine, zip1, zip2,
uzp1, uzp2, trn1, trn2, simd_bsl): Use AUTO_FP flags.

aarch64: Relax builtin flags for integer builtins

This patch relaxes the flags for most integer builtins to NONE as they don't read/write memory
and don't care about the FPCR/FPSR or exceptions so we should be more aggressive with them.

This leads to fallout in a testcase where the result of an intrinsic was unused and it is now
DCE'd. The testcase is adjusted.

gcc/ChangeLog:

* config/aarch64/aarch64-simd-builtins.def (clrsb, clz, ctz, popcount,
vec_smult_lane_, vec_smlal_lane_, vec_smult_laneq_, vec_smlal_laneq_,
vec_umult_lane_, vec_umlal_lane_, vec_umult_laneq_, vec_umlal_laneq_,
ashl, sshl, ushl, srshl, urshl, sdot_lane, udot_lane, sdot_laneq,
udot_laneq, usdot_lane, usdot_laneq, sudot_lane, sudot_laneq, ashr,
ashr_simd, lshr, lshr_simd, srshr_n, urshr_n, ssra_n, usra_n, srsra_n,
ursra_n, sshll_n, ushll_n, sshll2_n, ushll2_n, ssri_n, usri_n, ssli_n,
ssli_n, usli_n, bswap, rbit, simd_bsl, eor3q, rax1q, xarq, bcaxq): Use
NONE builtin flags.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/arg-type-diagnostics-1.c: Return result from foo.

libstdc++: Fix markup for status tables in docs

libstdc++-v3/ChangeLog:

* doc/xml/manual/status_cxx2011.xml: Remove stray table cell.
* doc/xml/manual/status_cxx2014.xml: Likewise.
* doc/xml/manual/status_cxx2017.xml: Likewise.
* doc/html/manual/status.html: Regenerate.

tree-vect-patterns: Don't create over widening patterns for stmts used in reductions [PR98848]

As discussed in the PR, the reduction code isn't able to cope with type
promotions/demotions in the reduction computation, so if we recognize an
over-widening pattern that has vect_reduction_def type, we most likely make
it non-vectorizable.

2021-02-02  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/98848
* tree-vect-patterns.c (vect_recog_over_widening_pattern): Punt if
STMT_VINFO_DEF_TYPE (last_stmt_info) is vect_reduction_def.

* gcc.dg/vect/pr98848.c: New test.
* gcc.dg/vect/pr92205.c: Remove xfail.

testsuite: Add testcase for already fixed PR [PR97960]

This testcase has been fixed by
r11-5904-g4cf70c20cb10acd6fb1016611d05540728176b60
so I'm checking it in so that we can close the PR.

2021-02-02  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/97960
* g++.dg/torture/pr97960.C: New test.

PR target/98743: Fix ICE in convert_move for RISC-V

 - Check `from` mode is not BLMmode before call store_expr, calling store_expr
   with BLKmode will cause ICE.

 - Verified with riscv64, x86_64 and aarch64, no introduce new regression.

Note: Those logic was introduced by 3e60ddeb8220ed388819bb3f14e8caa9309fd3c2,
      so I cc Jakub for reivew.

Changes for V2:

 - Checking mode of `from` rather than mode of `to`.
 - Verified on riscv64, x86_64 and aarch64 again.

gcc/ChangeLog:

PR target/98743
* expr.c: Check mode before calling store_expr.

gcc/testsuite/ChangeLog:

PR target/98743
* g++.dg/opt/pr98743.C: New.

arm: Auto-vectorization for MVE: vorn

This patch enables MVE vornq instructions for auto-vectorization.  MVE
vornq insns in mve.md are modified to use ior instead of unspec
expression.

2021-02-01  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/
* config/arm/iterators.md (supf): Remove VORNQ_S and VORNQ_U.
(VORNQ): Remove.
* config/arm/mve.md (mve_vornq_s<mode>): New entry for vorn
instruction using expression ior.
(mve_vornq_u<mode>): New expander.
(mve_vornq_f<mode>): Use ior code instead of unspec.
* config/arm/unspecs.md (VORNQ_S, VORNQ_U, VORNQ_F): Remove.

gcc/testsuite/
* gcc.target/arm/simd/mve-vorn.c: Add vorn tests.

restore current_function_decl after re-gimplifying nested ADDR_EXPRs

Ada makes extensive use of nested functions, which turn all automatic
variables of the enclosing function that are used in nested ones into
members of an artificial FRAME record type.

The address of a local variable is usually passed to asan marking
functions without using a temporary.  asan_expand_mark_ifn will reject
an ADDR_EXPRs if it's split out from the call into an SSA_NAMEs.

Taking the address of a member of FRAME within a nested function was
not regarded as a gimple val: while introducing FRAME variables,
current_function_decl pointed to the outermost function, even while
processing a nested function, so decl_address_invariant_p, checking
that the context of the variable is current_function_decl, returned
false for such ADDR_EXPRs.

decl_address_invariant_p, called when determining whether an
expression is a legitimate gimple value, compares the context of
automatic variables with current_function_decl.  Some of the
tree-nested function processing doesn't set current_function_decl, but
ADDR_EXPR-processing bits temporarily override it.  However, they
restore it before re-gimplifying, which causes even ADDR_EXPRs
referencing automatic variables in the FRAME struct of a nested
function to not be regarded as address-invariant.

This patch moves the restores of current_function_decl in the
ADDR_EXPR-handling bits after the re-gimplification, so that the
correct current_function_decl is used when testing for address
invariance.

for  gcc/ChangeLog

* tree-nested.c (convert_nonlocal_reference_op): Move
current_function_decl restore after re-gimplification.
(convert_local_reference_op): Likewise.

for  gcc/testsuite/ChangeLog

* gcc.dg/asan/nested-1.c: New.

analyzer: directly explore within static functions [PR93355,PR96374]

PR analyzer/93355 tracks that -fanalyzer fails to report the FILE *
leak in read_alias_file in intl/localealias.c.

One reason for the failure is that read_alias_file is marked as
"static", and the path leading to the single call of
read_alias_file is falsely rejected as infeasible due to
PR analyzer/96374.  I have been attempting to fix that bug, but
don't have a good solution yet.

Previously, -fanalyzer only directly explored "static" functions
if they were needed for call summaries, instead forcing them to
be indirectly explored, but if we have a feasibility bug like
above, we will fail to report any issues in a function that's
only called by such a falsely infeasible path.

It now seems wrong to me to reject directly exploring static
functions: even if there is currently no way to call a function,
it seems reasonable to warn about bugs within them, since
otherwise these latent bugs are a timebomb in the code.

Hence this patch reworks toplevel_function_p to directly explore
almost all functions, working around these feasiblity issues.
It introduces a naming convention that "__analyzer_"-prefixed
function names don't get directly explored, since this is
useful in the analyzer's DejaGnu-based tests.

This workaround gets PR analyzer/93355 closer to working, but
unfortunately there is a second instance of PR analyzer/96374
within read_alias_file itself which means even with this patch
-fanalyzer falsely rejects the path as infeasible.

Still, this ought to help in other cases, and simplifies the
implementation.

gcc/analyzer/ChangeLog:
PR analyzer/93355
PR analyzer/96374
* engine.cc (toplevel_function_p): Simplify so that
we only reject functions with a "__analyzer_" prefix.
(add_any_callbacks): Delete.
(exploded_graph::build_initial_worklist): Update for
dropped param of toplevel_function_p.
(exploded_graph::build_initial_worklist): Don't bother
looking for callbacks that are reachable from global
initializers.

gcc/testsuite/ChangeLog:
PR analyzer/93355
PR analyzer/96374
* gcc.dg/analyzer/conditionals-3.c: Add "__analyzer_"
prefix to support subroutines where necessary.
* gcc.dg/analyzer/data-model-1.c: Likewise.
* gcc.dg/analyzer/feasibility-1.c (called_by_test_6a): New.
(test_6a): New.
* gcc.dg/analyzer/params.c: Add "__analyzer_" prefix to support
subroutines where necessary.
* gcc.dg/analyzer/pr96651-2.c: Likewise.
* gcc.dg/analyzer/signal-4b.c: Likewise.
* gcc.dg/analyzer/single-field.c: Likewise.
* gcc.dg/analyzer/torture/conditionals-2.c: Likewise.

analyzer: add more feasibility test cases [PR93355,PR96374]

This patch adds a couple more reduced test cases derived from the
integration test for PR analyzer/93355.  In both cases, the analyzer
falsely rejects the buggy code paths as being infeasible due to
PR analyzer/96374, and so the tests are marked as XFAIL for now.

gcc/testsuite/ChangeLog:
PR analyzer/93355
PR analyzer/96374
* gcc.dg/analyzer/pr93355-localealias-feasibility-2.c: New test.
* gcc.dg/analyzer/pr93355-localealias-feasibility-3.c: New test.

d: Fix junk in generated symbol on powerpc64-*-* [PR98921]

This adds a special formatter to OutBuffer to handle formatted printing
of integers, a common case.  The replacement is faster and safer.

In dmangle.c, it also gets rid of a number of problematic casts, as seen
on powerpc64 targets.

Reviewed-on: https://github.com/dlang/dmd/pull/12174

gcc/d/ChangeLog:

PR d/98921
* dmd/MERGE: Merge upstream dmd 5e2a81d9c.

Daily bump.

aarch64: Reimplement vrshrn* intrinsics using builtins

This patch moves the vrshrn* intrinsics to builtins away from inline
asm.

It's a bit of code, but it's very similar to the recent vsrhn*
reimplementation except that we use an unspec rather than standard RTL
codes for the functionality.

gcc/ChangeLog:

* config/aarch64/aarch64-simd-builtins.def (rshrn, rshrn2):
Define builtins.
* config/aarch64/aarch64-simd.md (aarch64_rshrn<mode>_insn_le):
Define.
(aarch64_rshrn<mode>_insn_be): Likewise.
(aarch64_rshrn<mode>): Likewise.
(aarch64_rshrn2<mode>_insn_le): Likewise.
(aarch64_rshrn2<mode>_insn_be): Likewise.
(aarch64_rshrn2<mode>): Likewise.
* config/aarch64/aarch64.md (unspec): Add UNSPEC_RSHRN.
* config/aarch64/arm_neon.h (vrshrn_high_n_s16): Reimplement
using builtin.
(vrshrn_high_n_s32): Likewise.
(vrshrn_high_n_s64): Likewise.
(vrshrn_high_n_u16): Likewise.
(vrshrn_high_n_u32): Likewise.
(vrshrn_high_n_u64): Likewise.
(vrshrn_n_s16): Likewise.
(vrshrn_n_s32): Likewise.
(vrshrn_n_s64): Likewise.
(vrshrn_n_u16): Likewise.
(vrshrn_n_u32): Likewise.
(vrshrn_n_u64): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/narrow_high-intrinsics.c: Adjust rshrn2
assembly scan.

analyzer: fix false positives with *UNKNOWN_PTR [PR98918]

PR analyzer/98918 reports various false positives and state explosions
on correct code that frees nodes and other pointers in a singly-linked
list.

The issue is that state-merger in the loop leads to UNKNOWN_VALUEs,
and these are then erroneously used to form compound symbolic values
and regions, such as;
  INIT_VAL((*UNKNOWN(struct marker *)).ref)
and:
  (*INIT_VAL((*UNKNOWN(struct marker * *))))
The malloc state machine then treats these symbolic values as
identifying specific pointers, and thus e.g. erroneously reports a
double-free when
  INIT_VAL((*UNKNOWN(struct marker *)).ref)
is freed twice (on subsequent iterations of the loop).

Similarly, the increasingly complex compound symbolic values have
sm-state which prevents state merging, and eventually lead to the
analysis hitting safety limits and stopping.

This patch makes various compound values involving UNKNOWN be
themselves UNKNOWN, resolving both the false positives and the state
explosions.

gcc/analyzer/ChangeLog:
PR analyzer/98918
* region-model-manager.cc
(region_model_manager::get_or_create_initial_value):
Fold the initial value of *UNKNOWN_PTR to an UNKNOWN value.
(region_model_manager::get_field_region): Fold the value
of UNKNOWN_PTR->FIELD to *UNKNOWN_PTR_OF_&FIELD_TYPE.

gcc/testsuite/ChangeLog:
PR analyzer/98918
* gcc.dg/analyzer/pr98918.c: New test.

libstdc++: Make deque iterator operator- usable with value-init iterators

N3644 implies that operator- can be used on value-init iterators. We now return
0 if both iterators are value initialized. If only one is value initialized we
keep the UB by returning the result of a normal computation which is a meaningless
value.

libstdc++-v3/ChangeLog:

PR libstdc++/70303
* include/bits/stl_deque.h (std::deque<>::operator-(iterator, iterator)):
Return 0 if both iterators are value-initialized.
* testsuite/23_containers/deque/70303.cc: New test.
* testsuite/23_containers/vector/70303.cc: New test.

tree-optimization/98499 - fix modref analysis on RVO statements

Before the change RVO gimple statements were treated as local
stores by modres analysis. But in practice RVO escapes target.

2021-02-01  Sergei Trofimovich  <siarheit@google.com>

gcc/ChangeLog:

PR tree-optimization/98499
* ipa-modref.c (analyze_ssa_name_flags): treat RVO
conservatively and assume all possible side-effects.

gcc/testsuite/ChangeLog:

PR tree-optimization/98499
* g++.dg/pr98499.C: new test.

aarch64: Reimplement vmovl_high_* intrinsics using builtins

The vmovl_high_* intrinsics map down to the SXTL2/UXTL2 instructions
that already have appropriately-named patterns and expanders,
so it's straightforward to wire them up.

gcc/ChangeLog:

* config/aarch64/aarch64-simd-builtins.def (vec_unpacks_hi,
vec_unpacku_hi_): Define builtins.
* config/aarch64/arm_neon.h (vmovl_high_s8): Reimplement using
builtin.
(vmovl_high_s16): Likewise.
(vmovl_high_s32): Likewise.
(vmovl_high_u8): Likewise.
(vmovl_high_u16): Likewise.
(vmovl_high_u32): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/simd/vmovl_high_1.c: New test.

aarch64: Reimplement vabdl_* intrinsics using builtins

Another simple set of intrinsic moved to builtins in the straightforward
way.

gcc/ChangeLog:

* config/aarch64/aarch64-simd-builtins.def (sabdl, uabdl):
Define builtins.
* config/aarch64/aarch64-simd.md (aarch64_<sur>abdl<mode>): New
pattern.
* config/aarch64/aarch64.md (unspec): Define UNSPEC_SABDL,
UNSPEC_UABDL.
* config/aarch64/arm_neon.h (vabdl_s8): Reimplemet using
builtin.
(vabdl_s16): Likewise.
(vabdl_s32): Likewise.
(vabdl_u8): Likewise.
(vabdl_u16): Likewise.
(vabdl_u32): Likewise.
* config/aarch64/iterators.md (ABDL): New int iterator.
(sur): Handle UNSPEC_SABDL, UNSPEC_UABDL.

Document various BLOCK macros.

gcc/ChangeLog:

* tree.h (BLOCK_VARS): Add comment.
(BLOCK_SUBBLOCKS): Same.
(BLOCK_SUPERCONTEXT): Same.
(BLOCK_ABSTRACT_ORIGIN): Same.
(inlined_function_outer_scope_p): Same.

Reset front end trees before they make it into the middle end (PR middle-end/97172).

gcc/ChangeLog:

PR middle-end/97172
* attribs.c (attr_access::free_lang_data): Define new function.
* attribs.h (attr_access::free_lang_data): Declare new function.

gcc/c/ChangeLog:

PR middle-end/97172
* c-decl.c (free_attr_access_data): New function.
(c_parse_final_cleanups): Call free_attr_access_data.

gcc/testsuite/ChangeLog:

PR middle-end/97172
* gcc.dg/pr97172.c: New test.

libstdc++: Update C++17 status table for <charconv>

libstdc++-v3/ChangeLog:

* doc/xml/manual/status_cxx2011.xml: Update std::call_once
status.
* doc/xml/manual/status_cxx2014.xml: Likewise.
* doc/xml/manual/status_cxx2017.xml: Likewise. Update
std::from_chars and std::to_chars status. Fix formatting.
* doc/html/manual/status.html: Regenerate.

Avoid -Wstringop-truncation.

libiberty/ChangeLog:

* dyn-string.c (dyn_string_insert_cstr): Use memcpy instead of strncpy
to avoid -Wstringop-truncation.