bugzilla-daemon [Wed, 3 Jun 2020 22:00:49 +0000 (22:00 +0000)]
[libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 19:21:58 +0000 (20:21 +0100)]
[libre-riscv-dev] regfile-to-function-unit connection taking shape
Tobias Platen [Wed, 3 Jun 2020 13:28:05 +0000 (15:28 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 03jun2020
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 12:50:07 +0000 (13:50 +0100)]
[libre-riscv-dev] daily kan-ban update 03jun2020
bugzilla-daemon [Wed, 3 Jun 2020 12:00:03 +0000 (12:00 +0000)]
[libre-riscv-dev] [Bug 361] New: all test_pipe_caller.py needs RA=0 tests
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 10:08:12 +0000 (11:08 +0100)]
[libre-riscv-dev] googleusercontent looks like it got hacked yesterday
bugzilla-daemon [Wed, 3 Jun 2020 03:27:01 +0000 (03:27 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 3 Jun 2020 02:31:04 +0000 (02:31 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 3 Jun 2020 01:50:05 +0000 (01:50 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 3 Jun 2020 01:41:06 +0000 (01:41 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 3 Jun 2020 01:35:18 +0000 (01:35 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 01:28:59 +0000 (02:28 +0100)]
Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt decoder tables: M-Form and X-Form switched RS and RB
bugzilla-daemon [Wed, 3 Jun 2020 01:28:01 +0000 (01:28 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 3 Jun 2020 01:13:32 +0000 (01:13 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 3 Jun 2020 00:47:10 +0000 (00:47 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Paul Mackerras [Wed, 3 Jun 2020 00:40:52 +0000 (10:40 +1000)]
Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt decoder tables: M-Form and X-Form switched RS and RB
bugzilla-daemon [Wed, 3 Jun 2020 00:38:12 +0000 (00:38 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 3 Jun 2020 00:11:03 +0000 (00:11 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Tue, 2 Jun 2020 23:59:16 +0000 (23:59 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Tue, 2 Jun 2020 23:54:24 +0000 (23:54 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Tue, 2 Jun 2020 23:46:44 +0000 (23:46 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 23:16:24 +0000 (00:16 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 02jun2020
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 23:07:36 +0000 (00:07 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 02jun2020
bugzilla-daemon [Tue, 2 Jun 2020 23:07:53 +0000 (23:07 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Tue, 2 Jun 2020 23:07:13 +0000 (23:07 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Tue, 2 Jun 2020 23:06:41 +0000 (23:06 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
Cole Poirier [Tue, 2 Jun 2020 23:06:01 +0000 (16:06 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 02jun2020
Cole Poirier [Tue, 2 Jun 2020 23:05:27 +0000 (16:05 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 01jun2020
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 23:03:51 +0000 (00:03 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 01jun2020
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 23:02:52 +0000 (00:02 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 02jun2020
Cole Poirier [Tue, 2 Jun 2020 22:48:26 +0000 (15:48 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 01jun2020
bugzilla-daemon [Tue, 2 Jun 2020 22:41:28 +0000 (22:41 +0000)]
[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9
Jacob Lifshay [Tue, 2 Jun 2020 22:35:28 +0000 (15:35 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 02jun2020
bugzilla-daemon [Tue, 2 Jun 2020 21:38:28 +0000 (21:38 +0000)]
[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9
bugzilla-daemon [Tue, 2 Jun 2020 21:33:55 +0000 (21:33 +0000)]
[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9
bugzilla-daemon [Tue, 2 Jun 2020 21:03:11 +0000 (21:03 +0000)]
[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9
bugzilla-daemon [Tue, 2 Jun 2020 20:30:58 +0000 (20:30 +0000)]
[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9
bugzilla-daemon [Tue, 2 Jun 2020 20:19:31 +0000 (20:19 +0000)]
[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9
bugzilla-daemon [Tue, 2 Jun 2020 20:11:58 +0000 (20:11 +0000)]
[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9
bugzilla-daemon [Tue, 2 Jun 2020 19:09:36 +0000 (19:09 +0000)]
[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9
bugzilla-daemon [Tue, 2 Jun 2020 18:43:44 +0000 (18:43 +0000)]
[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9
bugzilla-daemon [Tue, 2 Jun 2020 18:27:47 +0000 (18:27 +0000)]
[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9
bugzilla-daemon [Tue, 2 Jun 2020 18:26:16 +0000 (18:26 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Tue, 2 Jun 2020 17:54:29 +0000 (17:54 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 16:04:41 +0000 (17:04 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 02jun2020
Tobias Platen [Tue, 2 Jun 2020 15:43:33 +0000 (17:43 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 02jun2020
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 15:37:33 +0000 (16:37 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 02jun2020
Tobias Platen [Tue, 2 Jun 2020 15:03:18 +0000 (17:03 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 02jun2020
Tobias Platen [Tue, 2 Jun 2020 14:44:45 +0000 (16:44 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 02jun2020
bugzilla-daemon [Tue, 2 Jun 2020 14:06:17 +0000 (14:06 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Tue, 2 Jun 2020 12:27:24 +0000 (12:27 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 12:10:37 +0000 (13:10 +0100)]
Re: [libre-riscv-dev] microwatt decoder tables: M-Form and X-Form switched RS and RB
bugzilla-daemon [Tue, 2 Jun 2020 11:21:39 +0000 (11:21 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 10:48:08 +0000 (11:48 +0100)]
[libre-riscv-dev] daily kan-ban update 02jun2020
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 10:18:28 +0000 (11:18 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 01jun2020
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 10:11:11 +0000 (11:11 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 01jun2020
Jacob Lifshay [Tue, 2 Jun 2020 06:17:57 +0000 (23:17 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 01jun2020
Cole Poirier [Tue, 2 Jun 2020 00:22:56 +0000 (17:22 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 01jun2020
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 00:01:53 +0000 (01:01 +0100)]
Re: [libre-riscv-dev] microwatt decoder tables: M-Form and X-Form switched RS and RB
bugzilla-daemon [Mon, 1 Jun 2020 23:24:23 +0000 (23:24 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 1 Jun 2020 23:24:22 +0000 (23:24 +0000)]
[libre-riscv-dev] [Bug 358] new MCU-ALU test picked up RC / OE / CR handling issue
Paul Mackerras [Mon, 1 Jun 2020 23:13:11 +0000 (09:13 +1000)]
Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt decoder tables: M-Form and X-Form switched RS and RB
bugzilla-daemon [Mon, 1 Jun 2020 22:04:40 +0000 (22:04 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 1 Jun 2020 21:50:43 +0000 (21:50 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 1 Jun 2020 21:41:59 +0000 (21:41 +0000)]
[libre-riscv-dev] [Bug 360] move RS to 1st or 2nd operand in CSV files
bugzilla-daemon [Mon, 1 Jun 2020 20:39:26 +0000 (20:39 +0000)]
[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9
bugzilla-daemon [Mon, 1 Jun 2020 20:17:16 +0000 (20:17 +0000)]
[libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline
bugzilla-daemon [Mon, 1 Jun 2020 20:13:36 +0000 (20:13 +0000)]
[libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline
bugzilla-daemon [Mon, 1 Jun 2020 19:31:18 +0000 (19:31 +0000)]
[libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline
bugzilla-daemon [Mon, 1 Jun 2020 19:16:21 +0000 (19:16 +0000)]
[libre-riscv-dev] [Bug 300] Documentation for the SOC
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 19:05:16 +0000 (20:05 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 01jun2020
bugzilla-daemon [Mon, 1 Jun 2020 19:05:07 +0000 (19:05 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Cole Poirier [Mon, 1 Jun 2020 19:03:37 +0000 (12:03 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 01jun2020
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 19:02:03 +0000 (20:02 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 01jun2020
Michael Nolan [Mon, 1 Jun 2020 18:54:40 +0000 (14:54 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 01jun2020
bugzilla-daemon [Mon, 1 Jun 2020 18:35:38 +0000 (18:35 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 18:33:56 +0000 (19:33 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 01jun2020
Cole Poirier [Mon, 1 Jun 2020 18:30:05 +0000 (11:30 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 01jun2020
bugzilla-daemon [Mon, 1 Jun 2020 18:09:01 +0000 (18:09 +0000)]
[libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline
bugzilla-daemon [Mon, 1 Jun 2020 18:07:21 +0000 (18:07 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Mon, 1 Jun 2020 18:06:23 +0000 (18:06 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Mon, 1 Jun 2020 17:55:19 +0000 (17:55 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Mon, 1 Jun 2020 17:53:56 +0000 (17:53 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Mon, 1 Jun 2020 17:52:21 +0000 (17:52 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Mon, 1 Jun 2020 17:51:28 +0000 (17:51 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Mon, 1 Jun 2020 17:06:10 +0000 (17:06 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
Tobias Platen [Mon, 1 Jun 2020 16:20:35 +0000 (18:20 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 01jun2020
bugzilla-daemon [Mon, 1 Jun 2020 12:40:38 +0000 (12:40 +0000)]
[libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline
bugzilla-daemon [Mon, 1 Jun 2020 12:39:35 +0000 (12:39 +0000)]
[libre-riscv-dev] [Bug 360] New: move RS to 1st or 2nd operand in CSV files
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 12:20:45 +0000 (13:20 +0100)]
[libre-riscv-dev] microwatt decoder tables: M-Form and X-Form switched RS and RB
bugzilla-daemon [Mon, 1 Jun 2020 12:02:46 +0000 (12:02 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 1 Jun 2020 12:01:22 +0000 (12:01 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 1 Jun 2020 11:55:04 +0000 (11:55 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 1 Jun 2020 11:46:27 +0000 (11:46 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 1 Jun 2020 11:09:03 +0000 (11:09 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 10:40:36 +0000 (11:40 +0100)]
[libre-riscv-dev] daily kan-ban update 01jun2020
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 10:15:12 +0000 (11:15 +0100)]
Re: [libre-riscv-dev] Named Records in nMigen
Jock Tanner [Mon, 1 Jun 2020 07:17:33 +0000 (17:17 +1000)]
Re: [libre-riscv-dev] Named Records in nMigen
Yehowshua [Mon, 1 Jun 2020 06:33:53 +0000 (02:33 -0400)]
Re: [libre-riscv-dev] Named Records in nMigen
Yehowshua [Mon, 1 Jun 2020 06:29:44 +0000 (02:29 -0400)]
[libre-riscv-dev] Named Records in nMigen
projects / libre-riscv-dev.git / log