yosys.git
3 years agoMerge pull request #2295 from epfl-vlsc/firrtl_blackbox_generic_parameters
Miodrag Milanović [Tue, 24 Nov 2020 06:50:17 +0000 (07:50 +0100)]
Merge pull request #2295 from epfl-vlsc/firrtl_blackbox_generic_parameters

Add firrtl backend support for generic parameters in blackbox components

3 years agoFormatting fixes
Sahand Kashani [Mon, 23 Nov 2020 09:43:59 +0000 (10:43 +0100)]
Formatting fixes

3 years agoBump version
Yosys Bot [Sat, 21 Nov 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2443 from YosysHQ/dave/nexus-mult-infer
Miodrag Milanović [Fri, 20 Nov 2020 09:30:56 +0000 (10:30 +0100)]
Merge pull request #2443 from YosysHQ/dave/nexus-mult-infer

nexus: Multiplier inference support

3 years agonexus: DSP inference support
David Shah [Fri, 20 Nov 2020 08:26:58 +0000 (08:26 +0000)]
nexus: DSP inference support

Signed-off-by: David Shah <dave@ds0.me>
3 years agoBump version
Yosys Bot [Thu, 19 Nov 2020 00:10:10 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2441 from YosysHQ/dave/nexus_dsp_sim
Miodrag Milanović [Wed, 18 Nov 2020 11:22:05 +0000 (12:22 +0100)]
Merge pull request #2441 from YosysHQ/dave/nexus_dsp_sim

nexus: Add DSP simulation model

3 years agonexus: Add DSP simulation model
David Shah [Tue, 17 Nov 2020 11:56:18 +0000 (11:56 +0000)]
nexus: Add DSP simulation model

Signed-off-by: David Shah <dave@ds0.me>
3 years agoFix duplicated parameter name typo
Miodrag Milanovic [Wed, 18 Nov 2020 09:03:57 +0000 (10:03 +0100)]
Fix duplicated parameter name typo

3 years agoBump version
Yosys Bot [Tue, 17 Nov 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

3 years agobackends/blif: Remove unused vector of strings (#2420)
William Woodruff [Mon, 16 Nov 2020 08:31:48 +0000 (03:31 -0500)]
backends/blif: Remove unused vector of strings (#2420)

* backends/blif: Remove unused vector of strings

For reasons that are unclear to me, this was being used to store every
result of `cstr` before returning them. The vector was never accessed otherwise,
resulting in a huge unnecessary memory sink when emitting to BLIF.

* backends/blif: Remove CSTR macro

* backends/blif: Actually call str()

3 years agoMerge pull request #2438 from kbeckmann/gowin_rpll
Miodrag Milanović [Mon, 16 Nov 2020 08:30:54 +0000 (09:30 +0100)]
Merge pull request #2438 from kbeckmann/gowin_rpll

synth_gowin: Add rPLL blackbox

3 years agosynth_gowin: Add rPLL blackbox
Konrad Beckmann [Wed, 11 Nov 2020 16:01:50 +0000 (17:01 +0100)]
synth_gowin: Add rPLL blackbox

3 years agoBump version
Yosys Bot [Wed, 11 Nov 2020 00:10:17 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2433 from YosysHQ/paths_as_globals
Miodrag Milanović [Tue, 10 Nov 2020 07:05:42 +0000 (08:05 +0100)]
Merge pull request #2433 from YosysHQ/paths_as_globals

Expose abc and data paths as globals for pyosys

3 years agoBump version
Yosys Bot [Sun, 8 Nov 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2414 from zeldin/abc-depend-clang-fix
whitequark [Sat, 7 Nov 2020 18:48:03 +0000 (18:48 +0000)]
Merge pull request #2414 from zeldin/abc-depend-clang-fix

Prevent CXXFLAGS from leaking to abc Makefile

3 years agoPrevent CXXFLAGS from leaking to abc Makefile
Marcus Comstedt [Tue, 27 Oct 2020 13:04:28 +0000 (14:04 +0100)]
Prevent CXXFLAGS from leaking to abc Makefile

This fixes an issue with abc/depends.sh when the compiler is clang.

3 years agoMerge pull request #2432 from Xiretza/nexus-tests
Miodrag Milanović [Sat, 7 Nov 2020 14:07:45 +0000 (15:07 +0100)]
Merge pull request #2432 from Xiretza/nexus-tests

Update nexus arch tests to new harness

3 years agoExpose abc and data paths as globals
Miodrag Milanovic [Fri, 6 Nov 2020 13:17:15 +0000 (14:17 +0100)]
Expose abc and data paths as globals

3 years agoBump version
Yosys Bot [Tue, 3 Nov 2020 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2426 from whitequark/cxxrtl-auto-top
whitequark [Mon, 2 Nov 2020 20:58:10 +0000 (20:58 +0000)]
Merge pull request #2426 from whitequark/cxxrtl-auto-top

cxxrtl: run `hierarchy -auto-top` if no top module is present

3 years agocxxrtl: run `hierarchy -auto-top` if no top module is present.
whitequark [Mon, 2 Nov 2020 19:18:56 +0000 (19:18 +0000)]
cxxrtl: run `hierarchy -auto-top` if no top module is present.

In most cases, a CXXRTL simulation would use a top module, either
because this module serves as an entry point to the CXXRTL C API,
or because the outputs of a top module are unbuffered, improving
performance. Taking this into account, the CXXRTL backend now runs
`hierarchy -auto-top` if there is no top module. For the few cases
where this behavior is unwanted, it now accepts a `-nohierarchy`
option.

Fixes #2373.

3 years agoBump version
Yosys Bot [Mon, 2 Nov 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2425 from whitequark/cxxrtl-meminit-constness
whitequark [Sun, 1 Nov 2020 17:08:42 +0000 (17:08 +0000)]
Merge pull request #2425 from whitequark/cxxrtl-meminit-constness

cxxrtl: don't assert on non-constant $meminit inputs

3 years agocxxrtl: don't assert on non-constant $meminit inputs.
whitequark [Sun, 1 Nov 2020 15:25:55 +0000 (15:25 +0000)]
cxxrtl: don't assert on non-constant $meminit inputs.

Fixes #2129.

3 years agoMerge pull request #2424 from whitequark/cxxrtl-multiple-drivers
whitequark [Sun, 1 Nov 2020 13:52:59 +0000 (13:52 +0000)]
Merge pull request #2424 from whitequark/cxxrtl-multiple-drivers

cxxrtl: don't assert on wires with multiple drivers

3 years agocxxrtl: don't assert on wires with multiple drivers.
whitequark [Sun, 1 Nov 2020 12:49:20 +0000 (12:49 +0000)]
cxxrtl: don't assert on wires with multiple drivers.

Fixes #2374.

3 years agoBump version
Yosys Bot [Sun, 1 Nov 2020 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2416 from QuantamHD/master
whitequark [Sat, 31 Oct 2020 07:59:44 +0000 (07:59 +0000)]
Merge pull request #2416 from QuantamHD/master

Adds support for defining abc location at runtime

3 years agoBump version
Yosys Bot [Sat, 31 Oct 2020 00:10:15 +0000 (00:10 +0000)]
Bump version

3 years agoUpdate verific version
Miodrag Milanovic [Fri, 30 Oct 2020 07:32:59 +0000 (08:32 +0100)]
Update verific version

3 years agoUpdate nexus arch tests to new harness
Xiretza [Thu, 29 Oct 2020 13:42:07 +0000 (14:42 +0100)]
Update nexus arch tests to new harness

3 years agoThis patch adds support for defining the ABC location at runtime instead of at compil...
Ethan Mahintorabi [Thu, 29 Oct 2020 01:59:59 +0000 (18:59 -0700)]
This patch adds support for defining the ABC location at runtime instead of at compile time. This is helpful in build systems like bazel which do not have stable locations for binaries or directories during the compilation phase.

This change should be backwards compatible with the existing behavior.

3 years agoBump version
Yosys Bot [Sun, 25 Oct 2020 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoxilinx: Fix attributes_test.ys
Marcelina Kościelnicka [Fri, 23 Oct 2020 17:04:00 +0000 (19:04 +0200)]
xilinx: Fix attributes_test.ys

This test pretty much passes by accident — the `prep` command runs
memory_collect without memory_dff first, which prevents merging read
register into the memory, and thus blocks block RAM inference for a
reason completely unrelated to the attribute.

The attribute setting didn't actually work because it was set on the
containing module instead of the actual memory.

3 years agoBump version
Yosys Bot [Fri, 23 Oct 2020 00:10:07 +0000 (00:10 +0000)]
Bump version

3 years agonexus: Add make_transp to BRAMs
David Shah [Thu, 22 Oct 2020 14:11:59 +0000 (15:11 +0100)]
nexus: Add make_transp to BRAMs

Signed-off-by: David Shah <dave@ds0.me>
3 years agoMerge pull request #2403 from nakengelhardt/sim_timescale
N. Engelhardt [Thu, 22 Oct 2020 12:01:24 +0000 (14:01 +0200)]
Merge pull request #2403 from nakengelhardt/sim_timescale

sim -vcd: add date, version, and option for timescale

3 years agomemory_dff: Fix needlessly duplicating enable bits.
Marcelina Kościelnicka [Thu, 22 Oct 2020 08:37:44 +0000 (10:37 +0200)]
memory_dff: Fix needlessly duplicating enable bits.

When the register being merged into the EN signal happens to be a $sdff,
the current code creates a new $mux for every bit, even if they happen
to be identical (as is usually the case), preventing proper grouping
further down the flow.  Fix this by adding a simple cache.

Fixes #2409.

3 years agoBump version
Yosys Bot [Thu, 22 Oct 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

3 years agobtor: Use Mem helper.
Marcelina Kościelnicka [Sun, 18 Oct 2020 01:28:36 +0000 (03:28 +0200)]
btor: Use Mem helper.

3 years agosmt2: Use Mem helper.
Marcelina Kościelnicka [Sun, 18 Oct 2020 01:09:45 +0000 (03:09 +0200)]
smt2: Use Mem helper.

3 years agoverilog_backend: Use Mem helper.
Marcelina Kościelnicka [Sat, 17 Oct 2020 19:48:38 +0000 (21:48 +0200)]
verilog_backend: Use Mem helper.

3 years agosim: Use Mem helper.
Marcelina Kościelnicka [Sat, 17 Oct 2020 13:49:36 +0000 (15:49 +0200)]
sim: Use Mem helper.

3 years agoclk2fflogic: Use Mem helper.
Marcelina Kościelnicka [Fri, 16 Oct 2020 23:39:22 +0000 (01:39 +0200)]
clk2fflogic: Use Mem helper.

3 years agoopt_mem: Use Mem helpers.
Marcelina Kościelnicka [Sat, 17 Oct 2020 20:21:05 +0000 (22:21 +0200)]
opt_mem: Use Mem helpers.

3 years agomemory_bram: Use Mem helpers.
Marcelina Kościelnicka [Sat, 17 Oct 2020 20:20:55 +0000 (22:20 +0200)]
memory_bram: Use Mem helpers.

3 years agomemory_map: Use Mem helpers.
Marcelina Kościelnicka [Sat, 17 Oct 2020 20:20:32 +0000 (22:20 +0200)]
memory_map: Use Mem helpers.

3 years agomemory_unpack: Use Mem helpers.
Marcelina Kościelnicka [Sat, 17 Oct 2020 20:20:47 +0000 (22:20 +0200)]
memory_unpack: Use Mem helpers.

3 years agomemory_collect: Use Mem helpers.
Marcelina Kościelnicka [Sat, 17 Oct 2020 20:20:24 +0000 (22:20 +0200)]
memory_collect: Use Mem helpers.

3 years agomemory_nordff: Use Mem helpers.
Marcelina Kościelnicka [Sat, 17 Oct 2020 20:20:16 +0000 (22:20 +0200)]
memory_nordff: Use Mem helpers.

3 years agoAdd new helper structures to represent memories.
Marcelina Kościelnicka [Sat, 17 Oct 2020 20:19:34 +0000 (22:19 +0200)]
Add new helper structures to represent memories.

3 years agouse strftime instead of put_time for gcc 4.8 compatibility
N. Engelhardt [Wed, 21 Oct 2020 15:47:00 +0000 (17:47 +0200)]
use strftime instead of put_time for gcc 4.8 compatibility

3 years agoBump version
Yosys Bot [Wed, 21 Oct 2020 00:10:07 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2405 from byuccl/fix_xilinx_cells
clairexen [Tue, 20 Oct 2020 15:11:36 +0000 (17:11 +0200)]
Merge pull request #2405 from byuccl/fix_xilinx_cells

xilinx/cells_sim.v: Move signal declaration to before first use

3 years agoMerge pull request #2404 from YosysHQ/claire/fixrpcargs
clairexen [Tue, 20 Oct 2020 09:32:35 +0000 (11:32 +0200)]
Merge pull request #2404 from YosysHQ/claire/fixrpcargs

Fix argument handling in connect_rpc

3 years agoBump version
Yosys Bot [Tue, 20 Oct 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

3 years agoMove signal declarations to before first use
Jeff Goeders [Mon, 19 Oct 2020 22:09:04 +0000 (16:09 -0600)]
Move signal declarations to before first use

Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
3 years agoFix argument handling in connect_rpc
Claire Xenia Wolf [Mon, 19 Oct 2020 11:40:57 +0000 (13:40 +0200)]
Fix argument handling in connect_rpc

Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
3 years agoMerge pull request #2397 from daveshah1/nexus
Miodrag Milanović [Mon, 19 Oct 2020 09:20:56 +0000 (11:20 +0200)]
Merge pull request #2397 from daveshah1/nexus

synth_nexus: Initial implementation

3 years agowild guessing at the problem because it builds fine on my machines
N. Engelhardt [Fri, 16 Oct 2020 16:46:59 +0000 (18:46 +0200)]
wild guessing at the problem because it builds fine on my machines

3 years agosim -vcd: add date, version, and option for timescale
N. Engelhardt [Fri, 16 Oct 2020 16:19:58 +0000 (18:19 +0200)]
sim -vcd: add date, version, and option for timescale

3 years agoBump version
Yosys Bot [Fri, 16 Oct 2020 00:10:07 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2398 from jakobwenzel/smtbmc-escape
clairexen [Thu, 15 Oct 2020 16:08:59 +0000 (18:08 +0200)]
Merge pull request #2398 from jakobwenzel/smtbmc-escape

smtbmc: escape identifiers in verilog testbench

3 years agosynth_nexus: Initial implementation
David Shah [Thu, 1 Oct 2020 10:15:54 +0000 (11:15 +0100)]
synth_nexus: Initial implementation

Signed-off-by: David Shah <dave@ds0.me>
3 years agoBump version
Yosys Bot [Tue, 13 Oct 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

3 years agoextend verific library API for formal apps and generators
Miodrag Milanovic [Mon, 12 Oct 2020 12:56:15 +0000 (14:56 +0200)]
extend verific library API for formal apps and generators

3 years agoBump version
Yosys Bot [Fri, 9 Oct 2020 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoopt_clean: Better memory handling.
Marcelina Kościelnicka [Thu, 8 Oct 2020 11:33:47 +0000 (13:33 +0200)]
opt_clean: Better memory handling.

Previously, `$memwr` and `$meminit` cells were always preserved (along
with the memory itself).  With this change, they are instead part of the
main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr`
cells) is only preserved iff any associated `$memrd` cell needs to be
preserved.

3 years agosmtbmc: escape identifiers in verilog testbench
Jakob Wenzel [Tue, 6 Oct 2020 09:24:29 +0000 (11:24 +0200)]
smtbmc: escape identifiers in verilog testbench

3 years agoBump version
Yosys Bot [Tue, 6 Oct 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

3 years agoUpdate required Verific version
Miodrag Milanović [Mon, 5 Oct 2020 11:27:27 +0000 (13:27 +0200)]
Update required Verific version

3 years agoBump version
Yosys Bot [Sat, 3 Oct 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2396 from YosysHQ/claire/empty-param
clairexen [Fri, 2 Oct 2020 08:16:23 +0000 (10:16 +0200)]
Merge pull request #2396 from YosysHQ/claire/empty-param

Ignore empty parameters in Verilog module instantiations

3 years agoBump version
Yosys Bot [Fri, 2 Oct 2020 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoIgnore empty parameters in Verilog module instantiations
Claire Xenia Wolf [Thu, 1 Oct 2020 16:26:53 +0000 (18:26 +0200)]
Ignore empty parameters in Verilog module instantiations

Fixes #2394

Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
3 years agoMerge pull request #2378 from udif/pr_dollar_high_low
clairexen [Thu, 1 Oct 2020 16:17:36 +0000 (18:17 +0200)]
Merge pull request #2378 from udif/pr_dollar_high_low

Added $high(), $low(), $left(), $right()

3 years agoMerge pull request #2380 from Xiretza/parallel-tests
clairexen [Thu, 1 Oct 2020 16:12:31 +0000 (18:12 +0200)]
Merge pull request #2380 from Xiretza/parallel-tests

Clean up and parallelize testsuite

3 years agoUpdate .gitignore
David Shah [Thu, 1 Oct 2020 14:53:14 +0000 (15:53 +0100)]
Update .gitignore

Signed-off-by: David Shah <dave@ds0.me>
3 years agoMerge pull request #2395 from YosysHQ/sha1_if_contain_spaces
clairexen [Thu, 1 Oct 2020 12:32:43 +0000 (14:32 +0200)]
Merge pull request #2395 from YosysHQ/sha1_if_contain_spaces

Use sha1 for parameter list in case if they contain spaces

3 years agoBump version
Yosys Bot [Thu, 1 Oct 2020 00:10:08 +0000 (00:10 +0000)]
Bump version

3 years agouse sha1 for parameter list in case if they contain spaces
Miodrag Milanovic [Wed, 30 Sep 2020 07:16:59 +0000 (09:16 +0200)]
use sha1 for parameter list in case if they contain spaces

3 years agoFixed installation dir override for Python scripts
Miodrag Milanovic [Wed, 30 Sep 2020 05:47:36 +0000 (07:47 +0200)]
Fixed installation dir override for Python scripts

3 years agoBump version
Yosys Bot [Wed, 30 Sep 2020 00:10:09 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2393 from nakengelhardt/no_const_sensitivity
clairexen [Tue, 29 Sep 2020 15:31:01 +0000 (17:31 +0200)]
Merge pull request #2393 from nakengelhardt/no_const_sensitivity

write_verilog: emit intermediate wire for constant values in sensitivity list

3 years agoMerge pull request #2392 from YosysHQ/mmicko/hierarchy_fix
clairexen [Tue, 29 Sep 2020 15:21:08 +0000 (17:21 +0200)]
Merge pull request #2392 from YosysHQ/mmicko/hierarchy_fix

Validate parameters only when they are used

3 years agoBump version
Yosys Bot [Tue, 29 Sep 2020 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoadd tests
N. Engelhardt [Mon, 28 Sep 2020 16:12:40 +0000 (18:12 +0200)]
add tests

3 years agowrite_verilog: emit intermediate wire for constant values in sensitivity list
N. Engelhardt [Mon, 28 Sep 2020 16:11:18 +0000 (18:11 +0200)]
write_verilog: emit intermediate wire for constant values in sensitivity list

3 years agoMerge pull request #2386 from btut/fix/pyinstallpath
Miodrag Milanović [Mon, 28 Sep 2020 10:54:38 +0000 (12:54 +0200)]
Merge pull request #2386 from btut/fix/pyinstallpath

Fixed python installation path

3 years agoMerge pull request #2387 from btut/fix/pythonWrappersCXXFlags
N. Engelhardt [Mon, 28 Sep 2020 10:45:52 +0000 (12:45 +0200)]
Merge pull request #2387 from btut/fix/pythonWrappersCXXFlags

Use CXXFLAGS to enable pyosys specific code before generating wrappers

3 years agotests: add gitignores for auto-generated makefiles
Xiretza [Sat, 26 Sep 2020 14:27:37 +0000 (16:27 +0200)]
tests: add gitignores for auto-generated makefiles

3 years agoUse CXXFLAGS to enable pyosys specific code before generating wrappers
Benedikt Tutzer [Fri, 25 Sep 2020 10:57:46 +0000 (12:57 +0200)]
Use CXXFLAGS to enable pyosys specific code before generating wrappers

The .pyh files were generated without the CXXFLAGS. This meant that code
marked by the WITH_PYTHON flag was excluded. This is fixed by adding the
flag in the rule for .pyh files.

3 years agoValidate parameters only when they are used
Miodrag Milanovic [Fri, 25 Sep 2020 09:40:37 +0000 (11:40 +0200)]
Validate parameters only when they are used

3 years agoFixed python installation path
Benedikt Tutzer [Fri, 25 Sep 2020 09:21:16 +0000 (11:21 +0200)]
Fixed python installation path

The path where python expects it's libraries seems to change from
operating system to operating system, but can be querried from the site
package.

3 years agoBump version
Yosys Bot [Thu, 24 Sep 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

3 years ago xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)
Eddie Hung [Wed, 23 Sep 2020 16:15:24 +0000 (09:15 -0700)]
 xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)

* xilinx: eliminate SCCs from DSP48E1 model

* xilinx: add SCC test for DSP48E1

* Update techlibs/xilinx/cells_sim.v

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled

3 years agoMerge pull request #2384 from nakengelhardt/fix_2383
Miodrag Milanović [Wed, 23 Sep 2020 11:04:54 +0000 (13:04 +0200)]
Merge pull request #2384 from nakengelhardt/fix_2383

switch argument order to work with macOS getopt

3 years agoswitch argument order to work with macOS getopt
N. Engelhardt [Wed, 23 Sep 2020 10:48:26 +0000 (12:48 +0200)]
switch argument order to work with macOS getopt