Gabriel Somlo [Thu, 19 Mar 2020 23:13:47 +0000 (19:13 -0400)]
targets/nexys4ddr: add '--with-spi-sdcard' build option
Gabriel Somlo [Thu, 19 Mar 2020 22:04:27 +0000 (18:04 -0400)]
platforms/nexys4ddr: add spisdcard pins.
Synchronize with litex-boards commit #
57bcadb.
Gabriel Somlo [Thu, 19 Mar 2020 22:20:30 +0000 (18:20 -0400)]
targets/nexys4ddr: make sdcard reset conditional
Gabriel Somlo [Fri, 20 Mar 2020 01:50:54 +0000 (21:50 -0400)]
software/libbase/spisdcard: fix 4-byte FAT fields on 64-bit CPUs
On 64-bit architectures (e.g., Rocket), 'unsigned long' means
eight (not four) bytes. Use 'unsigned int' wherever a FAT data
structure requires a four-byte field!
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Gabriel Somlo [Thu, 19 Mar 2020 23:36:24 +0000 (19:36 -0400)]
bios: make SPI SDCard boot configs other than linux-on-litex-vexriscv
When NOT on linux-on-litex-vexriscv, we load 'boot.bin' to MAIN_RAM_BASE,
and jump to it.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Gabriel Somlo [Thu, 19 Mar 2020 23:24:22 +0000 (19:24 -0400)]
bios/boot.c: cosmetic: re-indent spisdcardboot() for consistency
enjoy-digital [Thu, 19 Mar 2020 21:10:33 +0000 (22:10 +0100)]
Merge pull request #431 from antmicro/hybrid-mac
litex_sim: add support for hybrid mac
Florent Kermarrec [Thu, 19 Mar 2020 10:02:15 +0000 (11:02 +0100)]
software/libbase/bios: rename spi.c/h to spisdcard.h, also rename functions.
Florent Kermarrec [Thu, 19 Mar 2020 09:47:28 +0000 (10:47 +0100)]
software/bios/main: revert USDDRPHY_DEBUG (merge issue with SPI SD CARD PR).
enjoy-digital [Thu, 19 Mar 2020 09:41:09 +0000 (10:41 +0100)]
Merge pull request #429 from rob-ng15/master
SPI hardware bitbanging from SD CARD
Piotr Binkowski [Fri, 13 Mar 2020 14:34:44 +0000 (15:34 +0100)]
litex_sim: add support for hybrid mac
enjoy-digital [Thu, 19 Mar 2020 08:05:02 +0000 (09:05 +0100)]
Merge pull request #430 from gsomlo/gls-sdclk-stub
bios/sdcard: provide sdclk_set_clk() stub for clocker-less targets
Gabriel Somlo [Sat, 14 Mar 2020 19:54:07 +0000 (15:54 -0400)]
bios/sdcard: provide sdclk_set_clk() stub for clocker-less targets
Targets which lack an adjustable clocker will not expose the required
registers. Provide a stub sdclk_set_clk() routine for those situations.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Florent Kermarrec [Wed, 18 Mar 2020 18:05:54 +0000 (19:05 +0100)]
platforms/kcu105: fix pcie tx0 p/n swap.
rob-ng15 [Tue, 17 Mar 2020 09:51:11 +0000 (09:51 +0000)]
SPI hardware bitbanging from SD CARD
rob-ng15 [Tue, 17 Mar 2020 09:50:45 +0000 (09:50 +0000)]
SPI hardware bitbanging from SD CARD
rob-ng15 [Tue, 17 Mar 2020 09:50:16 +0000 (09:50 +0000)]
SPI hardware bitbanging from SD CARD
Florent Kermarrec [Mon, 16 Mar 2020 10:44:39 +0000 (11:44 +0100)]
soc/cores/clock: make sure specific clkoutn_divide_range is only used as a fallback solution.
Sean Cross [Sat, 14 Mar 2020 10:08:24 +0000 (18:08 +0800)]
Merge pull request #425 from esden/csr-cod-split-reg
Make CSR documentation diagrams, with more than 8 bits, be split into multiple lanes.
Piotr Esden-Tempski [Fri, 13 Mar 2020 21:24:27 +0000 (14:24 -0700)]
Add bit more logic to decide when to switch to multilane CSR documentation.
Now we only generate multilane bitfield documentation when the CSR has
fields, and the smallest field is less than 8bit long. As this is when
we start running into space problems with the field names.
Piotr Esden-Tempski [Fri, 13 Mar 2020 05:08:54 +0000 (22:08 -0700)]
Split CSR documentation diagrams with more than 8 bits into multiple lanes.
In cases when each CSR bit has a name and we use CSR with more than 8
bits, the register diagram quickly becomes crowded and hard to read.
With this patch we split the register into multiple lanes of 8 bits
each.
enjoy-digital [Fri, 13 Mar 2020 17:06:23 +0000 (18:06 +0100)]
Merge pull request #427 from enjoy-digital/s7mmcm_fractional_divide
cores/clock: simplify Fractional Divide support on S7MMCM.
Florent Kermarrec [Fri, 13 Mar 2020 14:51:18 +0000 (15:51 +0100)]
cores/clock: simplify Fractional Divide support on S7MMCM.
Specific clkoutn_divide_range can now be provided by specialized XilinxClocking classes.
When provided, the specific range will be used. Floats are also now supported in the
range definition/iteration.
enjoy-digital [Fri, 13 Mar 2020 13:15:24 +0000 (14:15 +0100)]
Merge pull request #421 from betrusted-io/clk0_fractional
add fractional division options to clk0 config on PLL
Florent Kermarrec [Fri, 13 Mar 2020 11:24:36 +0000 (12:24 +0100)]
test: add initial (minimal) test for clock abstraction modules.
Also fix divclk_divide_range on S6DCM.
Florent Kermarrec [Fri, 13 Mar 2020 08:37:23 +0000 (09:37 +0100)]
targets/icebreaker: add description of the board, link to crowdsupply campagin and to the more complete example.
Sean Cross [Fri, 13 Mar 2020 05:44:13 +0000 (13:44 +0800)]
Merge pull request #426 from esden/update-wavedrom
Updating the vendored wavedrom js files.
Piotr Esden-Tempski [Fri, 13 Mar 2020 05:35:04 +0000 (22:35 -0700)]
Updating the vendored wavedrom js files.
Florent Kermarrec [Thu, 12 Mar 2020 11:20:48 +0000 (12:20 +0100)]
soc/intergration: rename mr_memory_x parameter to memory_x.
enjoy-digital [Thu, 12 Mar 2020 11:12:48 +0000 (12:12 +0100)]
Merge pull request #424 from esden/generate-memory-x
Add --mr-memory-x parameter to generate memory regions memory.x file
Piotr Esden-Tempski [Thu, 12 Mar 2020 01:07:33 +0000 (18:07 -0700)]
Add --mr-memory-x parameter to generate memory regions memory.x file.
This file is used by rust embedded target pacs.
Florent Kermarrec [Wed, 11 Mar 2020 11:57:29 +0000 (12:57 +0100)]
Merge branch 'master' of github.com/enjoy-digital/litex
Florent Kermarrec [Wed, 11 Mar 2020 11:56:40 +0000 (12:56 +0100)]
software: revert LTO changes (Disable it).
It seems LTO is not yet fully working with all configurations, so it's better
reverting the changes for now.
- cause issues with LM32 available compilers.
- seems to cause issues with min/lite variant of VexRiscv.
- seems to cause issues with some litex-buildenv configurations. (see https://github.com/enjoy-digital/litex/issues/417).
Sean Cross [Wed, 11 Mar 2020 11:38:42 +0000 (19:38 +0800)]
Merge pull request #422 from xobs/core-doc-fixes
Core doc fixes
enjoy-digital [Wed, 11 Mar 2020 11:33:50 +0000 (12:33 +0100)]
Merge pull request #423 from gsomlo/gls-ethmac-fixes
integration/soc: add_ethernet: honor self.map["ethmac"], if present
Florent Kermarrec [Wed, 11 Mar 2020 11:06:15 +0000 (12:06 +0100)]
cores/gpio: add CSR descriptions.
Florent Kermarrec [Wed, 11 Mar 2020 10:04:42 +0000 (11:04 +0100)]
cores/icap: add CSR descriptions.
Florent Kermarrec [Wed, 11 Mar 2020 09:58:22 +0000 (10:58 +0100)]
cores/spi: add CSR descriptions.
Florent Kermarrec [Wed, 11 Mar 2020 09:38:28 +0000 (10:38 +0100)]
cores/pwm: add CSR descriptions.
Florent Kermarrec [Wed, 11 Mar 2020 09:05:14 +0000 (10:05 +0100)]
cores/xadc: add CSR descriptions.
Gabriel Somlo [Tue, 10 Mar 2020 23:45:45 +0000 (19:45 -0400)]
integration/soc: add_ethernet: honor self.map["ethmac"], if present
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Florent Kermarrec [Tue, 10 Mar 2020 16:02:28 +0000 (17:02 +0100)]
targets/kcu105: move cd_pll4x.
Florent Kermarrec [Tue, 10 Mar 2020 15:48:07 +0000 (16:48 +0100)]
targets/kcu105: simplify CRG using USIDELAYCTRL.
Florent Kermarrec [Tue, 10 Mar 2020 15:45:38 +0000 (16:45 +0100)]
cores/clock/USIDELAYCTRL: use separate reset/ready counters and set cd_sys.rst internally.
This is the behaviour that was duplicated in each target. Integrating it here
will allow simplifying the targets.
Sean Cross [Tue, 10 Mar 2020 12:40:04 +0000 (20:40 +0800)]
soc/cores/spi_opi: documentation fixes
The ModuleDoc-generated documentation for the spi_opi module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the spi_opi document would appear as full
sections.
This cleans up these errors so that it parses properly under sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
Sean Cross [Tue, 10 Mar 2020 12:37:55 +0000 (20:37 +0800)]
soc/cores/i2s: fix rst parsing errors
The ModuleDoc-generated documentation for the i2s module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the i2s document would appear as full
sections.
This cleans up these errors so that it parses properly under sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
Florent Kermarrec [Tue, 10 Mar 2020 12:08:49 +0000 (13:08 +0100)]
bios: add more Ultrascale SDRAM debug with sdram_cdly command to set clk/cmd delay.
bunnie [Tue, 10 Mar 2020 10:48:30 +0000 (18:48 +0800)]
add fractional division options to clk0 config on PLL
S7 MMCMs allow fractional divider on clock 0. Add a fallback
to try fractional values on clock 0 if a solution can't be found.
This is necessary for e.g. generating both a 100MHz and 48MHz
clock from a 12MHz source with margin=0
enjoy-digital [Tue, 10 Mar 2020 10:43:23 +0000 (11:43 +0100)]
Merge pull request #419 from gsomlo/gls-ultra-sdram-fixup
software/bios: fixup for Ultrascale SDRAM debug
Florent Kermarrec [Tue, 10 Mar 2020 10:11:33 +0000 (11:11 +0100)]
cores/clock: add logging to visualize clkin/clkouts and computed config.
Florent Kermarrec [Tue, 10 Mar 2020 10:10:23 +0000 (11:10 +0100)]
integration/soc: add FPGA device and System clock to logs.
Florent Kermarrec [Tue, 10 Mar 2020 10:09:56 +0000 (11:09 +0100)]
targets/icebreaker: create CRG after SoC.
Gabriel Somlo [Mon, 9 Mar 2020 14:24:30 +0000 (10:24 -0400)]
software/bios: fixup for Ultrascale SDRAM debug
Keep CSR accesses independent of csr_data_width and csr_alignment.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Florent Kermarrec [Mon, 9 Mar 2020 18:36:39 +0000 (19:36 +0100)]
integration/soc: set use_rom when cpu_reset_address is defined in a rom region.
Florent Kermarrec [Mon, 9 Mar 2020 18:16:02 +0000 (19:16 +0100)]
boards/platforms/icebreaker: cleanup a bit.
Florent Kermarrec [Mon, 9 Mar 2020 18:08:27 +0000 (19:08 +0100)]
software/common: fix LTO checks.
Florent Kermarrec [Mon, 9 Mar 2020 18:03:05 +0000 (19:03 +0100)]
soc/cores/clock/iCE40PLL: add SB_PLL40_PAD support.
Florent Kermarrec [Mon, 9 Mar 2020 18:02:23 +0000 (19:02 +0100)]
build/lattice/icestorm: add timingstrict parameter and default to False. (similar behavior than others backends)
Florent Kermarrec [Mon, 9 Mar 2020 16:02:29 +0000 (17:02 +0100)]
targets/icebreaker: simplify, use standard VexRiscv, add iCE40PLL and run BIOS from SPI Flash.
Florent Kermarrec [Mon, 9 Mar 2020 15:51:11 +0000 (16:51 +0100)]
lattice/icestorm: enable DSP inference with Yosys and avoid setting SPI Flash in deep sleep mode after configuration which prevent running ROM CPU code from SPI Flash.
Florent Kermarrec [Mon, 9 Mar 2020 10:56:55 +0000 (11:56 +0100)]
boards: add initial icebreaker platform/target from litex-boards.
Florent Kermarrec [Mon, 9 Mar 2020 09:55:31 +0000 (10:55 +0100)]
software/bios: add Ultrascale SDRAM debug functions.
Florent Kermarrec [Mon, 9 Mar 2020 08:37:31 +0000 (09:37 +0100)]
boards/platforms/kcu105: avoid unnecessary {{}} on INTERNAL_VREF.
Florent Kermarrec [Sun, 8 Mar 2020 18:17:31 +0000 (19:17 +0100)]
integration/soc/SoCRegion: add size_pow2 and use this internally for checks since decoder is using rounded size to next power or 2.
Florent Kermarrec [Fri, 6 Mar 2020 19:05:27 +0000 (20:05 +0100)]
soc: allow creating SoC without BIOS.
By default the behaviour is unchanged and the SoC will provide a ROM:
./arty.py
Bus Regions: (4)
rom : Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
sram : Origin: 0x01000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False
main_ram : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False
csr : Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
The integrated rom can be disabled with:
./arty.py --integrated-rom-size=0
but the SoC builder will check for a user provided rom, and if not provided will complains:
ERROR:SoC:CPU needs rom Region to be defined as Bus or Linker Region.
When a rom is provided, the CPU will use the rom base address as cpu_reset_address.
If the user just wants the CPU to start at a specified address without providing a rom,
the cpu_reset_address parameter can be used:
./arty.py --integrated-rom-size=0 --cpu-reset-address=0x01000000
If the provided reset address is not located in any defined Region, an error will
be produced:
ERROR:SoC:CPU needs reset address 0x00000000 to be in a defined Region.
When no rom is provided, the builder will not build the BIOS.
enjoy-digital [Fri, 6 Mar 2020 18:00:13 +0000 (19:00 +0100)]
Merge pull request #416 from enjoy-digital/csr_svd
Add SVD export capability to Builder (csr_svd parameter) and targets …
Florent Kermarrec [Fri, 6 Mar 2020 13:53:59 +0000 (14:53 +0100)]
integration/builder: rename software methods to _prepare_rom_software/_generate_rom_software/_initialize_rom_software.
Florent Kermarrec [Fri, 6 Mar 2020 13:20:32 +0000 (14:20 +0100)]
integration/builder: generate csr maps before compiling software.
Florent Kermarrec [Fri, 6 Mar 2020 07:36:52 +0000 (08:36 +0100)]
Add SVD export capability to Builder (csr_svd parameter) and targets (--csr-svd argument) and fix svd regression.
This allows generating SVD export files during the build as we are already doing for .csv or .json.
Use with Builder:
builder = Builder(soc, csr_svd="csr.svd")
Use with target:
./arty.py --csr-svd=csr.svd
Florent Kermarrec [Thu, 5 Mar 2020 22:42:16 +0000 (23:42 +0100)]
software/common.mak: fix LTO refactoring issue.
enjoy-digital [Thu, 5 Mar 2020 18:05:02 +0000 (19:05 +0100)]
Merge pull request #412 from antmicro/fix-copyrights
Fix copyrights
Karol Gugala [Thu, 5 Mar 2020 16:44:10 +0000 (17:44 +0100)]
Fix copyrights
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
enjoy-digital [Thu, 5 Mar 2020 14:22:40 +0000 (15:22 +0100)]
Merge pull request #408 from gsomlo/gls-fix-nexys-sdcard
targets/nexys4ddr: fix sdcard clocker initialization
Gabriel Somlo [Wed, 4 Mar 2020 18:38:02 +0000 (13:38 -0500)]
targets/nexys4ddr: fix sdcard clocker initialization
enjoy-digital [Thu, 5 Mar 2020 10:43:02 +0000 (11:43 +0100)]
Merge pull request #410 from antmicro/netv2-edid
platform/netv2: add proper I2C pins for HDMI IN0
Piotr Binkowski [Thu, 5 Mar 2020 10:27:47 +0000 (11:27 +0100)]
platform/netv2: add proper I2C pins for HDMI IN0
Florent Kermarrec [Thu, 5 Mar 2020 10:19:29 +0000 (11:19 +0100)]
targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
Florent Kermarrec [Wed, 4 Mar 2020 17:33:08 +0000 (18:33 +0100)]
bios/sdcard: update sdclk_mmcm_write with LiteSDCard clocker changes.
Florent Kermarrec [Wed, 4 Mar 2020 15:31:41 +0000 (16:31 +0100)]
doc: align to improve readability.
Florent Kermarrec [Wed, 4 Mar 2020 15:27:11 +0000 (16:27 +0100)]
soc/doc: remove soc.get_csr_regions support.
Now that SoC documentation is integrated in LiteX, this is no longer needed.
Florent Kermarrec [Wed, 4 Mar 2020 14:53:18 +0000 (15:53 +0100)]
bios/main: rename flushl2 command to flush_l2_cache, add flush_cpu_dcache command and expose them in help.
Florent Kermarrec [Wed, 4 Mar 2020 14:21:43 +0000 (15:21 +0100)]
README: update quick start guide and add instructions for windows.
Florent Kermarrec [Wed, 4 Mar 2020 11:16:03 +0000 (12:16 +0100)]
README: update
- improve presentation
- add link to #litex freenode channel.
- add example of complex SoC.
- make it directly usable on Wiki.
- only keep one quick start guide.
- add community paragraph and link to Litex-Hub.
Florent Kermarrec [Wed, 4 Mar 2020 09:53:44 +0000 (10:53 +0100)]
doc: remove partial doc imported from litex-buildenv-wiki: we'll create a LiteX wiki and doc.
Florent Kermarrec [Wed, 4 Mar 2020 08:06:27 +0000 (09:06 +0100)]
build: assume vendor tools are in the PATH and remove automatic sourcing, source and toolchain_path parameters.
Automatic sourcing was not consistent between build backends (and only really supported by ISE/Vivado)
and had no real additional value vs the complexity needed to support it. Now just assume required vendor
tools are in the PATH.
This also removes distutils dependency.
Florent Kermarrec [Wed, 4 Mar 2020 07:11:21 +0000 (08:11 +0100)]
software/common: add LTO enable flag and cleanup.
Florent Kermarrec [Tue, 3 Mar 2020 18:04:18 +0000 (19:04 +0100)]
litex_sim: fix with_uart parameter.
Florent Kermarrec [Mon, 2 Mar 2020 08:44:20 +0000 (09:44 +0100)]
targets/nexys4ddr: add default kwargs parameters.
Florent Kermarrec [Mon, 2 Mar 2020 08:31:45 +0000 (09:31 +0100)]
Merge branch 'master' of https://github.com/enjoy-digital/litex
Florent Kermarrec [Mon, 2 Mar 2020 08:31:32 +0000 (09:31 +0100)]
integration/soc_core: change disable parameters to no-xxyy.
enjoy-digital [Mon, 2 Mar 2020 08:30:05 +0000 (09:30 +0100)]
Merge pull request #405 from sajattack/sifive-triple
add riscv-sifive-elf triple
Florent Kermarrec [Mon, 2 Mar 2020 08:07:31 +0000 (09:07 +0100)]
integration/soc: add auto_int type and use it on all int parameters.
Allow passing parameters as int or hex values.
Florent Kermarrec [Mon, 2 Mar 2020 08:01:05 +0000 (09:01 +0100)]
targets/nexys4ddr: use SoCCore and add_sdram to avoid use of specific SoCSDRAM.
Florent Kermarrec [Mon, 2 Mar 2020 07:42:59 +0000 (08:42 +0100)]
integration/soc: add ethphy CSR in target.
Florent Kermarrec [Sun, 1 Mar 2020 19:50:44 +0000 (20:50 +0100)]
targets/nexys4ddr: use soc.add_ethernet method.
Florent Kermarrec [Sun, 1 Mar 2020 19:50:13 +0000 (20:50 +0100)]
integration/soc: add add_ethernet method.
Florent Kermarrec [Sun, 1 Mar 2020 17:58:55 +0000 (18:58 +0100)]
integration/soc: mode litedram imports to add_sdram, remove some separators.
Paul Sajna [Sun, 1 Mar 2020 09:39:03 +0000 (01:39 -0800)]
add riscv-sifive-elf triple
Florent Kermarrec [Sat, 29 Feb 2020 10:07:06 +0000 (11:07 +0100)]
test/test_targets: use uart-name=stub.
Florent Kermarrec [Fri, 28 Feb 2020 21:34:11 +0000 (22:34 +0100)]
soc/uart: add configurable UART FIFO depth.