kajoljain379 [Sat, 12 Jan 2019 08:06:30 +0000 (13:36 +0530)]
arch-power: Initialize PC State
Initialize PC state to 0x100.
Change-Id: Id130d161e40d287dfb1a1f97d5e1d58dfa0f2303
Signed-off-by: kajoljain379 <kajoljain797@gmail.com>
Kajol Jain [Wed, 12 Jun 2019 07:02:59 +0000 (12:32 +0530)]
arch-power: Added function to modify MSR and SRR1 register
* Added general function to modify MSR and SRR1 register.
* Added macros to get mask for
* Set particular bit.
* Unset Bit.
Change-Id: I17b82f6ef7f7d8915f9c1320f99fc6f3f9ecaf74
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>
Phanikiran Harithas [Sun, 10 Jun 2018 12:15:05 +0000 (17:45 +0530)]
power: Add support for Radix Translation
Power ISA v3.0 introduces the Radix MMU in addition to the Hash MMU.
This patch adds support in gem5 for handling the Radix based address
translations when MSR[IR,DR] bits are set.
It also adds an example of a radix_walk.
Change-Id: I193f8d44f36b429997f7ffcb788a50544ba65a8c
Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Phanikiran Harithas [Sun, 10 Jun 2018 10:41:41 +0000 (16:11 +0530)]
power: Add support for real-mode addressing (translation is off)
This patch adds support for executing programs which don't have the
translation support (MSR[IR, DR] = 0). With this change, we should be
able to run 64 little endian elf binaries executing previleged
instructions with translation off.
Change-Id: Iaa64a37676874cee1ed1a0591b51b5e842774b45
Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Phanikiran Harithas [Sun, 10 Jun 2018 09:01:05 +0000 (14:31 +0530)]
power: Add support for handling the Decrementer Interrupt
This patch allows the programming of the decrementer device, which
will count down to zero. As of now, the decrement happens after every
instruction. When the decrementer value hits 0, the CPU is delivered a
decrementer interrupt.
[ego@linux.vnet.ibm.com: Fixed Conflicts in src/arch/power/interrupts.hh]
Change-Id: I3a863a8e2bca434d5a8139df662429d3e83a8542
Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Phanikiran Harithas [Sun, 10 Jun 2018 08:33:04 +0000 (14:03 +0530)]
arch-power: Define more special purpose registers, mtspr,mfspr instructions
This patch defines more special purpose registers taking their count
to 49.
This also defines the mtspr and mfspr instructions to move the
contents to and from the these special purpose registers.
[ego@linux.vnet.ibm.com: Fixed conflicts in
src/arch/power/isa/decoder.isa,
src/arch/power/isa/operands.isa,
src/arch/power/registers.hh]
[kajoljain797@gmail.com: Fixed rfid, hrfid, mtmsr, mtmsrd instructions]
NOTE: Perhaps can be folded into the previous patch which introduces
CR, MSR, PTCR, etc.
Change-Id: I4dd6ba8c710c4c522fadc685b60fb039dfd0a743
Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>
Phanikiran Harithas [Sun, 10 Jun 2018 08:19:58 +0000 (13:49 +0530)]
power: Added support for CR, XER, FPSR, MSR, PTCR Registers
Define Condition Register (CR), XER, FPSR, MSR, PTCR Registers
as miscelleneous registers.
In particular, annotate the bits of MSR and PTCR for future use.
Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Change-Id: I6f1490b1490e16f9095075f5cd0056894fbf6608
phanikiran [Sun, 10 Jun 2018 08:02:57 +0000 (13:32 +0530)]
Power: Add a minimal system configuration
[ego@linux.vnet.ibm.com: Fixeed conflicts in example/fs.py]
Signed-off-by: Phanikiran Harithas <phanikiran.harithas@gmail.com>
Signed-off-by: Venkatnarayan Kulkarni <venkatnarayankulkarni@gmail.com>
Change-Id: Idf6dad2ea3a7eef7bb3475c5abb2108690e59942
Sandipan Das [Thu, 7 Jun 2018 14:46:12 +0000 (20:16 +0530)]
arch-power: Update hello test program
This updates the hello test program binary to an equivalent
64-bit little endian executable. Since this binary is built
with a recent toolchain, the kernel version provided by the
uname system call is ramped up to be able to meet the minimum
version required by glibc. This binary also uses the readlink
system call and the Move From Time Base (mftb) instruction.
So, placeholder code is added for these.
Change-Id: I645b344e8582f938711b75488bd25899c374cca3
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 14:37:02 +0000 (20:07 +0530)]
arch-power: Fix stack layout for 64-bit execution
This fixes the call stack layout by changing the size of the
auxiliary vector entries, each of which contain two 64-bit
values. Also, all base addresses for stack contents are now
considered to be 64 bits in order to prevent underflows during
program execution.
Users can now run statically-linked 64-bit ELF ABI v2 compliant
PowerPC LSB ELF executables in syscall emulation mode.
Change-Id: I256399d9344b1b101385e32ad8978325aec9844e
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 14:33:01 +0000 (20:03 +0530)]
arch-power: Add branch target address register instructions
This adds the definition of the Target Address Register (TAR)
and the following instructions that are associated with it:
* Move To Target Address Register (mttar)
* Move From Target Address Register (mftar)
* Branch Conditional to Branch Target Address Register (bctar[l])
Change-Id: I5130a22040e30a05e963b1cc8d38abbed9a49edb
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 14:30:41 +0000 (20:00 +0530)]
arch-power: Fix branch instructions
This fixes the following branch instructions in order to
support 64-bit addressing:
* Branch (b[l][a])
* Branch Conditional (bc[l][a])
* Branch Conditional to Link Register (bclr[l])
* Branch Conditional to Count Register (bcctr[l])
This also fixes disassembly generation for all of the above.
Change-Id: I7cad4e1b3b2945ab06c4ffc8c79842f1453c85ec
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 13:30:23 +0000 (19:00 +0530)]
arch-power: Add fixed-point doubleword rotate instructions
This adds the following rotate instructions:
* Rotate Left Doubleword Immediate then Clear Left (rldicl[.])
* Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
* Rotate Left Doubleword Immediate then Clear (rldic[.])
* Rotate Left Doubleword then Clear Left (rldcl[.])
* Rotate Left Doubleword then Clear Right (rldcr[.])
* Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])
Change-Id: I27520314e738e5bed92bf07c1150943c9f83e881
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 13:20:10 +0000 (18:50 +0530)]
arch-power: Add fields for MD and MDS form instructions
This introduces the extended opcode fields and the fields
mb and me for MD and MDS form instructions.
Change-Id: I2c3366794ed42f5d31ba1d69e360c0ac67c74e06
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 13:16:02 +0000 (18:46 +0530)]
arch-power: Fix fixed-point word rotate instructions
This fixes the following rotate instructions:
* Rotate Left Word Immediate then And with Mask (rlwinm[.])
* Rotate Left Word then And with Mask (rlwnm[.])
* Rotate Left Word Immediate then Mask Insert (rlwimi[.])
For 64-bit execution, these instructions should perform rotate
operations on a 64-bit value formed by concatenating two copies
of the lower order 32 bits of the value in the source register.
This also fixes disassembly generation for all of the above.
Change-Id: Iccd8c6ad10a26d66dcecd64c8f1f8118ec8c1278
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 13:09:20 +0000 (18:39 +0530)]
arch-power: Add fixed-point doubleword shift instructions
This adds the following shift instructions:
* Shift Left Doubleword (sld[.])
* Shift Right Doubleword (srd[.])
* Shift Right Algebraic Doubleword (srad[.])
* Shift Right Algebraic Doubleword Immediate (sradi[.])
* Extend-Sign Word and Shift Left Immediate (extswsli[.])
Change-Id: Icd1f3efda715c5b8a7c7bc648ba29a8749e74695
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 12:48:50 +0000 (18:18 +0530)]
arch-power: Add fields for XS form instructions
This introduces the extended opcode field and the field
sh for XS form instructions.
Change-Id: I8f7cb3a2fda33b5b0076ffe12ffebeb5ec1c33a6
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 12:46:46 +0000 (18:16 +0530)]
arch-power: Fix fixed-point word shift instructions
This fixes the following shift instructions:
* Shift Left Word (slw[.])
* Shift Right Word (srw[.])
* Shift Right Algebraic Word (sraw[.])
* Shift Right Algebraic Word Immediate (srawi[.])
For 64-bit execution, these instructions should perform
shift operations on only the lower order 32 bits of the
source register instead of all 64 bits.
This also fixes disassembly generation for all of the above.
Change-Id: I18871486d74969244d474eaf0f9d810f06faf50a
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 10:57:21 +0000 (16:27 +0530)]
arch-power: Add fixed-point logical bit permute instructions
This adds the following logical instructions:
* Bit Permute Doubleword (bpermd[.])
Change-Id: I1af329cd28871c00ebb0574e38a53bcd6a3b794c
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 10:46:01 +0000 (16:16 +0530)]
arch-power: Add fixed-point logical parity instructions
This adds the following logical instructions:
* Parity Word (prtyw)
* Parity Doubleword (prtyd)
Change-Id: Icb1737435dfabf9ac7b14ce1fcdf1c232289bf24
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 10:38:15 +0000 (16:08 +0530)]
arch-power: Add fixed-point logical population count instructions
This adds the following logical instructions:
* Population Count Bytes (popcntb)
* Population Count Words (popcntw)
* Population Count Doubleword (popcntd)
Change-Id: I946d1f8b270b4c75849cdfb7e413974ae8748494
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 09:39:04 +0000 (15:09 +0530)]
arch-power: Add fixed-point logical count zeros instructions
This adds the following logical instructions:
* Count Trailing Zeros Word (cnttzw[.])
* Count Leading Zeros Doubleword (cntlzd[.])
* Count Trailing Zeros Doubleword (cnttzd[.])
Change-Id: I4bcf090178d9241f230509ba55e8e58f5e7794ac
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 09:30:27 +0000 (15:00 +0530)]
arch-power: Add fixed-point logical extend sign instructions
This adds the following logical instructions:
* Extend Sign Word (extsw[.])
Change-Id: I610e84c2361b99b00ceef2170ede5b6dee8ec21b
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 09:19:41 +0000 (14:49 +0530)]
arch-power: Fix fixed-point logical instructions
This fixes the following logical instructions:
* Extend Sign Byte (extsb[.])
* Extend Sign Halfword (extsh[.])
* Count Leading Zeros Word (cntlzw[.])
* Compare Bytes (cmpb)
This also fixes disassembly generation for all of the above.
Change-Id: I98873edf24db606d8de481aa18bcb809ad38d296
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 09:15:03 +0000 (14:45 +0530)]
arch-power: Add fixed-point compare instructions
This adds the following compare instructions:
* Compare Ranged Byte (cmprb)
* Compare Equal Byte (cmpeqb)
Change-Id: I44765b3a9a8f0a3d81ecd6984efce3fd01ba4b24
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 08:53:20 +0000 (14:23 +0530)]
arch-power: Fix fixed-point compare instructions
This fixes the following compare instructions:
* Compare (cmp)
* Compare Logical (cmpl)
* Compare Immediate (cmpi)
* Compare Logical Immediate (cmpli)
Instead of always doing a 32-bit comparison, these instructions
now use the length field to determine the type of comparison to
be done. The comparison can either be based on the lower order
32 bits or on all 64 bits of the values.
This also fixes disassembly generation for all of the above.
Change-Id: I6a9f783efa9ef2f2ef3c16eada61074d6f798a20
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 06:53:49 +0000 (12:23 +0530)]
arch-power: Add fixed-point doubleword arithmetic modulo instructions
This adds the following arithmetic instructions:
* Modulo Signed Doubleword (modsd)
* Modulo Unsigned Doubleword (modud)
Change-Id: Ic7bcb85869ccedf5c95aadfe925c85b3b1155031
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 06:51:13 +0000 (12:21 +0530)]
arch-power: Add fixed-point doubleword arithmetic divide extended instructions
This adds the following arithmetic instructions:
* Divide Doubleword Extended (divde[o][.])
* Divide Doubleword Extended Unsigned (divdeu[o][.])
Change-Id: I535605fa6d32153054d259bcb14b952a26a1372a
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 06:37:31 +0000 (12:07 +0530)]
arch-power: Add fixed-point doubleword arithmetic divide instructions
This adds the following arithmetic instructions:
* Divide Doubleword (divd[o][.])
* Divide Doubleword Unsigned (divdu[o][.])
Change-Id: Iedfa46ee482201a25dbc195ac5cb7f5f5e83c29b
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 06:30:28 +0000 (12:00 +0530)]
arch-power: Add fixed-point doubleword multipy-add instructions
This adds the following arithmetic instructions:
* Multiply-Add Low Doubleword (maddld)
* Multiply-Add High Doubleword (maddhd)
* Multiply-Add High Doubleword Unsigned (maddhdu)
Change-Id: I09ecca9f3eb0abaf6b5a82a6d33d7f3e54b9837b
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 06:25:23 +0000 (11:55 +0530)]
arch-power: Add fields for VA form instructions
This introduces the extended opcode field and the operand
field RC for VA form instructions.
Change-Id: I60d1bff6e7c7dd41e6fbe28a5f012b6fd66e7bc3
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 06:23:03 +0000 (11:53 +0530)]
arch-power: Add fixed-point doubleword multiply instructions
This adds the following arithmetic instructions:
* Multiply Low Doubleword (mulld[o][.])
* Multiply High Doubleword (mulhd[.])
* Multiply High Doubleword Unsigned (mulhdu[.])
Change-Id: I505d94dc8e9711c575c94f75e10f7e05e1d05fdf
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 06:13:04 +0000 (11:43 +0530)]
arch-power: Add fixed-point arithmetic add instructions
This adds the following arithmetic instructions:
* Add PC Immediate Shifted (addpcis)
Change-Id: Id9de59427cbf8578fd75cbb7c98fb767d885d89a
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 05:44:41 +0000 (11:14 +0530)]
arch-power: Add fields for DX form instructions
This introduces the extended opcode field and the fields
d0, d1 and d2 for DX form instructions.
Change-Id: Iac52bca39993e4a5f299f33d356e36037c516130
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 05:41:11 +0000 (11:11 +0530)]
arch-power: Add fixed-point word arithmetic modulo instructions
This adds the following arithmetic instructions:
* Modulo Signed Word (modsw)
* Modulo Unsigned Word (moduw)
Change-Id: I5590e569afb71dd429c473bd18c65457e2c49286
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 05:30:35 +0000 (11:00 +0530)]
arch-power: Add fixed-point word arithmetic divide extended instructions
This adds the following arithmetic instructions:
* Divide Word Extended (divwe[o][.])
* Divide Word Extended Unsigned (divweu[o][.])
Change-Id: I1b8321de569d1be466e9d84ca5047b0c4682a0e3
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 05:24:51 +0000 (10:54 +0530)]
arch-power: Fix fixed-point arithmetic multiply and divide instructions
This fixes the following arithmetic instructions:
* Multiply Low Immediate (mulli)
* Multiply Low Word (mullw[o][.])
* Multiply High Word (mulhw[.])
* Multiply High Word Unsigned (mulhwu[.])
* Divide Word (divw[o][.])
* Divide Word Unsigned (divwu[o][.])
This also fixes disassembly generation for all of the above.
Change-Id: I46fd3751b86a7436a962f8b93f26d8343f215fed
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Thu, 7 Jun 2018 04:54:28 +0000 (10:24 +0530)]
arch-power: Fix fixed-point arithmetic add and subtract instructions
This fixes the following arithmetic instructions:
* Add Immediate (addi)
* Add Immediate Shifted (addis)
* Add (add[o][.])
* Subtract From (subf[o][.])
* Add Immediate Carrying (addic)
* Add Immediate Carrying and Record (addic.)
* Subtract From Immediate Carrying (subfic)
* Add Carrying (addc[o][.])
* Subtract From Carrying (subfc[o][.])
* Add Extended (adde[o][.])
* Subtract From Extended (subfe[o][.])
* Add to Zero Extended (addze[o][.])
* Subtract From Zero Extended (subfze[o][.])
* Negate (neg[o][.])
This also fixes disassembly generation for all of the above.
Change-Id: I431020a3f8b8610d6e18d1450848a50f477912cb
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Wed, 6 Jun 2018 21:48:00 +0000 (03:18 +0530)]
arch-power: Add fixed-point store conditional instructions
This adds the following store instructions:
* Store Byte Conditional Indexed (stbcx.)
* Store Halfword Conditional Indexed (sthcx.)
* Store Doubleword Conditional Indexed (stdcx.)
Change-Id: I065113e817e2ae419a6f3231e645bacd95460607
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Wed, 6 Jun 2018 21:44:13 +0000 (03:14 +0530)]
arch-power: Add fixed-point load and reserve instructions
This adds the following load instructions:
* Load Byte And Reserve Indexed (lbarx)
* Load Halfword And Reserve Indexed (lharx)
* Load Doubleword And Reserve Indexed (ldarx)
Change-Id: Iac3cf0e16e2b5da8b772be81850419e21f26bdab
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Wed, 6 Jun 2018 21:41:17 +0000 (03:11 +0530)]
arch-power: Add fixed-point byte-reversed load and store instructions
This adds the following load and store instructions:
* Load Halfword Byte-Reverse Indexed (lhbrx)
* Load Word Byte-Reverse Indexed (lwbrx)
* Load Doubleword Byte-Reverse Indexed (ldbrx)
* Store Halfword Byte-Reverse Indexed (sthbrx)
* Store Word Byte-Reverse Indexed (stwbrx)
* Store Doubleword Byte-Reverse Indexed (stdbrx)
Change-Id: I9f211bb4e3007ca09002a9ba4e5afb4b2e67cddd
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Wed, 6 Jun 2018 21:35:44 +0000 (03:05 +0530)]
arch-power: Add fixed-point doubleword load and store instructions
This adds the following load and store instructions:
* Load Doubleword (ld)
* Load Doubleword Indexed (ldx)
* Load Doubleword with Update (ldu)
* Load Doubleword with Update Indexed (ldux)
* Store Doubleword (std)
* Store Doubleword Indexed (stdx)
* Store Doubleword with Update (stdu)
* Store Doubleword with Update Indexed (stdux)
Change-Id: I57a95003b6c6cfc09cc40f9ac03b32a8dfd7b26d
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Wed, 6 Jun 2018 21:27:03 +0000 (02:57 +0530)]
arch-power: Fix fixed-point load and store instructions
This fixes the following load and store instructions as a result
of the change in register widths:
* Load Word and Zero (lwz)
* Load Word and Zero Indexed (lwzx)
* Load Word and Zero with Update (lwzu)
* Load Word and Zero with Update Indexed (lwzux)
* Load Word Algebraic (lwa)
* Load Word And Reserve Indexed (lwarx)
* Store Word (stw)
* Store Word Indexed (stwx)
* Store Word with Update (stwu)
* Store Word with Update Indexed (stwux)
* Store Word Conditional Indexed (stwcx.)
This also fixes disassembly generation for all of the above.
Change-Id: I1a25cdb5ffe86145b7ffcf2c2bd7b27048a415d2
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Wed, 6 Jun 2018 21:00:09 +0000 (02:30 +0530)]
arch-power: Introduce proper opcode fields
This introduces separate extended opcode fields for DS, X, XFL,
XFX, XL and XO form instructions and renames the primary opcode
field from OPCODE to PO as listed in the Power ISA manual.
Scenarios where multiple instructions of different forms share
the same primary opcode have also been addressed by using the
correct extended opcode fields for decoding.
Change-Id: I4a01820f6a6326ef79330221b717952c6b9cbba3
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Wed, 6 Jun 2018 19:48:55 +0000 (01:18 +0530)]
arch-power: Reorder instruction decoding logic
This reorders the decoding logic based on the category of
instructions. The ordering applied here is roughly in line
with the Power ISA manual which is as follows:
* Branch facility instructions
* Branch instructions
* Condition Register instructions
* System Call instructions
* Fixed-point facility instructions
* Load instructions
* Store instructions
* Arithmetic instructions
* Compare instructions
* Logical instructions
* Rotate and Shift instructions
* Move To/From System Register instructions
* Floating-point facility instructions
* Load instructions
* Store instructions
* Arithmetic instructions
* Move instructions
* Rounding and Conversion instructions
* Compare instructions
* Status and Control Register instructions
Change-Id: Icfb57c5e442a959e502222222b84289d8e74ecbf
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Mon, 4 Jun 2018 16:21:23 +0000 (21:51 +0530)]
arch-power: Make ELF interpreter read 64-bit LSB executables
This makes the ELF interpreter read 64-bit little endian (LSB)
PowerPC executables only. This drops support for the 32-bit big
endian (MSB) executables as the goal here is to enable a modern
64-bit execution environment for the Power ISA.
Change-Id: I0569f7e1d1e58ce874ec2d13291e7a758d56399f
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Sandipan Das [Mon, 4 Jun 2018 15:02:28 +0000 (20:32 +0530)]
arch-power: Switch to 64-bit registers and operands
This increases the width of the general-purpose registers and some
of the other important registers to 64 bits. This is a prerequisite
for enabling a 64-bit execution environment and allows the register
operands provided in instructions to also be recognized as 64-bit.
Change-Id: I442315163a5029bbfb9d4b16b5e6decd3ab2d61b
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Bobby R. Bruce [Wed, 11 Nov 2020 21:34:23 +0000 (13:34 -0800)]
misc: Updated the RELEASE-NOTES and version number
Updated the RELEASE-NOTES.md and version number for the v20.1.0.2
hotfix release.
Change-Id: Ibb6b62a36bd1f9084f7d8311ff1f94b8564dbe9b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37435
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Sat, 17 Oct 2020 10:48:22 +0000 (03:48 -0700)]
cpu,stats: Fix incorrect stat names of ThreadStateStats
Previously, ThreadStateStats uses ThreadState::threadId() to
determine the name of the stats. However, in the ThreadState
constructor, ThreadStateStats is initialized before ThreadState
is intialized. As a result, the name of ThreadStateStats has
a wrong ThreadID.
This commit uses ThreadID instead of ThreadState to determine
the name of the stats.
This causes a name collision between ThreadStateStats and
ExecContextStats as both have the name of "thread_[tid]".
Ideally, those stats should be merged to the BaseSimpleCPU.
However, both ThreadStateStats and ExecContextStats have
a stat named numInsts. So, for now, ExecContextStats will
have a name of "exec_context.thread_[tid]", while ThreadStateStats
keeps its name.
Change-Id: If9a21549f98bd6e3ce6dc29bdf183e8fd5f51a67
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37455
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Sun, 8 Nov 2020 14:38:04 +0000 (15:38 +0100)]
configs: Fix MemorySize division
The memory size is expected to be an integer.
Jira: https://gem5.atlassian.net/browse/GEM5-806
Change-Id: I44b2d423a3478d2598950779222151f09970cbd8
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37255
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Bobby R. Bruce [Thu, 5 Nov 2020 22:38:25 +0000 (14:38 -0800)]
misc: Updated the RELEASE-NOTES and version number
Updated the RELEASE-NOTES.md and version number for the v20.1.0.1
hot-fix.
Change-Id: I51f7ba6f1178a2d8e80488ed2184b8735c2234a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37116
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
jiemingyin [Wed, 21 Oct 2020 23:43:05 +0000 (19:43 -0400)]
mem-garnet: Fix garnet network interface stats
Fixing a bug in garnet network interface where flit source delay is
computed using both tick and cycle.
Change-Id: If21a985f371a818611d13e9cd5ce344dbcf5fb2b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36416
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37115
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jieming Yin <bjm419@gmail.com>
Bobby R. Bruce [Wed, 30 Sep 2020 18:14:02 +0000 (11:14 -0700)]
misc: Updated version to 20.1.0.0
Change-Id: Ic7a37581c58caa354eeecab051122116177d0721
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35456
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Wed, 30 Sep 2020 17:55:03 +0000 (10:55 -0700)]
scons: Removed -Werror for the gem5 20.1 release
While gem5 compiles on all our supported compilers, removing the -Werror
flag on the stable branch ensures that, as new compilers are released
with stricter warnings, gem5 remains compilable.
Change-Id: I9a356472dc4d729a3fef9f1455814c900103bd66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35455
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Wed, 30 Sep 2020 22:11:17 +0000 (15:11 -0700)]
misc: Updated CONTRIBUTING.md: 'master' -> 'stable'
The `master` branch is now the `stable` branch. This commit updates
CONTRIBUTING.md accordingly.
Change-Id: Ic5231eda336520e8a7260efac6474b4f0af08c37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35457
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Jason Lowe-Power [Wed, 30 Sep 2020 00:03:08 +0000 (17:03 -0700)]
misc: Add release notes for 20.1
Change-Id: I011ff987e222326dd7f0787c41043578b52b236a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35375
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Sungkeun Kim [Thu, 24 Sep 2020 11:42:18 +0000 (06:42 -0500)]
sim: Adding missing argument of panic function
panic function call in panicFsOnlyPseudoInst (src/sim/pseudo_inst.cc) needs to be invoked with argument (name).
Jira Issue: https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/GEM5-786?filter=allissues
Change-Id: Iecacab7b9e0383373b69e9b790fa822d173d29c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35040
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Nikos Nikoleris [Tue, 29 Sep 2020 09:28:24 +0000 (10:28 +0100)]
ext: Disable range-loop-analysis warnings for pybind11
Change-Id: I9d9e118c1c70c2f6b11260fff31ecd763e491115
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35296
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Fri, 25 Sep 2020 17:25:43 +0000 (10:25 -0700)]
tests,misc: Updated TestLib and boot-tests for gzipped imgs
In efforts to reduce storage costs and download times, the images hosted
by us have been gzipped. The TestLib framework has therefore been
extended to decompress gzipped files after download.
The x86-boot-tests are, at present, the only tests which use the gem5
images. These tests have been updated to download the gzipped image.
Change-Id: I6b2dbe9472a604148834820db8ea70e91e94376f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35257
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Mon, 28 Sep 2020 18:56:19 +0000 (11:56 -0700)]
scons,python: Add warning for when python3-config is not used
We cannot say for certain whether 'python-config' is python2 or python3,
but this patch will produce a warning if 'python3-config' is not used,
stating that support for python2 will be dropped in future releases of
gem5.
Change-Id: I114da359c8768071bf7dd7f2701aae85e3459678
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35256
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Tue, 22 Sep 2020 20:05:02 +0000 (13:05 -0700)]
tests: Removing gem5/hello_se/ref/simerr
This is not needed in any comparison we make. It was probably added in
error.
Change-Id: Ie771654f73d101d0ef90ca6e2864a7cb684b3919
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34996
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Mon, 28 Sep 2020 18:23:38 +0000 (11:23 -0700)]
scons,python: Add python2-config to PYTHON_CONFIG
PYTHON_CONFIG can be python2-config as well as python2.7-config.
Change-Id: I482cb922fcf26b37f67f2aca392e04968ca144bd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35255
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Mon, 21 Sep 2020 20:51:19 +0000 (13:51 -0700)]
scons,python: Prioritize Python3 for PYTHON_CONFIG
Change-Id: I0ac4d90b93f2e0a9384216f759937f7b0aa23d41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34899
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Tue, 22 Sep 2020 19:37:34 +0000 (12:37 -0700)]
python: Flush the simulation stdout/stderr buffers
Occasionally gem5's stdout/stderr, when run within the TestLib
framework, will be shuffled. This is resolved by flushing the
stdout/stderr buffer before and after simulation.
In addition to this, the verifier.py has been improved to remove
boilerplate gem5 code from the stdout comparison.
Change-Id: I04c8f9cee4475b8eab2f1ba9bb76bfa3cfcca6ec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34995
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Timothy Hayes [Wed, 23 Sep 2020 13:39:46 +0000 (14:39 +0100)]
arch-arm: Instantiate a single HTM checkpoint at ISA::startup
Change-Id: I48cc71dce607233f025387379507bcd485943dde
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35016
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Timothy Hayes [Wed, 23 Sep 2020 11:10:37 +0000 (12:10 +0100)]
cpu: Allow storing an invalid HTM checkpoint
Commits
02745afd and
f9b4e32 introduced a mechanism for creating checkpoint
objects for hardware transactional memory (HTM) and Arm TME. Because the
checkpoint object also contains the local UID of a transaction, it is
needed before any architectural checkpointing takes places. This caused
segfaults when running HTM codes.
This commit allows ISAs to allocate a checkpoint once at the beginning
of simulation. In order to do that we need to remove the validity check
assertion; the cpt will become valid only after a first successfull
transaction start
Change-Id: I233d01805f8ab655131ed8cd6404950a2bf6fbc7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35015
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Nikos Nikoleris [Thu, 17 Sep 2020 17:09:32 +0000 (18:09 +0100)]
mem: Fix some reference use in range loops
This change fixes two cases of range loops, one where we can't use
lvalue reference, and one more where we have to use an lvalue
reference as we can't create a copy. In both cases clang would warn.
Change-Id: I760aa094af66be32a150bad37acc21d6fd512a65
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34776
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Fri, 25 Sep 2020 07:56:24 +0000 (00:56 -0700)]
mem: When loading an image directly in memory, use the right CL size.
Some code was added fairly recently which would load a memory image
into a memory directly in order to make it easier to set up ROMs.
Unfortunately, that code accidentally used the image size instead of
the cache line size when setting up the port proxy which would actually
write the data. This happens to work when the image size is a power of
two since that's all the proxy checks for, but there's no guarantee
that every image will be sized that way.
This change instead looks into the system object, retrieves the cache
line size from it, and uses that to set up the port proxy.
Change-Id: I227ac475b855d9516e1feb881769e12ec4e7d598
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35155
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Matthew Poremba [Thu, 24 Sep 2020 18:10:04 +0000 (13:10 -0500)]
configs: Set kvm_map in DRAMInterface in Ruby.py
The kvm_map parameter from AbstractMemory has been moved from MemCtrl
(formerly DRAMCtrl) to DRAMInterface. Assign it to DRAMInterface
instead.
Change-Id: I4508aefcf5eb859d9ffe05c81d85a1b84ee0a196
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35095
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Thu, 24 Sep 2020 07:36:21 +0000 (00:36 -0700)]
fastmodel: Update the IRIS ThreadContext base class.
The syscall() method has been removed, and HTM related methods have
been added.
Change-Id: I796c1a554bfd4b1ee01a62c9c7ad403dd699cc0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35038
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Thu, 24 Sep 2020 07:37:04 +0000 (00:37 -0700)]
arm,fastmodel: Update the VExpressFastModel to use ArmInterruptPins.
The HDLCD device now uses an ArmInterruptPin instead of a GIC and
interrupt number parameter.
Change-Id: I31122e66a1c18f61592f3dca214ee057baad8f88
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35039
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Thu, 24 Sep 2020 07:34:54 +0000 (00:34 -0700)]
fastmodel: Update for the isa_traits.hh changes.
arch/arm/isa_traits.hh no longer has using namespace ArmISA, and also
no longer directly or indirectly provides interrupt number related
constants.
Change-Id: Ieda31d1db4f85632a555b2f72ee8bff0aa159eee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35037
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Mon, 21 Sep 2020 19:13:08 +0000 (12:13 -0700)]
tests,base: Fixed unittests for .fast
unittests.fast, unittests.prof, and unittests.perf had failing tests due
to the stripping of asserts via compiler optimization. This patch alters
the unittests to skip these tests when TRACING_ON == 0.
Change-Id: I2d4ab795ecfc2c4556b5eb1877635409d0836ec6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34898
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Wed, 16 Sep 2020 16:45:13 +0000 (09:45 -0700)]
util: Removed libelf-dev dep from Dockerfiles
The libelf-dev dependency is no longer required in our Dockerfiles.
This reverts commit
0cf67fb36281b17956d4dc10f05054bf711b4ba3,
https://gem5-review.googlesource.com/c/public/gem5/+/33596.
The libelf-dev dependency has been kept for the "all_dependencies"
Dockerfiles.
The corresponding Docker images have been built and uploaded to:
https://gcr.io/gem5-test.
Change-Id: Iacbd8240f69d476ad3a649baaccb6b85fec2487c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34676
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Jason Lowe-Power [Wed, 16 Sep 2020 00:59:51 +0000 (17:59 -0700)]
configs: Add special case in MemConfig
SimpleMemory doesn't implement a full MemCtrl interface. Thus, like the
NVM and HMC memories, we need to add a special case to MemConfig.py. The
--mem-type command line option now works for SimpleMemory and all of the
DRAM interfaces (it does not work for the NVM interfaces, though).
Issue-on: https://gem5.atlassian.net/browse/GEM5-777
Change-Id: I6d60649215be324bdd2a104b1976752f936c960e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34595
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Tue, 15 Sep 2020 02:46:47 +0000 (19:46 -0700)]
mem-ruby: Remove conditional includes based on THE_ISA in ruby.
These were including instruction class definitions from x86 for some
reason. There was no code in those .cc files which actually used
anything from them, as evidenced by the fact that the GCN3_X86 build
still works. No other code in the file was conditionally compiled as of
today.
Change-Id: I3cef8348fb601dd7af67665cf64bbf514c91c3db
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34577
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Tue, 15 Sep 2020 02:45:13 +0000 (19:45 -0700)]
gpu: Fix a syntax error in X86GPUTLB.py.
The recent changes which removed master/slave terminology also
accidentally deleted an "=", making the syntax in that file illegal.
Change-Id: I50aa945f0f66765db36775380b98a88caff23c13
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34576
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Tue, 15 Sep 2020 02:40:42 +0000 (19:40 -0700)]
arm: Use zero initialization for the BigRegVect types.
These were being initialized with BigRegVect brv = {0}, which made the
compiler complain because there is internal structure. The first element
of the union is actually an array, and this was telling it to initialize
that array to scalar 0. It was warning about this which was breaking the
build.
Instead, use zero initlization like BigRegVect brv = {}. This
initializes the first element of the union to all zeroes, with all
padding bits initialized to zero as well.
This satisfies the compiler and avoids a build error.
Change-Id: I31e7a8730c538637ff2e0c7fb00a4e12ed05e074
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34575
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Tue, 15 Sep 2020 03:29:24 +0000 (20:29 -0700)]
cpu,misc: Revert problematic terminology renames in BaseCPU
Due to gem5's use of duck-typing, we must termorarly revert the
terminology in BaseCPU back to master/slave to avoid issues.
This fixes https://gem5.atlassian.net/browse/GEM5-775.
Change-Id: Idf1cb99aa9568ee70943ebec96f27394d8167f8c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34495
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Jason Lowe-Power [Fri, 11 Sep 2020 20:26:29 +0000 (13:26 -0700)]
mem-ruby: Update port names in Ruby
After the terminology update commit there were still many confusing
names in the Ruby ports. This changeset is a proposal for updating these
names.
For an example use case, see the following resources changeset.
https://gem5-review.googlesource.com/c/public/gem5-resources/+/34416
Change-Id: I01d4f24a70b300e39438ee147dfab7a8d674d5c7
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34417
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Jason Lowe-Power [Fri, 11 Sep 2020 18:32:05 +0000 (11:32 -0700)]
tests: Remove MIPS from Learning gem5 tests
Change-Id: Iffd9f5da188cac26ac75a8109886c36789956959
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34415
Reviewed-by: mike upton <michaelupton@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Jason Lowe-Power [Fri, 11 Sep 2020 20:32:06 +0000 (13:32 -0700)]
dev: Fix port name in x86 device
Change-Id: I7704109287b9a1a09e51da3c62c29720631ce87e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34435
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Fri, 11 Sep 2020 20:40:54 +0000 (21:40 +0100)]
arch-arm: Fix ArmISA namespace requirement for Arm KVM
This is needed after:
https://gem5-review.googlesource.com/c/public/gem5/+/34155
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I614b908a48145d8c2f5e8b8177448e3269f8dac9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34418
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Muhammad Sarmad Saeed [Fri, 24 Jul 2020 22:08:27 +0000 (22:08 +0000)]
misc: Update documentation of SimObject related APIs
Updated documentation of Drain, Serialize, Evnet queue and Simobject
APIs. Made some corrections to where the documentation was available
in the code but did not appear in the documentation.
Change-Id: I5254e87eb5663232e824bcd5592da0a04eba673b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31814
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Srikant Bharadwaj [Thu, 10 Sep 2020 07:39:45 +0000 (03:39 -0400)]
mem-garnet: Upgrade garnet version to 3.0
This version of garnet includes HeteroGarnet which
supports heterogenous interconnect systems, flexible
router and link configurations, and better debugging
resources.
This patch changes the garnet directory structure
to not include the version number. The user will be
informed about the garnet version being used.
Change-Id: Id4763421528305193ae0cd10c159b385a9513553
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34259
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Jason Lowe-Power [Thu, 10 Sep 2020 21:58:15 +0000 (14:58 -0700)]
arch-arm: Initialize some cases of destReg
Some compilers complained that this variable may be uninitialized. This
change initializes it to 0.
Change-Id: I201d75ba05ce49d13bbaf4d67e1c728ef704fdf0
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34335
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: mike upton <michaelupton@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Jason Lowe-Power [Thu, 10 Sep 2020 19:06:56 +0000 (12:06 -0700)]
tests: Update x86 system.py for MemCtrl interface
Change-Id: If4103b197720f74df70d0a24602e2b3715936826
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34315
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: mike upton <michaelupton@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Srikant Bharadwaj [Thu, 10 Sep 2020 06:33:51 +0000 (02:33 -0400)]
mem-garnet: Allow empty vnet list for garnet network links
An empty supporting_vnet list is the default and implies that
all vnets are supported. This removes the assert which requires
the list to have a minimum list size of 1.
Change-Id: I6710ba06041164bbd597d98e75374a26a1aa5655
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34258
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Srikant Bharadwaj [Thu, 10 Sep 2020 06:31:43 +0000 (02:31 -0400)]
mem-garnet: Fix default value of network bridge
Initializing the network bridge with NULL causes it to have
an class error when instatiating a link. The bridge is only
needed whne either a CDC or SerDes is enabled. This is handled
later during construction of the GarnetLink.
Change-Id: If19a21a6d9bf49449b9c390467d08d3422ae991a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34257
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Shivani Parekh [Mon, 24 Aug 2020 18:47:44 +0000 (11:47 -0700)]
misc: Replaced master/slave terminology
Change-Id: I4df2557c71e38cc4e3a485b0e590e85eb45de8b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33553
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Dimitrios Chasapis [Thu, 10 Sep 2020 11:53:35 +0000 (13:53 +0200)]
configs,python: Fixes an issue with python3 and the config scripts when restoring a checkpoint
Fixes a compatibility issue with the configuration scripts when trying to restore a checkpoint. Since python2.4 list.sort has an updated interface. The older one has been dropped in python3.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-754
Change-Id: I09f819057d510e477d6ceae0356fafad40f4280d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34295
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Mahyar Samani [Sat, 2 May 2020 02:19:19 +0000 (02:19 +0000)]
tests: cross-compiling hello binaries for hello_se tests.
Some of the hello_se tests fail due to different syntax of the string
for different isas. This patch adds makefiles for cross-compiling the
hello.c file located at tests/test-progs/hello/src/.
Change-Id: I8ccfc0487020df9da722a97e57310db2d2e8882c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28528
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Thu, 10 Sep 2020 05:26:29 +0000 (22:26 -0700)]
cpu: Fixed unused var error when with fast builds
As `is_htm_speculative` is only used in assert statements, it is
considered unused during the `.fast` compilation. This commit adds the
`M5_USED_VAR` macro.
This caused our compiler tests to fail:
https://www.mail-archive.com/gem5-dev@gem5.org/msg35913.html
Change-Id: I00d187d1a31d065c236ac29a657bd479ad4b03bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34256
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Iru Cai [Thu, 10 Sep 2020 06:18:19 +0000 (14:18 +0800)]
arch-arm: just return the fault in twoEqualRegInst{,Fp}
This prevents the code from using the uninitialized destReg when
running the ``if (imm >= eCount)`` branch, which will make GCC 10.2
report a -Werror=maybe-uninitialized error when building gem5.opt.
Change-Id: Ie6e7d3d47a1b65b840b2106263ecfc21eb6af26b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34275
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Iru Cai [Fri, 21 Aug 2020 07:11:39 +0000 (15:11 +0800)]
arch-arm: Fix build errors with gcc 10.2
The "-Werror=type-limits" flag in GCC 10.2 reports these errors,
because ``imm`` in neon.isa, and ``imm`` and ``count`` in sve.isa are
unsigned, and they're used to do ``imm < 0`` and ``imm * count >= 0``
comparison.
Change-Id: I33934357f578a9fc1040a6d9c08ea929fb36eb47
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33154
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Andreas Sandberg [Mon, 24 Aug 2020 17:00:57 +0000 (18:00 +0100)]
dev: Use the new ByteOrder param type in VirtIO devices
VirtIO devices currently request their endianness from the System
object. Instead of explicitly querying the system for its endianness,
expose the device's endianness as a param. This param defaults to the
endianness of a parent object using the Parent proxy (in practice the
system).
Change-Id: If4f84ff61f4d064bdd015a881790f5af03de6535
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33296
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Andreas Sandberg [Mon, 24 Aug 2020 16:55:45 +0000 (17:55 +0100)]
dev: Use the new ByteOrder param type in SimpleUart
Use the new ByteOrder param type in SimpleUart. The default value is
currently little endian. However, it is expected that most users of
this device will use single-byte accesses which aren't affected by
endianness.
Change-Id: I3f5d4ea566e5127474cff976332bd53c5b49b9e2
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33295
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Gabe Black [Mon, 18 May 2020 13:10:15 +0000 (06:10 -0700)]
fastmodel: Add an ISA class which defers to IRIS.
This class is just to enable checkpointing of "ISA" state, aka the
MiscRegs.
Change-Id: I45315b8aaa09aaf6230f44665c13597400efd780
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29822
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Tue, 5 May 2020 05:44:02 +0000 (22:44 -0700)]
fastmodel: Create a fake "Interrupts" object for fast model CPUs.
This object doesn't actually manage interrupts since the fast model
CPUs do that on their own, it just checkpoints interrupt related state.
Change-Id: I9d3a6354b02e4ae7bfd032c50e51a3a841b81388
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29821
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Thu, 10 Sep 2020 00:24:05 +0000 (17:24 -0700)]
arch-mips: Replaced `BigEndianByteOrder` in MIPS
The following change removed the `BigEndianByteOrder` enum and replaced
it with `ByteOrder:big`:
https://gem5-review.googlesource.com/c/public/gem5/+/33174
This change was not propogated to `src/arch/mips/isa/decoder.isa` and
`src/arch/mips/isa/formats/mem.isa`, and therefore caused compilation
errors. This caused the Nightly Build to fail:
https://www.mail-archive.com/gem5-dev@gem5.org/msg35900.html
This commit fixes this error.
Change-Id: I3967eb9e9236a7a95318c17ca410b613b8473eed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34255
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
projects / gem5.git / log