gem5.git
13 years agoARM: Get rid of some comments/todos that no longer apply.
Ali Saidi [Mon, 11 Apr 2011 01:02:28 +0000 (21:02 -0400)]
ARM: Get rid of some comments/todos that no longer apply.

13 years agoruby: fixes to support more types of RubyRequests
Brad Beckmann [Wed, 6 Apr 2011 21:41:41 +0000 (14:41 -0700)]
ruby: fixes to support more types of RubyRequests

13 years agoARM: Update stats for default inclusion of CF adapter.
Ali Saidi [Mon, 4 Apr 2011 16:42:32 +0000 (11:42 -0500)]
ARM: Update stats for default inclusion of CF adapter.

13 years agoARM: Include IDE/CF controller by default in PBX model.
Ali Saidi [Mon, 4 Apr 2011 16:42:31 +0000 (11:42 -0500)]
ARM: Include IDE/CF controller by default in PBX model.

Frame buffer and boot linux:
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit
Linux from a CF card:
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit
Run Android
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android
Run MP
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38

13 years agoSim: Fix Simulation.py to allow more than 1 core for standard switching.
Anthony Gutierrez [Mon, 4 Apr 2011 16:42:31 +0000 (11:42 -0500)]
Sim: Fix Simulation.py to allow more than 1 core for standard switching.

This patch moves the assignment of testsys.switch_cpus, testsys.switch_cpus_1,
switch_cpu_list, and switch_cpu_list1 outside of the for loop so they are
assigned only once, after switch_cpus and switch_cpus_1 are constructed.

13 years agoARM: Update stats for previous changes.
Ali Saidi [Mon, 4 Apr 2011 16:42:31 +0000 (11:42 -0500)]
ARM: Update stats for previous changes.

13 years agoARM: Use CPU local lock before sending load to mem system.
Ali Saidi [Mon, 4 Apr 2011 16:42:29 +0000 (11:42 -0500)]
ARM: Use CPU local lock before sending load to mem system.

This change uses the locked_mem.hh header to handle implementing CLREX. It
simplifies the current implementation greatly.

13 years agoARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.
Ali Saidi [Mon, 4 Apr 2011 16:42:28 +0000 (11:42 -0500)]
ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.

This change fixes a small bug in the arm copyRegs() code where some registers
wouldn't be copied if the processor was in a mode other than MODE_USER.
Additionally, this change simplifies the way the O3 switchCpu code works by
utilizing TheISA::copyRegs() to copy the required context information
rather than the adhoc copying that goes on in the CPU model. The current code
makes assumptions about the visibility of int and float registers that aren't
true for all architectures in FS mode.

13 years agoARM: Fix bug in MicroLdrNeon templates for initiateAcc().
Ali Saidi [Mon, 4 Apr 2011 16:42:28 +0000 (11:42 -0500)]
ARM: Fix bug in MicroLdrNeon templates for initiateAcc().

13 years agoARM: Cleanup and small fixes to some NEON ops to match the spec.
William Wang [Mon, 4 Apr 2011 16:42:28 +0000 (11:42 -0500)]
ARM: Cleanup and small fixes to some NEON ops to match the spec.

Only certain bits of the cpacr can be written, some must be equal.
Mult instructions that write the same register should do something sane

13 years agoARM: Cleanup implementation of ITSTATE and put important code in PCState.
Ali Saidi [Mon, 4 Apr 2011 16:42:28 +0000 (11:42 -0500)]
ARM: Cleanup implementation of ITSTATE and put important code in PCState.

Consolidate all code to handle ITSTATE in the PCState object rather than
touching a variety of structures/objects.

13 years agoARM: Fix m5op parameters bug.
Ali Saidi [Mon, 4 Apr 2011 16:42:28 +0000 (11:42 -0500)]
ARM: Fix m5op parameters bug.

All the m5op parameters are 64 bits, but we were only sending 32 bits;
and the static register indexes were incorrectly specified.

13 years agoARM: Tag appropriate instructions as IsReturn
Ali Saidi [Mon, 4 Apr 2011 16:42:27 +0000 (11:42 -0500)]
ARM: Tag appropriate instructions as IsReturn

13 years agoARM: Fix table walk going on while ASID changes error
Ali Saidi [Mon, 4 Apr 2011 16:42:27 +0000 (11:42 -0500)]
ARM: Fix table walk going on while ASID changes error

13 years agoCPU: Remove references to memory copy operations
Ali Saidi [Mon, 4 Apr 2011 16:42:26 +0000 (11:42 -0500)]
CPU: Remove references to memory copy operations

13 years agoO3: Update stats for memory order violation checking patch.
Ali Saidi [Mon, 4 Apr 2011 16:42:25 +0000 (11:42 -0500)]
O3: Update stats for memory order violation checking patch.

13 years agoO3: Tighten memory order violation checking to 16 bytes.
Ali Saidi [Mon, 4 Apr 2011 16:42:23 +0000 (11:42 -0500)]
O3: Tighten memory order violation checking to 16 bytes.

The comment in the code suggests that the checking granularity should be 16
bytes, however in reality the shift by 8 is 256 bytes which seems much
larger than required.

13 years agoIDE: Support x86, Alpha, and ARM use of the IDE controller.
Ali Saidi [Mon, 4 Apr 2011 16:42:23 +0000 (11:42 -0500)]
IDE: Support x86, Alpha, and ARM use of the IDE controller.

13 years agoARM: Fix checkpointing case where PL111 is powered off.
Ali Saidi [Mon, 4 Apr 2011 16:42:23 +0000 (11:42 -0500)]
ARM: Fix checkpointing case where PL111 is powered off.

13 years agoARM: Remove debugging warn that was accidently left in.
Ali Saidi [Mon, 4 Apr 2011 16:42:23 +0000 (11:42 -0500)]
ARM: Remove debugging warn that was accidently left in.

13 years agoARM: Fix multiplication error in udelay
Ali Saidi [Mon, 4 Apr 2011 16:42:23 +0000 (11:42 -0500)]
ARM: Fix multiplication error in udelay

13 years agohammer: fixed dma uniproc error
Brad Beckmann [Fri, 1 Apr 2011 22:50:23 +0000 (15:50 -0700)]
hammer: fixed dma uniproc error

Fixed an error reguarding DMA for uninprocessor systems.  Basically removed an
overly agressive optimization that lead to inconsistent state between the
cache and the directory.

13 years agoCacheMemory: add allocateVoid() that is == allocate() but no return value.
Lisa Hsu [Fri, 1 Apr 2011 01:20:12 +0000 (18:20 -0700)]
CacheMemory: add allocateVoid() that is == allocate() but no return value.
This function duplicates the functionality of allocate() exactly, except that it does not return
a return value.  In protocols where you just want to allocate a block
but do not want that block to be your implicitly passed cache_entry, use this function.
Otherwise, SLICC will complain if you do not consume the pointer returned by allocate(),
and if you do a dummy assignment Entry foo := cache.allocate(address), the C++
compiler will complain of an unused variable.  This is kind of a hack to get around
those issues, but suggestions welcome.

13 years agoRuby: Simplify SLICC and Entry/TBE handling.
Lisa Hsu [Fri, 1 Apr 2011 00:18:00 +0000 (17:18 -0700)]
Ruby: Simplify SLICC and Entry/TBE handling.
Before this changeset, all local variables of type Entry and TBE were considered
to be pointers, but an immediate use of said variables would not be automatically
deferenced in SLICC-generated code.  Instead, deferences occurred when such
variables were passed to functions, and were automatically dereferenced in
the bodies of the functions (e.g. the implicitly passed cache_entry).

This is a more general way to do it, which leaves in place the
assumption that parameters to functions and local variables of type AbstractCacheEntry
and TBE are always pointers, but instead of dereferencing to access member variables
on a contextual basis, the dereferencing automatically occurs on a type basis at the
moment a member is being accessed.  So, now, things you can do that you couldn't before
include:

Entry foo := getCacheEntry(address);
cache_entry.DataBlk := foo.DataBlk;

or

cache_entry.DataBlk := getCacheEntry(address).DataBlk;

or even

cache_entry.DataBlk := static_cast(Entry, pointer, cache.lookup(address)).DataBlk;

13 years agoRuby: Add new object called WireBuffer to mimic a Wire.
Lisa Hsu [Fri, 1 Apr 2011 00:17:57 +0000 (17:17 -0700)]
Ruby: Add new object called WireBuffer to mimic a Wire.
This is a substitute for MessageBuffers between controllers where you don't
want messages to actually go through the Network, because requests/responses can
always get reordered wrt to one another (even if you turn off Randomization and turn on Ordered)
because you are, after all, going through a network with contention. For systems where you model
multiple controllers that are very tightly coupled and do not actually go through a network,
it is a pain to have to write a coherence protocol to account for mixed up request/response orderings
despite the fact that it's completely unrealistic.  This is *not* meant as a substitute for real
MessageBuffers when messages do in fact go over a network.

13 years agoRuby: have the rubytester pass contextId to Ruby.
Lisa Hsu [Fri, 1 Apr 2011 00:17:51 +0000 (17:17 -0700)]
Ruby: have the rubytester pass contextId to Ruby.

13 years agoRuby: enable multiple sequencers in one controller.
Lisa Hsu [Fri, 1 Apr 2011 00:17:49 +0000 (17:17 -0700)]
Ruby: enable multiple sequencers in one controller.

13 years agoRuby: pass Packet->Req->contextId() to Ruby.
Lisa Hsu [Fri, 1 Apr 2011 00:17:47 +0000 (17:17 -0700)]
Ruby: pass Packet->Req->contextId() to Ruby.
It is useful for Ruby to understand from whence request packets came.
This has all request packets going into Ruby pass the contextId value, if
it exists.  This supplants the old libruby proc_id value passed around in
all the Messages, so I've also removed the unused unsigned proc_id; member
generated by SLICC for all Message types.

13 years agoRuby: Bug in SLICC forgot semicolon at end of code.
Lisa Hsu [Thu, 31 Mar 2011 19:20:16 +0000 (12:20 -0700)]
Ruby: Bug in SLICC forgot semicolon at end of code.

13 years agosim: typecast Tick to UTick for eventQ assert
Korey Sewell [Tue, 29 Mar 2011 23:36:36 +0000 (19:36 -0400)]
sim: typecast Tick to UTick for eventQ assert

13 years agoPower: Fix compilation.
Gabe Black [Tue, 29 Mar 2011 17:04:19 +0000 (13:04 -0400)]
Power: Fix compilation.

13 years agoThis patch supports cache flushing in MOESI_hammer
Somayeh Sardashti [Mon, 28 Mar 2011 15:49:45 +0000 (10:49 -0500)]
This patch supports cache flushing in MOESI_hammer

13 years agoConfig: Import math in MI_example.py
Nilay Vaish [Mon, 28 Mar 2011 15:49:36 +0000 (10:49 -0500)]
Config: Import math in MI_example.py

13 years agotests: update reference outputs for ruby cache index change
Steve Reinhardt [Sun, 27 Mar 2011 05:24:36 +0000 (22:24 -0700)]
tests: update reference outputs for ruby cache index change

MOESI_CMP_token is the only protocol that showed noticeable stats
differences.

13 years agomips: cleanup ISA-specific code
Korey Sewell [Sat, 26 Mar 2011 13:23:52 +0000 (09:23 -0400)]
mips: cleanup ISA-specific code
***
(1): get rid of expandForMT function
MIPS is the only ISA that cares about having a piece of ISA state integrate
multiple threads so add constants for MIPS and relieve the other ISAs from having
to define this. Also, InOrder was the only core that was actively calling
this function
* * *
(2): get rid of corespecific type
The CoreSpecific type was used as a proxy to pass in HW specific params to
a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense
to not force every other ISA to use CoreSpecific as well use a special
reset function to set it. That probably should go in a PowerOn reset fault
 anyway.

13 years agoruby: fixed cache index setting
Brad Beckmann [Fri, 25 Mar 2011 17:13:50 +0000 (10:13 -0700)]
ruby: fixed cache index setting

13 years agoArm: Add in a missing miscRegName.
Gabe Black [Fri, 25 Mar 2011 04:46:14 +0000 (00:46 -0400)]
Arm: Add in a missing miscRegName.

13 years agoArm: Get rid of unused and incomplete setCp15Register and readCp15Register.
Gabe Black [Thu, 24 Mar 2011 18:39:00 +0000 (14:39 -0400)]
Arm: Get rid of unused and incomplete setCp15Register and readCp15Register.

13 years agoArm: Get rid of the unused copyStringArray32 method from Arm process classes.
Gabe Black [Thu, 24 Mar 2011 18:00:15 +0000 (14:00 -0400)]
Arm: Get rid of the unused copyStringArray32 method from Arm process classes.

13 years agoISA parser: Set up op_src_decl and op_dest_decl for pc operands.
Gabe Black [Thu, 24 Mar 2011 17:55:16 +0000 (13:55 -0400)]
ISA parser: Set up op_src_decl and op_dest_decl for pc operands.

13 years agoThis patch fixes a build error in networktest.cc that occurs with gcc4.2
Tushar Krishna [Wed, 23 Mar 2011 03:38:09 +0000 (23:38 -0400)]
This patch fixes a build error in networktest.cc that occurs with gcc4.2

13 years agoRuby: Remove CacheMsg class from SLICC
Nilay Vaish [Tue, 22 Mar 2011 11:41:54 +0000 (06:41 -0500)]
Ruby: Remove CacheMsg class from SLICC
The goal of the patch is to do away with the CacheMsg class currently in use
in coherence protocols. In place of CacheMsg, the RubyRequest class will used.
This class is already present in slicc_interface/RubyRequest.hh. In fact,
objects of class CacheMsg are generated by copying values from a RubyRequest
object.

13 years agoThis patch makes garnet use the info about active and inactive vnets during allocatio...
Tushar Krishna [Tue, 22 Mar 2011 02:51:59 +0000 (22:51 -0400)]
This patch makes garnet use the info about active and inactive vnets during allocation and power estimations etc

13 years agofix garnet fleible pipeline
Tushar Krishna [Tue, 22 Mar 2011 02:51:59 +0000 (22:51 -0400)]
fix garnet fleible pipeline

13 years agoThis patch adds the network tester for simple and garnet networks.
Tushar Krishna [Tue, 22 Mar 2011 02:51:58 +0000 (22:51 -0400)]
This patch adds the network tester for simple and garnet networks.
The tester code is in testers/networktest.
The tester can be invoked by configs/example/ruby_network_test.py.
A dummy coherence protocol called Network_test is also addded for network-only simulations and testing. The protocol takes in messages from the tester and just pushes them into the network in the appropriate vnet, without storing any state.

13 years agoSLICC: Remove WakeUp* import calls from ast/__init__.py
Nilay Vaish [Sun, 20 Mar 2011 14:23:27 +0000 (09:23 -0500)]
SLICC: Remove WakeUp* import calls from ast/__init__.py
I had recently committed a patch that removed the WakeUp*.py files from the
slicc/ast directory. I had forgotten to remove the import  calls for these
files from slicc/ast/__init__.py. This resulted in error while running
regressions on zizzer. This patch does the needful.

13 years agoconfigs: combine ruby_se.py and se.py to avoid all that code duplication
Lisa Hsu [Sun, 20 Mar 2011 04:13:04 +0000 (21:13 -0700)]
configs: combine ruby_se.py and se.py to avoid all that code duplication

13 years agoenable x86 workloads on se.py
Lisa Hsu [Sun, 20 Mar 2011 04:13:02 +0000 (21:13 -0700)]
enable x86 workloads on se.py

13 years agose.py: Modify script to make multiprogramming much easier.
Lisa Hsu [Sun, 20 Mar 2011 04:12:59 +0000 (21:12 -0700)]
se.py: Modify script to make multiprogramming much easier.
Now, instead of --bench benchname, you can do --bench bench1-bench2-bench3 and it will
set up a simulation that instantiates those three workloads.  Only caveat is that now,
for sanity checking, your -n X must match the number of benches in the list.

13 years agoutil: update aggregator to handle x86 checkpoints.
Lisa Hsu [Sun, 20 Mar 2011 04:12:55 +0000 (21:12 -0700)]
util:  update aggregator to handle x86 checkpoints.
Also, make update to understand some of the newer serialized variables

13 years agoRuby: Convert CacheRequestType to RubyRequestType
Nilay Vaish [Sat, 19 Mar 2011 23:34:59 +0000 (18:34 -0500)]
Ruby: Convert CacheRequestType to RubyRequestType
This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent code makes use of the same request type.

13 years agoRuby: Convert AccessModeType to RubyAccessMode
Nilay Vaish [Sat, 19 Mar 2011 23:34:37 +0000 (18:34 -0500)]
Ruby: Convert AccessModeType to RubyAccessMode
This patch converts AccessModeType to RubyAccessMode so that both the
protocol dependent and independent code uses the same access mode.

13 years agoMOESI_hammer: minor fixes to full-bit dir
Brad Beckmann [Sat, 19 Mar 2011 21:17:48 +0000 (14:17 -0700)]
MOESI_hammer: minor fixes to full-bit dir

13 years agoRuby: dma retry fix
Brad Beckmann [Sat, 19 Mar 2011 21:17:48 +0000 (14:17 -0700)]
Ruby: dma retry fix

This patch fixes the problem where Ruby would fail to call sendRetry on ports
after it nacked the port.  This patch is particularly helpful for bursty dma
requests which often include several packets.

13 years agoRubyPort: minor fixes to trace flag and dprintfs
Brad Beckmann [Sat, 19 Mar 2011 21:17:48 +0000 (14:17 -0700)]
RubyPort: minor fixes to trace flag and dprintfs

13 years agoruby: added useful dma progress dprintf
Brad Beckmann [Sat, 19 Mar 2011 21:17:48 +0000 (14:17 -0700)]
ruby: added useful dma progress dprintf

13 years agoslicc: improved invalid transition message
Brad Beckmann [Sat, 19 Mar 2011 21:17:48 +0000 (14:17 -0700)]
slicc: improved invalid transition message

13 years agoMOESI_hammer: fixed dma bug with shared data
Brad Beckmann [Sat, 19 Mar 2011 21:17:48 +0000 (14:17 -0700)]
MOESI_hammer: fixed dma bug with shared data

13 years agoMOESI_CMP_directory: significant dma bug fixes
Brad Beckmann [Sat, 19 Mar 2011 21:17:48 +0000 (14:17 -0700)]
MOESI_CMP_directory: significant dma bug fixes

13 years agoSLICC: Remove external_type for structures
Nilay Vaish [Fri, 18 Mar 2011 19:12:04 +0000 (14:12 -0500)]
SLICC: Remove external_type for structures
In SLICC, in order to define a type a data type for which it should not
generate any code, the keyword external_type is used. For those data types for
which code should be generated, the keyword structure is used. This patch
eliminates the use of keyword external_type for defining structures. structure
key word can now have an optional attribute external, which would be used for
figuring out whether or not to generate the code for this structure. Also, now
structures can have functions as well data members in them.

13 years agoSLICC: Remove the keyword wake_up_dependents
Nilay Vaish [Fri, 18 Mar 2011 19:12:03 +0000 (14:12 -0500)]
SLICC: Remove the keyword wake_up_dependents
In order to add stall and wait facility for protocols, a keyword
wake_up_dependents was introduced. This patch removes the keyword,
instead this functionality is now implemented as function call.

13 years agoSLICC: Remove the keyword wake_up_all_dependents
Nilay Vaish [Fri, 18 Mar 2011 19:12:01 +0000 (14:12 -0500)]
SLICC: Remove the keyword wake_up_all_dependents
In order to add stall and wait facility for protocols, a keyword
wake_up_all_dependents was introduced. This patch removes the keyword,
instead this functionality is now implemented as function call.

13 years agoswig: get rid of m5.internal.random module (swig/random.i)
Steve Reinhardt [Fri, 18 Mar 2011 18:47:15 +0000 (11:47 -0700)]
swig: get rid of m5.internal.random module (swig/random.i)
Thanks to swig this was interfering with the standard Python
random module.  The only function in that module was seed(),
which erroneously called srand48().  Moved the function to
m5.internal.core, renamed it seedRandom(), and made it call
random_mt.init() instead.

13 years agobase: disable FastAlloc in debug builds by default
Steve Reinhardt [Fri, 18 Mar 2011 18:47:11 +0000 (11:47 -0700)]
base: disable FastAlloc in debug builds by default
FastAlloc's reuse policies can mask allocation bugs, so
we typically want it disabled when debugging.  Set
FORCE_FAST_ALLOC to enable even when debugging, and set
NO_FAST_ALLOC to disable even in non-debug builds.

13 years agoAutomated merge with ssh://hg@repo.m5sim.org/m5
Ali Saidi [Fri, 18 Mar 2011 00:24:37 +0000 (19:24 -0500)]
Automated merge with ssh://hg@repo.m5sim.org/m5

13 years agoARM: Update stats for the previous changes and add ARM_FS/O3 regression.
Ali Saidi [Fri, 18 Mar 2011 00:20:22 +0000 (19:20 -0500)]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.

13 years agoARM: Add minimal ARM_SE support for m5threads.
Chris Emmons [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
ARM: Add minimal ARM_SE support for m5threads.

Updated some of the assembly code sequences to use armv7 instructions and
coprocessor 15 for storing the TLS pointer.

13 years agoARM: Fix subtle bug in LDM.
Ali Saidi [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
ARM: Fix subtle bug in LDM.

If the instruction faults mid-op the base register shouldn't be written back.

13 years agoARM: Implement the Instruction Set Attribute Registers (ISAR).
Ali Saidi [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
ARM: Implement the Instruction Set Attribute Registers (ISAR).

The ISAR registers describe which features the processor supports.
Transcribe the values listed in section B5.2.5 of the ARM ARM
into the registers as read-only values

13 years agoARM: Identify branches as conditional or unconditional and direct or indirect.
Ali Saidi [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
ARM: Identify branches as conditional or unconditional and  direct or indirect.

13 years agoARM: Bare metal system should have 256MB of RAM.
Ali Saidi [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
ARM: Bare metal system should have 256MB of RAM.

13 years agoARM: Fix small bug with VLDM/VSTM instructions.
Ali Saidi [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
ARM: Fix small bug with VLDM/VSTM instructions.

13 years agoARM: Detect and skip udelay() functions in linux kernel.
Ali Saidi [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
ARM: Detect and skip udelay() functions in linux kernel.

This change speeds up booting, especially in MP cases, by not executing
udelay() on the core but instead skipping ahead tha amount of time that is being
delayed.

13 years agoARM: Allow conditional quiesce instructions.
Ali Saidi [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
ARM: Allow conditional quiesce instructions.

This patch prevents not executed conditional instructions marked as
IsQuiesce from stalling the pipeline indefinitely. If the instruction
is not executed the quiesceSkip psuedoinst is called which schedules a
wakes up call to the fetch stage.

13 years agoStats: Update the statistics for rfe patch.
Ali Saidi [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
Stats: Update the statistics for rfe patch.

13 years agoARM: Fix RFE macrop.
Matt Horsnell [Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)]
ARM: Fix RFE macrop.

This changes the RFE macroop into 3 microops:

URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack
sp = sp + offset;         // optionally auto-increment
PC = URa; CPSR = URb;     // write to the PC and CPSR.

Importantly:
- writing to PC is handled in the last micro-op.
- loading occurs prior to state changes.

13 years agoARM: Rename registers used as temporary state by microops.
Matt Horsnell [Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)]
ARM: Rename registers used as temporary state by microops.

13 years agoO3: Send instruction back to fetch on squash to seed predecoder correctly.
Ali Saidi [Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)]
O3: Send instruction back to fetch on squash to seed predecoder correctly.

13 years agoO3: Cleanup the commitInfo comm struct.
Ali Saidi [Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)]
O3: Cleanup the commitInfo comm struct.

Get rid of unused members and use base types rather than derrived values
where possible to limit amount of state.

13 years agoARM: Previous change didn't end up setting instFlags, this does.
Ali Saidi [Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)]
ARM: Previous change didn't end up setting instFlags, this does.

13 years agoO3: Update regressions for mem block caching change.
Ali Saidi [Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)]
O3: Update regressions for mem block caching change.

13 years agoMem: Fix issue with dirty block being lost when entire block transferred to non-cache.
Ali Saidi [Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)]
Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.

This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.

13 years agoO3: Fix unaligned stores when cache blocked
Ali Saidi [Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)]
O3: Fix unaligned stores when cache blocked

Without this change the a store can be issued to the cache multiple times.
If this case occurs when the l1 cache is out of mshrs (and thus blocked)
the processor will never make forward progress because each cycle it will
send a single request using the recently freed mshr and not completing the
multipart store. This will continue forever.

13 years agoRuby: minor bugfix, line did not adhere to some macro usage conventions.
Lisa Hsu [Fri, 18 Mar 2011 00:08:35 +0000 (17:08 -0700)]
Ruby: minor bugfix, line did not adhere to some macro usage conventions.

13 years agoRuby: expose a simple mod function in slicc interface.
Lisa Hsu [Fri, 18 Mar 2011 00:01:41 +0000 (17:01 -0700)]
Ruby: expose a simple mod function in slicc interface.

13 years agoX86: Update the stats for parser on x86 O3.
Ali Saidi [Thu, 17 Mar 2011 04:43:54 +0000 (00:43 -0400)]
X86: Update the stats for parser on x86 O3.

13 years agoX86: Update the stats for gzip on x86 O3.
Gabe Black [Thu, 17 Mar 2011 02:08:41 +0000 (19:08 -0700)]
X86: Update the stats for gzip on x86 O3.

13 years agoRegressions: Move the X86_FS regressions to "quick" instead of "long".
Gabe Black [Sat, 12 Mar 2011 22:41:30 +0000 (14:41 -0800)]
Regressions: Move the X86_FS regressions to "quick" instead of "long".

--HG--
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal

13 years agoRegressions: Make X86_FS run automatically.
Gabe Black [Sat, 12 Mar 2011 22:38:57 +0000 (14:38 -0800)]
Regressions: Make X86_FS run automatically.

13 years agoSCons: Stop embedding the mercurial revision into the binary.
Gabe Black [Fri, 11 Mar 2011 19:27:36 +0000 (11:27 -0800)]
SCons: Stop embedding the mercurial revision into the binary.

This causes a lot of rebuilds that could have otherwise possibly been
avoided, and, more annoyingly, a lot of unnecessary rerunning of the
regressions. The benefits of having the revision in the output haven't
materialized, so this change removes it.

13 years agoGems: Eliminate the now unused GEMS_ROOT scons variable.
Gabe Black [Fri, 11 Mar 2011 19:27:26 +0000 (11:27 -0800)]
Gems: Eliminate the now unused GEMS_ROOT scons variable.

13 years agoRuby: Get rid of the dead ruby tester.
Gabe Black [Fri, 11 Mar 2011 19:27:16 +0000 (11:27 -0800)]
Ruby: Get rid of the dead ruby tester.

None of the code in the ruby tester directory is compiled or referred to
outside of that directory. This change eliminates it. If it's needed in the
future, it can be revived from the history. In the mean time, this removes
clutter and the only use of the GEMS_ROOT scons variable.

13 years agoAlpha: Fix the datatypes of some values read from the simulated kernel.
Yi Xiang [Wed, 9 Mar 2011 05:43:11 +0000 (21:43 -0800)]
Alpha: Fix the datatypes of some values read from the simulated kernel.

13 years agoSCons: Fix the polarity on the --ignore-style check.
Gabe Black [Fri, 4 Mar 2011 08:11:02 +0000 (00:11 -0800)]
SCons: Fix the polarity on the --ignore-style check.

13 years agoSCons: Clean up some inconsistent capitalization in scons options.
Gabe Black [Fri, 4 Mar 2011 07:55:21 +0000 (23:55 -0800)]
SCons: Clean up some inconsistent capitalization in scons options.

13 years agoSCons: Turn some scons variables into command line options.
Gabe Black [Fri, 4 Mar 2011 07:54:31 +0000 (23:54 -0800)]
SCons: Turn some scons variables into command line options.

13 years agoMips: MIPS_FS doesn't build currently, so delete it to avoid confusion.
Gabe Black [Fri, 4 Mar 2011 07:01:38 +0000 (23:01 -0800)]
Mips: MIPS_FS doesn't build currently, so delete it to avoid confusion.

MIPS_FS doesn't build and presumably doesn't work right now. Users might see
the MIP_FS file in build_opts and expect it to work. To avoid confusion, this
change deletes that file.

13 years agoStatetrace: Stub out the missing i386 version of sendState.
Gabe Black [Thu, 3 Mar 2011 06:53:11 +0000 (22:53 -0800)]
Statetrace: Stub out the missing i386 version of sendState.

13 years agoStatetrace: Rename i386 to i686.
Gabe Black [Thu, 3 Mar 2011 06:53:11 +0000 (22:53 -0800)]
Statetrace: Rename i386 to i686.

--HG--
rename : util/statetrace/arch/i386/tracechild.cc => util/statetrace/arch/i686/tracechild.cc
rename : util/statetrace/arch/i386/tracechild.hh => util/statetrace/arch/i686/tracechild.hh

13 years agoStatetrace: Fix the i686 detection macro.
Gabe Black [Thu, 3 Mar 2011 06:53:11 +0000 (22:53 -0800)]
Statetrace: Fix the i686 detection macro.