Florent Kermarrec [Thu, 16 Jan 2020 09:14:42 +0000 (10:14 +0100)]
targets: cleanup EthernetSoC
Florent Kermarrec [Thu, 16 Jan 2020 08:46:54 +0000 (09:46 +0100)]
soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty.
Florent Kermarrec [Thu, 16 Jan 2020 08:11:44 +0000 (09:11 +0100)]
targets/arty: add EtherboneSoC
Florent Kermarrec [Wed, 15 Jan 2020 12:17:59 +0000 (13:17 +0100)]
targets/kcu105: update
Florent Kermarrec [Wed, 15 Jan 2020 12:09:03 +0000 (13:09 +0100)]
test/test_targets: update
Florent Kermarrec [Tue, 14 Jan 2020 08:23:30 +0000 (09:23 +0100)]
SoCCore: set default integrated_rom/ram_size to 0. For targets, defaults values are provided by soc_core_args.
Florent Kermarrec [Mon, 13 Jan 2020 19:01:45 +0000 (20:01 +0100)]
SoCCore: use hex for integrated_rom/sram_size
enjoy-digital [Mon, 13 Jan 2020 18:57:59 +0000 (19:57 +0100)]
Merge pull request #339 from gsomlo/gls-csr-cleanup
CSR Improvements and Cleanup
Florent Kermarrec [Mon, 13 Jan 2020 16:39:23 +0000 (17:39 +0100)]
tools/litex_sim: use default integrated_rom_size
Florent Kermarrec [Mon, 13 Jan 2020 15:58:00 +0000 (16:58 +0100)]
cores/uart/UARTInterface: remove connect method
Florent Kermarrec [Mon, 13 Jan 2020 15:56:31 +0000 (16:56 +0100)]
soc_core: fix uart stub
Gabriel Somlo [Sun, 12 Jan 2020 00:38:15 +0000 (19:38 -0500)]
bios/sdram: switch to updated CSR accessors, and misc. cleanup
Revert to treating SDRAM_DFII_PIX_[RD|WR]DATA CSRs as arrays
of bytes, but use the new uintX_t array accessors for improved
legibility, and to avoid unnecessary byteswapping.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Gabriel Somlo [Wed, 18 Dec 2019 20:53:21 +0000 (15:53 -0500)]
software, integration/export: rename and reimplement CSR accessors
Implement CSR accessors for all standard integer types and
combinations of subregister alignments (32 or 64 bit) and
sizes (i.e., csr_data_width 8, 16, or 32).
Rename accessors to better reflect the size of the register
being accessed, and correspondingly update the generation
of "csr.h" in "export.py".
Additionally, provide read/write accessors that superimpose arrays
of standard unsigned C types over a CSR register (which may itself
be spread across multiple subregisters).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Florent Kermarrec [Mon, 13 Jan 2020 15:02:32 +0000 (16:02 +0100)]
cpu/vexriscv: revert mem_map_linux/main_ram
Florent Kermarrec [Mon, 13 Jan 2020 13:59:17 +0000 (14:59 +0100)]
SoCCore: set integrated rom/sram size default values in soc_core_args and use it in targets
Florent Kermarrec [Mon, 13 Jan 2020 13:40:26 +0000 (14:40 +0100)]
cpu/vexriscv/mem_map_linux: update main_ram to 0x40000000
Florent Kermarrec [Mon, 13 Jan 2020 13:39:45 +0000 (14:39 +0100)]
targets/genesys2: update self.register_sdram
Florent Kermarrec [Mon, 13 Jan 2020 12:00:17 +0000 (13:00 +0100)]
soc_sdram: add l2_data_width parameter to set minimal l2_data_width to improve DRAM accesses efficiency.
Florent Kermarrec [Mon, 13 Jan 2020 09:14:38 +0000 (10:14 +0100)]
cores/uart: add UARTCrossover
Florent Kermarrec [Mon, 13 Jan 2020 08:20:40 +0000 (09:20 +0100)]
cores/uart/UART: add stream interface (phy=None), add connect method and use this for UART Stub/Crossover.
A bridged/crossover UART can now just be created by:
- passing uart_name="stream" to SoCCore/SoCSDRAM.
- adding a crossover UART core to the design:
# UART Crossover (over Wishbone Bridge
from litex.soc.cores.uart import UART
self.submodules.uart_xover = UART(tx_fifo_depth=2, rx_fifo_depth=2)
self.add_csr("uart_xover")
self.comb += self.uart.connect(self.uart_xover)
Florent Kermarrec [Sun, 12 Jan 2020 21:06:35 +0000 (22:06 +0100)]
gen/fhdl/verilog: fix signed init values
enjoy-digital [Sun, 12 Jan 2020 20:18:23 +0000 (21:18 +0100)]
Merge pull request #338 from DurandA/master
Add optional 'ignore-loops' flag to nextpnr
Florent Kermarrec [Sun, 12 Jan 2020 20:11:44 +0000 (21:11 +0100)]
cores/uart: rename BridgedUART to UARTEmulator and rework/simplify it. Also integrated it in SoCCore with uart_name="emulator"
enjoy-digital [Sun, 12 Jan 2020 19:40:27 +0000 (20:40 +0100)]
Merge pull request #340 from xobs/bridged-uart
uart: add BridgedUart
Sean Cross [Sun, 12 Jan 2020 09:52:42 +0000 (19:52 +1000)]
uart: add BridgedUart
This version of the UART adds a second, compatible UART after
the first. This maintians software compatibility, and allows a
program running on the other side of the litex bridge to act as
a terminal emulator by manually reading and writing the second
UART.
Signed-off-by: Sean Cross <sean@xobs.io>
Arnaud Durand [Fri, 10 Jan 2020 15:06:08 +0000 (16:06 +0100)]
Add optional 'ignore-loops' flag to nextpnr
Florent Kermarrec [Fri, 10 Jan 2020 13:25:46 +0000 (14:25 +0100)]
bios/sdram: add memspeed
Florent Kermarrec [Fri, 10 Jan 2020 11:52:14 +0000 (12:52 +0100)]
wishbone/Cache: avoid REFILL_WRTAG state to improve speed.
Florent Kermarrec [Fri, 10 Jan 2020 07:49:23 +0000 (08:49 +0100)]
soc/cores/cpu: add riscv64-linux toolchain support for risc-v cpus.
Toolchain can be downloaded from https://toolchains.bootlin.com/
Florent Kermarrec [Thu, 9 Jan 2020 20:12:00 +0000 (21:12 +0100)]
targets: sync with litex-boards
Florent Kermarrec [Thu, 9 Jan 2020 18:45:51 +0000 (19:45 +0100)]
build/altera/quartus: allow multiple call of add_period_constraint if constraint is similar.
Similar to the changes already applied to Xilinx backend.
enjoy-digital [Thu, 9 Jan 2020 12:24:17 +0000 (13:24 +0100)]
Merge pull request #337 from gregdavill/spi-flash
soc/cores/spi_flash: Don't tristate DQ2/DQ3 when bitbanging
Greg Davill [Thu, 9 Jan 2020 11:23:00 +0000 (21:53 +1030)]
soc/cores/spi_flash: Don't tristate DQ2/DQ3 when bitbanging
Florent Kermarrec [Thu, 9 Jan 2020 10:03:17 +0000 (11:03 +0100)]
platforms/minispartan6: rename sd to sdcard and regroup data lines
Florent Kermarrec [Thu, 9 Jan 2020 10:00:54 +0000 (11:00 +0100)]
platforms/nexys4ddr: add sdcard pins
Florent Kermarrec [Wed, 8 Jan 2020 18:38:27 +0000 (19:38 +0100)]
build/lattice/trellis: use a single fonction to parse device
enjoy-digital [Wed, 8 Jan 2020 18:17:04 +0000 (19:17 +0100)]
Merge pull request #336 from kbeckmann/trellis-speed
trellis: Pass speed argument to nextpnr
Konrad Beckmann [Tue, 7 Jan 2020 22:15:13 +0000 (23:15 +0100)]
trellis: Pass speed grade argument to nextpnr
enjoy-digital [Mon, 6 Jan 2020 17:09:12 +0000 (18:09 +0100)]
Merge pull request #331 from betrusted-io/xadc_mods
WIP: add support for DRP on XADC
Florent Kermarrec [Mon, 6 Jan 2020 15:28:48 +0000 (16:28 +0100)]
soc/cores/xadc: define analog_layout and simplify analog_pads connections
bunnie [Mon, 6 Jan 2020 13:47:58 +0000 (21:47 +0800)]
bring back analog_pads specifier, remove reset conditions on VP
For the "P" side of the analog channels, actually, connecting
a digital line to them has "no meaning". The docs say that
either you connect an analog pin to a pad, or vivado "ties it off
appropriately". I wish it were the case that tying a pin to 0 or 1
would actually connect it to a power or ground, because it means
that even in unipolar mode you have to burn two pins to break out
the signal of interest *and* the ground reference analog pad
(I thought I could just connect it to "0" and the pin would be
grounded, but that doesn't happen -- it's just ignored if it's
not wired to a pad).
For the pad specifier, is it OK to leave it with an optional
argument of analog_pads=None? I tried assigning to the
self.analog property after instantiation, but this doesn't
seem to work, the default values are preferred. It looks like
if you don't want to do the analog_pads= optional argument
the other way to do it would be to add code on the instiating
module that tampers with the properties of the instance directly,
but I think that's sort of ugly.
Also, I noticed you stripped out the layout specifier for
the analog_pads. I thought it would be nice to provide that
in the file, so the caller doesn't have to infer what the
pad layout is by reading the code...what's the motivation for
removing that?
Florent Kermarrec [Sun, 5 Jan 2020 20:04:13 +0000 (21:04 +0100)]
cpu/minerva: fix variant syntax warning
Florent Kermarrec [Sat, 4 Jan 2020 22:59:04 +0000 (23:59 +0100)]
soc/core/xadc: cleanup, simplify and add expose_drp method - keep CSR ordering with older version, requested for software compatibility. - always enable analog capability (user will just not use it if not needed). - add expose_drp method (similar to clock.py) for cases where DRP is needed.
enjoy-digital [Sat, 4 Jan 2020 18:19:38 +0000 (19:19 +0100)]
Merge pull request #332 from gsomlo/gls-csr-mem-sel
interconnect/csr_bus/SRAM: allow 64-bit alignment (on 64-bit CPUs)
Gabriel Somlo [Fri, 3 Jan 2020 21:27:44 +0000 (16:27 -0500)]
interconnect/csr_bus/SRAM: allow 64-bit alignment (on 64-bit CPUs)
Similarly to how CSRBank subregisters are aligned to the CPU word
width (see commit
f4770219f), ensure SRAM word_bits are also aligned
to the CPU word width.
Additionally, fix the MMPTR() macro to access CSR subregisters as
CPU word (unsigned long) sized slices.
This fixes the functionality of the 'ident' bios command on 64-bit
CPUs (e.g., Rocket).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
bunnie [Fri, 3 Jan 2020 19:03:59 +0000 (03:03 +0800)]
fix a couple bugs in the DRP readout path
I'm now getting data out via DRP. Still some TODOs, but
progress.
bunnie [Fri, 3 Jan 2020 16:25:09 +0000 (00:25 +0800)]
add support for DRP on XADC
The design is backward-compatible in functionality for users
who don't want to use DRP. That is, on power on, the XADC will
scan the supply and temperature and store them in CSRs.
If drp_enable is set, the scanning stops, and the XADC is now
controlled by the DRP bus.
Wher drp_enable is reset, the XADC may return to an auto-sample
mode, but only if the internal registers are configured to do this.
If you return to drp_enable without, for example, turning on
the continuous sequence and setting which channels to check,
the results will be unpredictable (mostly either it'll scan just
once and stop, or it'll not scan all the channels, depending on
the register settings).
At this point, the backward compatibility was confirmed in testing,
the DRP API is still a work in progress as the application this
is being developed for needs to support fun stuff like real time
sampling of signals to a buffer.
Down the road, this block may have to be modified again to support an
output FIFO, so we're not railing the CPU trying to do real time
sampling of ADC data. This will probably be added as a True/False flag
of some sort in the parameter list, because the FIFO will be expensive
as far as BRAM goes to implement and applications that don't need the
FIFO buffer can probably use that BRAM for better things.
Florent Kermarrec [Fri, 3 Jan 2020 14:29:10 +0000 (15:29 +0100)]
cpu/microwatt: reorder sources, add comments
Florent Kermarrec [Thu, 2 Jan 2020 09:23:05 +0000 (10:23 +0100)]
build/lattice/icestorm: increase similarities with trellis.
Florent Kermarrec [Thu, 2 Jan 2020 08:41:47 +0000 (09:41 +0100)]
soc/integration/soc_core/SoCController: specify initial reset value of scratch register in description
Florent Kermarrec [Thu, 2 Jan 2020 08:38:23 +0000 (09:38 +0100)]
soc/integration/soc_core/SoCController: rephrase CSR descriptions a bit
enjoy-digital [Thu, 2 Jan 2020 08:26:35 +0000 (09:26 +0100)]
Merge pull request #330 from xobs/document-ctrl-timer0
Document CTRL and fix TIMER0 Documentation
Sean Cross [Thu, 2 Jan 2020 08:24:12 +0000 (16:24 +0800)]
cores: timer: clean up wording for timer documentation
This fixes some formatting errors with the timer documentation, such as
the lack of a space between the first and second sentences. It also
fixes some grammar for documentation of various fields.
Signed-off-by: Sean Cross <sean@xobs.io>
Sean Cross [Thu, 2 Jan 2020 07:37:45 +0000 (15:37 +0800)]
soc_core: ctrl: document registers
This adds a small amount of documentation to the three registers present
inside the `CTRL` module.
Signed-off-by: Sean Cross <sean@xobs.io>
Sean Cross [Thu, 2 Jan 2020 07:36:35 +0000 (15:36 +0800)]
cores: timer: fix documentation formatting
The ReStructured Text used was not properly formatted, resulting in
confusing and broken output. This corrects the output and lets it
format correctly when using sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
Florent Kermarrec [Wed, 1 Jan 2020 12:24:06 +0000 (13:24 +0100)]
soc/cores/clock: also allow margin=0 on iCE40PLL and ECP5PLL
enjoy-digital [Wed, 1 Jan 2020 12:20:15 +0000 (13:20 +0100)]
Merge pull request #328 from betrusted-io/precise_clocks
add the possibility for a "precise" clock solution
bunnie [Wed, 1 Jan 2020 10:49:00 +0000 (18:49 +0800)]
add the possibility for a "precise" clock solution
If clocks and multipliers are planned well, we can have
a zero-error solution for clocks. Suggest to change < to <= in
margin comparison loop, so that a "perfect" solution is allowed
to converge.
Florent Kermarrec [Tue, 31 Dec 2019 09:33:12 +0000 (10:33 +0100)]
build/microsemi/libero_soc: update add_period_constraint behavior when clock is already constrainted.
Florent Kermarrec [Tue, 31 Dec 2019 09:32:09 +0000 (10:32 +0100)]
build/xilinx/vivado: update add_period_constraint behavior when clock is already constrainted.
Florent Kermarrec [Tue, 31 Dec 2019 09:25:51 +0000 (10:25 +0100)]
build/lattice/icestorm/add_period_constraint: improve
- store period in ns.
- pass clocks to_build_pre_pack and do the convertion to MHz there.
- improve error message.
Florent Kermarrec [Tue, 31 Dec 2019 08:58:26 +0000 (09:58 +0100)]
soc/integration/builder: avoid try/except on LiteDRAM import, just check if SoC has an sdram and do the import if so
enjoy-digital [Tue, 31 Dec 2019 08:49:53 +0000 (09:49 +0100)]
Merge pull request #327 from zakgi/master
moving RAM offsets outside of CSR_ETHMAC define
Tim 'mithro' Ansell [Mon, 30 Dec 2019 18:25:14 +0000 (19:25 +0100)]
Allow specifying the same clock constraint multiple times.
(As long as the clock values actually match.)
Tim 'mithro' Ansell [Mon, 30 Dec 2019 18:24:26 +0000 (19:24 +0100)]
Allow LiteX builder to be used without LiteDRAM.
Tim 'mithro' Ansell [Mon, 30 Dec 2019 15:10:57 +0000 (16:10 +0100)]
Improve the invalid CPU type error message.
Florent Kermarrec [Mon, 30 Dec 2019 09:07:08 +0000 (10:07 +0100)]
build/xilinx/programmer: fix vivado_cmd when settings are sourced manually.
Giammarco Zacheo [Mon, 30 Dec 2019 06:56:42 +0000 (22:56 -0800)]
moving RAM offsets outside of CSR_ETHMAC define
enjoy-digital [Sat, 21 Dec 2019 20:31:04 +0000 (21:31 +0100)]
Merge pull request #321 from gsomlo/gls-rocket-aximem-wide
cpu/rocket: variants with double (128b) and quad (256b) wide mem_axi
enjoy-digital [Sat, 21 Dec 2019 20:30:09 +0000 (21:30 +0100)]
Merge pull request #319 from DurandA/feature-integer-attributes
Add integer attributes
Gabriel Somlo [Fri, 29 Nov 2019 23:42:54 +0000 (18:42 -0500)]
cpu/rocket: variants with double (128b) and quad (256b) wide mem_axi
Various development boards' LiteDRAM ports may have native data
widths of either 64 (nexys4ddr), 128 (versa5g), or 256 (trellis)
bits. Add Rocket variants configured with mem_axi ports of matching
data widths, so that a point to point connection between the CPU's
memory port and LiteDRAM can be accomplished without any additional
data width conversion gateware.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
enjoy-digital [Sat, 21 Dec 2019 18:40:21 +0000 (19:40 +0100)]
Merge pull request #320 from gsomlo/gls-touch-up
Misc. Rocket and CSR cleanup
Gabriel Somlo [Wed, 18 Dec 2019 16:24:11 +0000 (11:24 -0500)]
soc_core: csr_alignment assertions
Enforce the condition that csr_alignment be either 32 or 64 when
requested explicitly when initializing SoCCore().
Additionally, if a CPU is specified, enforce that csr_alignment be
equal to the native CPU word size (currently either 32 or 64), and
warn the caller if an alignment value *higher* than the CPU native
word size was explicitly requested.
In conclusion, if a CPU is specified, then csr_alignment should be
assumed to equal 8*sizeof(unsigned long).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Gabriel Somlo [Sat, 21 Dec 2019 17:59:19 +0000 (12:59 -0500)]
cpu/rocket: access PLIC registers via pointer dereference
Since the PLIC is internal to Rocket, access its registers
directly via pointer dereference, rather than through the
LiteX CSR Bus accessors (which assume subregister slicing,
and are therefore inappropriate for registers NOT accessed
over the LiteX CSR Bus).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Florent Kermarrec [Fri, 20 Dec 2019 22:32:21 +0000 (23:32 +0100)]
cpu/microwatt: add initial software support
Arnaud Durand [Thu, 19 Dec 2019 08:03:12 +0000 (09:03 +0100)]
Add integer attributes
Arnaud Durand [Thu, 19 Dec 2019 07:53:44 +0000 (08:53 +0100)]
Revert "gen/fhdl/verilog: allow single element verilog inline attribute"
This reverts commit
b845755995a8517d8e0ffa86156fb5577201f7d4.
Florent Kermarrec [Wed, 18 Dec 2019 18:02:30 +0000 (19:02 +0100)]
cpu/microwatt: add submodule
Florent Kermarrec [Wed, 18 Dec 2019 07:59:35 +0000 (08:59 +0100)]
cpu/microwatt: set csr to 0xc0000000 (IO region)
Florent Kermarrec [Wed, 18 Dec 2019 07:56:36 +0000 (08:56 +0100)]
cpu/microwatt: fix add_source/add_sources
Florent Kermarrec [Wed, 18 Dec 2019 07:46:38 +0000 (08:46 +0100)]
soc/cores/pwm: remove debug print(n)
Florent Kermarrec [Tue, 17 Dec 2019 08:47:31 +0000 (09:47 +0100)]
platforms/netv2: add xc7a100t support
Florent Kermarrec [Tue, 17 Dec 2019 08:47:12 +0000 (09:47 +0100)]
platforms/minispartan6: add assert on available devices
Florent Kermarrec [Tue, 17 Dec 2019 08:41:46 +0000 (09:41 +0100)]
cpu/microwatt: simplify add_sources
Florent Kermarrec [Tue, 17 Dec 2019 08:33:46 +0000 (09:33 +0100)]
cpu/microwatt: add io_regions and gcc_flags
Florent Kermarrec [Tue, 17 Dec 2019 08:27:19 +0000 (09:27 +0100)]
cpu/microwatt: update copyright
Florent Kermarrec [Mon, 16 Dec 2019 11:37:27 +0000 (12:37 +0100)]
cpu/microwatt: drive stall signal (no burst support)
Florent Kermarrec [Mon, 16 Dec 2019 10:13:10 +0000 (11:13 +0100)]
soc/cores/pwm: add clock_domain support
Florent Kermarrec [Mon, 16 Dec 2019 10:12:38 +0000 (11:12 +0100)]
build/xilinx/XilinxMultiRegImpl: fix n=0 case
Florent Kermarrec [Sat, 14 Dec 2019 21:47:07 +0000 (22:47 +0100)]
build/xilinx/ise: cleanup/simplify pass, remove mist support (not aware of anyone using it)
Florent Kermarrec [Fri, 13 Dec 2019 22:58:14 +0000 (23:58 +0100)]
soc/cores/cpu: add initial Microwatt gateware support
Implementation tested on arty:
cd litex/soc/cores/cpu/microwatt
git clone https://github.com/antonblanchard/microwatt
mv microwatt sources
cd litex/boards/targets
./arty --cpu-type=microwatt --no-compile-gateware
Florent Kermarrec [Fri, 13 Dec 2019 22:44:07 +0000 (23:44 +0100)]
soc/cores/cpu/minerva: add self.reset to i_rst
enjoy-digital [Fri, 13 Dec 2019 20:57:14 +0000 (21:57 +0100)]
Merge pull request #315 from gsomlo/gls-csr-assert
soc_core: additional CSR safety assertions
Gabriel Somlo [Thu, 12 Dec 2019 14:02:47 +0000 (09:02 -0500)]
soc_core: additional CSR safety assertions
Since csr_data_width=64 has probably never worked properly, remove
it as one of the possible options (to be fixed and re-added later).
Add csr_data_width=16, which has been tested and does work.
Additionally, ensure csr_data_width <= csr_alignment (we should not
attempt to create (sub)registers larger than the CPU's native word
size or XLen).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Florent Kermarrec [Thu, 12 Dec 2019 11:41:25 +0000 (12:41 +0100)]
soc_core: remove static 16MB csr region allocation (use csr_address_width to allocate the correct size)
Florent Kermarrec [Thu, 12 Dec 2019 10:27:56 +0000 (11:27 +0100)]
soc_core: add sort of CSR regions by origin (allow csr.h/csr.csv to be ordered by origin)
Florent Kermarrec [Mon, 9 Dec 2019 18:25:38 +0000 (19:25 +0100)]
cores/8b10b: use real Memory for 6b5b table (to improve timings on ECP5)
Florent Kermarrec [Sun, 8 Dec 2019 11:19:38 +0000 (12:19 +0100)]
build/xilinx/vivado: move build_script generation
Florent Kermarrec [Sun, 8 Dec 2019 11:08:17 +0000 (12:08 +0100)]
build/xilinx/vivado: cleanup/simplify
Florent Kermarrec [Sat, 7 Dec 2019 20:43:15 +0000 (21:43 +0100)]
build/lattice/icestorm: cleanup/simplify (and remove arachne-pnr support)