anv/multialloc: Add new add_size helper

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

compiler/blob: Make some parameters void instead of uint8_t

There are certain advantages to using uint8_t internally such as
well-defined arithmetic on all platforms.  However, interfaces that
work in terms of raw data should use a void* type.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

compiler/blob: Constify the reader

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

compiler/blob: Add (reserve|overwrite)_(uint32|intptr) helpers

These helpers not only call blob_reserve_bytes but also make sure that
the blob is properly aligned as if blob_write_* were called.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

compiler/blob: make blob_reserve_bytes() more useful

Despite the name, it could only be used if you immediately wrote to the
pointer. Noboby was using it outside of one test, so clearly this
behavior wasn't that useful. Instead, make it return an offset into the
data buffer so that the result isn't invalidated if you later write to
the blob. In conjunction with blob_overwrite_bytes(), this will be
useful for leaving a placeholder and then filling it in later, which
we'll need to do for handling phi nodes when serializing NIR.

v2 (Jason Ekstrand):
 - Detect overflow in the offset + to_write computation

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

compiler/blob: Allow for fixed-size blobs with a NULL data pointer

These can be used to easily count up the number of bytes that will be
required by "writing" it into the NULL blob.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

compiler/blob: Add a concept of a fixed-allocation blob

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

compiler/blob: Switch to init/finish instead of create/destroy

There's no reason why that tiny bit of memory needs to be on the heap.
We always put blob_reader on the stack, so why not do the same with the
writable blob.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

compiler: Move blob up a level

We're going to want to use the blob for Vulkan pipeline caching so it
makes sense to have it in libcompiler not libglsl.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

meson: Add inc_compiler to the libglsl includes

glsl/blob: Return false from grow_to_fit if we've ever failed

Otherwise we could have a failure followed by a smaller write that
succeeds and get a corrupted blob.  If we ever OOM, we should stop.

v2 (Jason Ekstrand):
 - Initialize the new boolean member in create_blob

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: mesa-stable@lists.freedesktop.org

glsl/blob: Return false from ensure_can_read on overrun

Otherwise, if you have a large read fail and then try to do a small
read, the small read may succeed even though it's at the wrong offset.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: mesa-stable@lists.freedesktop.org

i965: Share the flush for brw_blorp_miptree_download into a pbo

As all users of brw_blorp_miptree_download() must emit a full pipeline
and cache flush when targetting a user PBO (as that PBO may then be
subsequently bound or *be* bound anywhere and outside of the driver
dirty tracking) move that flush into brw_blorp_miptree_download()
itself.

v2 (Ken): Rebase without userptr stuff so it can land sooner.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

meta: Delete the PBO texture upload/download path

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Use blorp instead of meta for PBO pixel reads

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Use blorp instead of meta for PBO texture downloads

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/tex: Use blorp texture upload for all CCS_E textures

This improves the FillTex benchmark in GLBench 2.7 by 30% on my Broxton.
On Ken's Broxton which only has single-channel ram, it improves by 210%.

v2 (Ken): Check mt->aux_usage == ISL_AUX_USAGE_CCS_E rather than using
          intel_miptree_is_lossless_compressed().

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Use blorp instead of meta for PBO texture uploads

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add blorp-based texture upload and download paths

v1 (Topi Pohjolainen): original patch.

v2 (Topi Pohjolainen):
   - Fix return value (s/MESA_FORMAT_NONE/false/) (Anuj)
   - Move _mesa_tex_format_from_format_and_type() just
     in the end avoiding additional if-block (Anuj)
   - Explain better the array alignment restriction (Anuj)
   - Do not bail out in case of gl_pixelstore_attrib::ImageHeight,
     it is handled by _mesa_image_offset() automatically (Ken).
   - Support 1D_ARRAY by flipping depth, width and y, z (Ken).

v3 (Topi Pohjolainen):
   - Contrary to v2, do not try to handle
     gl_pixelstore_attrib::ImageHeight. Currently there are no
     tests in piglit or cts for it. One could possibly copy or
     modify tests/texturing/texsubimage.c. There, however, seems
     to be number of corner cases to consider. Moreover, current
     meta path applies the packing height for both source and
     targets when determining the offset. This would probably
     require re-visiting also.

v4 (Topi Pohjolainen): Rebased on top of merged drm-bacon

v5 (Jason Ekstrand):
   - Move to brw_blorp.c
   - Significant refactoring
   - Fixed 1-D array textures
   - Simplified handling of PBOs vs. CPU data.
   - Handle gl_pixelstore_attrib::ImageHeight.  It turns out there are
     piglit tests that cover this. The original version was failing them
     because of an error in the way it handled 1-D array textures.
   - Add support for texture download

v6 (Kenneth Graunke): Rebase fixes:
   - Use intel_miptree_check_level_layer instead of deleted fields
   - Update for mesa_format_supports_render[] rename.
   - Pass 'false' (read-only) to intel_bufferobj_buffer

v7 (Kenneth Graunke):
   - Fix brw_blorp_download_miptree to pass 'false' (not read only) for
     the destination buffer (caught by Chris Wilson).
   - Fix blorp_get_client_bo to pass intel_bufferobj_buffer !read_only
     for the 'writable' parameter instead of 'false' (caught by Jason).
   - Support GL_BGR, GL_BGRA, GL_BGRA_INTEGER, GL_BGR_INTEGER, allowing
     us to use this for ReadPixels on the window system buffer (caught
     by Chris Wilson).
   - Fix y-flipping bugs in download path (exposed by BGRA support).
   - Fix false vs. NULL return value in blorp_get_client_bo.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Refactor y-flipping coordinate transform.

I want to reuse it for the BLORP download path.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/tex: Check if there is data to upload up-front

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/barrier: Do the correct flushes for framebuffer access

Framebuffer access includes framebuffer reads so we need to invalidate
the texture cache.  We do not, however, need to flush the depth cache
because you cannot do bind a depth texture as an image.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/barrier: Do the correct flushes for texture updates

Texture uploads and downloads may go through the render pipe which may
result in texturing from or rendering to the texture or the PBO.  We
need to flush accordingly.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

include: Revert out the update of the Khronos GLX extension header.

They made a mistake in the MESA_swap_control XML, which I'm pursuing in
their github.  Until then, we can just back this piece out.

Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>

i965: Ignore GL_SKIP_DECODE_EXT for textures accessed via texelFetch().

The GL_EXT_texture_sRGB_decode spec says:

"The conversion of sRGB color space components to linear color space is
 always performed if the texel lookup function is one of the texelFetch
 builtin functions.

 Otherwise, if the texel lookup function is one of the texture builtin
 functions or one of the texture gather functions, the conversion of sRGB
 color space components to linear color space is controlled by the
 TEXTURE_SRGB_DECODE_EXT parameter.

 If the TEXTURE_SRGB_DECODE_EXT parameter is DECODE_EXT, the conversion
 of sRGB color space components to linear color space is performed.

 If the TEXTURE_SRGB_DECODE_EXT parameter is SKIP_DECODE_EXT, the value
 is returned without decoding. However, if the texture is also accessed
 with a texelFetch function, then the result of texture builtin functions
 and/or texture gather functions may be returned with decoding or without
 decoding."

This patch makes i965 force sRGB decoding for any textures accessed via
texelFetch().  If textures are accessed via texelFetch() and a regular
texture access function, this will affect the other ones too - which is
fine - it's undefined according to the last paragraph quoted.

We could make both work, but we'd have to emit multiple SURFACE_STATEs,
and have two binding table sections, like we do for texture gather hacks
on older platforms.

Fixes the following Android O CTS test:
dEQP-GLES31.functional.srgb_texture_decode.skip_decode.srgba8.texel_fetch

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

meta: Unset the textures_used_by_txf bitfield.

Drivers that use Meta are happily using blitting data using texelFetch
and GL_SKIP_DECODE_EXT, but the GL_EXT_texture_sRGB spec unfortunately
makes GL_SKIP_DECODE_EXT not necessarily work with texelFetch.

As a hack, just unset the texture_used_by_txf bitfield so we can
continue with the old desired behavior.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: Make nir_shader_gather_info() track texelFetch texture accesses.

For TGSI-based drivers, st_glsl_to_tgsi records this information.
For NIR-based drivers, nir_shader_gather_info() will do so.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

compiler: Move gl_program::TexelFetchSamplers to shader_info.

I'd like to put this sort of metadata in the shader_info structure,
rather than adding more things to gl_program.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radv: take unsafe_math and sisched into account when hashing shaders.

We want to generate different variants for sisched and unsafe_math
shader variants, so add them to the hash key.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/bufferobj: fix atomic offset/size get

When I realigned the bufferobj code, I didn't see the getters
were different, realign the getters to work the same as ssbo.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103214
Fixes: 65d3ef7cd (mesa: align atomic buffer handling code with ubo/ssbo (v1.1))
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

relnotes: document EGL_ANDROID_native_fence_sync on radeonsi

include: Update GL headers from khronos opengl registry.

Taken from their c6a99aff31874697741a08cbc8a3488606ce59c7, keeping the
BUILDING_MESA hunk in place.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

mapi: Update extension number of MESA_tile_raster_order.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

broadcom/vc5: Remove the u_resource_vtbl usage.

Like for vc4, this was just a wasted indirection.

mesa: Disallow GL_RED/GL_RG with half-floats on GLES2.

Sure, you'd think that the combination of GL_OES_texture_half_float and
GL_EXT_texture_rg would mean that GL_RG16F exists, but it doesn't.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103227
Fixes: c16a7443e999 ("mesa: Expose GL_OES_required_internalformat on GLES contexts.")
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: implement sync_file import/export

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: implement sync_file import/export

syncobj is used internally for interactions with command submission.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: add radeon_info::has_sync_file

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

broadcom/vc5: Don't pair VPMSETUP with other peripheral access.

The specs don't say you can't, but pairing it with an SFU write on the
7268 breaks all our simple shader tests using gl_MVP * gl_Vertex.

broadcom/vc5: Fix inclusion of FS flag bits in dumping the FS address.

st/dri: implement __DRIimageExtension::validateUsage properly

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium: add pipe_screen::check_resource_capability

This is optional (and no CAP).

Implemented by radeonsi, ddebug, rbug, trace.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface: add ac_surface::is_displayable

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amd/addrlib: add Addr2IsValidDisplaySwizzleMode

Some "standard" (_S) swizzle modes are displayable on Raven,
even though the micro tile mode says it's not displayable.
Expose the addrlib function to the driver.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

meson: fix typo in isl

Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Antia Puentes <apuentes@igalia.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

Android: disable i9x5 drivers on non-x86 builds

The i965 driver has become dependent on x86 specific compiler builtin
functions, so ensure it's disabled for non-x86 builds.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Rob Herring <robh@kernel.org>

etnaviv: Do GC3000 resolve-in-place when possible

If an RS blit is done with source exactly the same as destination, and
the hardware supports this, do an in-place resolve. This only fills in
tiles that have not been rendered to using information from the TS.

This is the same as the blob does and potentially saves significant
bandwidth when doing i.MX6qp scanout using PRE, and when rendering to
textures (though here using sampler TS would be even better).

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

egl_haiku: drop haiku_egl_driver struct

The struct only contained the one field we're interested in.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl: remove left over _EGLMain_t

Fixes: b174a1ae720cb404738c "egl: Simplify the "driver" interface"
Cc: Adam Jackson <ajax@redhat.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl: drop memset(0) of calloc'ed memory

`_EGLDriver *drv` is a freshly calloc()'ed object, memset(0)'ing some of
it is a no-op.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl: replace _egl_driver->Unload() callback with a simple free()

Bonus: fixes a memleak on haiku when unloading the driver

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

radv: don't crash if cache is disabled.

If you set MESA_GLSL_CACHE_DISABLE, radv crashed.

Fixes: fd24be134f (radv: make use of on-disk cache)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radv: use CLEAR_STATE for initializing some registers

Based on RadeonSI.

This improves some Vulkan demos by +1% to +3%.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: add has_clear_state and enable it on CIK+ only

This will allow us to emit the CLEAR_STATE packet instead
of a bunch of useless packets when doing CS initialization.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: do not set registers for merged ES-GS on GFX9

Based on RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: move the raster config emission in si_set_raster_config()

Similar to RadeonSI, also only call this function for <= VI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radeonsi: add support for PIPE_FORMAT_{X1,A1}R5G5B5_UNORM

Fixes dEQP-EGL.functional.image.modify.tex_rgb5_a1_tex_subimage_rgba8

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: add tests for PIPE_FORMAT_{X1,A1}B5G5R5_UNORM formats

This is a left-over from my version of adding the new format
after rebasing on Eric's version.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

include/drm-uapi: clarify when headers can be updated.

Clarify when headers can be updated here.

Reviewed-by: Gurchetan Singh<gurchetansingh@chromium.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: remove duplicate line of code

The same line of code is a few lines above.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: make use of on-disk cache

If the app provided in-memory pipeline cache doesn't yet contain
what we are looking for, or it doesn't provide one at all then we
fallback to the on-disk cache.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: create on-disk shader cache

This is the drivers on-disk cache intended to be used as a
fallback as opposed to the pipeline cache provided by apps.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: remove duplicate debug_flags field

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

anv: intel: use anv_image's computed size for importing a BO

Rather than relying on size = stride * height, we can rely on
anv_image's total size.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Daniel Stone <daniels@collabora.com>

anv: bo_cache: allow importing a BO larger than needed

It's not a problem if a BO has been allocated larger than we need it
to be.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102940
Fixes: 818b857914 ("anv: Use the BO cache for DeviceMemory allocations")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Cc: mesa-stable@lists.freedesktop.org

st/glsl_to_tgsi: the second destination doesn't support relative addressing

It's not used -- DFRACEXP gets array indexes of its exponent out-parameter
lowered earlier -- and it wouldn't have worked correctly anyway when both
dst and dst1 use relative addressing.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/glsl_to_tgsi: fix DFRACEXP with only one destination

Replace the undefined destination by a new temporary register.

Cleanup merge_two_dsts while we're at it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/glsl_to_tgsi: fix indirect access to 64-bit integer

Make sure we actually allocate two adjacent TGSI temporaries. The
current code fails e.g. when an arithmetic operation has two
operands with indirect accesses.

I will send out a new piglit test
(arb_gpu_shader_int64/execution/indirect-array-two-accesses.shader_test)

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: don't assign prog->ShadowSamplers

It's not used, and the assignment for the TGSI case was incorrect
for sampler arrays.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/glsl_to_tgsi: ignore GL_TEXTURE_SRGB_DECODE_EXT for samplers used with texelFetch*()

See the comment for the relevant spec quote.

Fixes dEQP-GLES31.functional.srgb_texture_decode.skip_decode.srgba8.texel_fetch

v2: note the interaction between ARB_bindless_texture and EXT_texture_sRGB_decode
    as a TODO

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: store state that affects sampler views per context

This fixes sequences like:

1. Context 1 samples from texture with sRGB decode enabled
2. Context 2 samples from texture with sRGB decode disabled
3. Context 1 samples from texture with sRGB decode disabled

Previously, step 3 would see the prev_sRGBDecode value from context 2
and would incorrectly use the old sampler view with sRGB decode enabled.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

swr: simd16 shaders work in progress

Start building vertex shaders as simd16.

Disabled by default, set USE_SIMD16_SHADERS in knobs.h to experiment.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

gallium: allow 512-bit vectors

Increase the max allowed vector size from 256 to 512.

No piglit llvmpipe regressions running on avx2.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

i965: Drop brw_bo_alloc in ARB_indirect_parameters implementation.

The original implementation allocated a new BO here, but we decided to
switch to intel_upload_space, which returns a reference to the current
upload BO.  We accidentally kept the brw_bo_alloc, even though it's no
longer necessary - intel_upload_space will immediately unreference it,
causing us to allocate and immediately free a buffer.

Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>

i965: Allow mapped VBOs during drawing in non-debug contexts.

Section 6.3.2 of the GL 4.5 spec says:

   "Any GL command which attempts to read from, write to, or change
    the state of a buffer object may generate an INVALID_OPERATION error
    if all or part of the buffer object is mapped ... However, only
    commands which explicitly describe this error are required to do so.
    If an error is not generated, such commands will have undefined
    results and may result in GL interruption or termination."

Setting this flag allows us to skip walking over the buffer bindings
for every enabled vertex attribute (_mesa_all_buffers_are_unmapped).

Improves performance in GFXBench4's gl_driver2_off microbenchmark by
3.05797% +/- 0.709031% (n=33) on Apollolake.

This breaks KHR-*.draw_elements_base_vertex_tests.invalid_mapped_bos,
but that test is invalid and has been removed from the upstream CTS.

Reviewed-by: Eric Anholt <eric@anholt.net>

meson: fix glx test

That requires a generated header that was rolled into a loop.

fixes: a47c525f3281a27 ("meson: build glx")
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

nv50,nvc0: fix push hint logic in presence of a start offset

Previously buffer offsets were passed in explicitly as an offset, which
had to be added to the resource address. Now they are passed in via an
increased 'start' parameter. As a result, we were double-adding the
start offset in this kind of situation.

This condition was triggered by piglit's draw-elements test which has a
requisite glMultiDrawElements in combination with a small enough number
of vertices to go through the immediate push path.

Fixes: 330d0607ed6 ("gallium: remove pipe_index_buffer and set_index_buffer")
Reported-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable@lists.freedesktop.org

i965: Make brw_update_texture_surface static.

Trivial.  It's not used in other files.

Android: fix build break from r600/radeon split

Commit 06bfb2d28f7a ("r600: fork and import gallium/radeon") broke the
Android build:

external/mesa3d/src/gallium/drivers/radeon/r600_pipe_common.c:43:10: fatal error: 'llvm-c/TargetMachine.h' file not found
         ^~~~~~~~~~~~~~~~~~~~~~~~

Update the Android makefiles so that drivers/radeon is only built when
radeonsi (and therefore LLVM) is enabled.

Fixes: 06bfb2d28f7a (r600: fork and import gallium/radeon)
Acked-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>

Android: move libraries to /vendor

As part of Treble project in Android O, all the device specific files have
to be located in a separate vendor partition. This is done by setting
LOCAL_PROPRIETARY_MODULE (the name is misleading). This change will not
break existing platforms without a vendor partition as it will just move
files to /system/vendor.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Rob Herring <robh@kernel.org>

i965: Fix output register sizes when multiple variables share a slot.

ARB_enhanced_layouts allows multiple output variables to share the same
location - and these variables may not have the same sizes.  For
example, consider these output variables:

   // consume X/Y/Z components of 6 vectors
   layout(location = 0) out vec3 a[6];

   // consumes W component of the first vector
   layout(location = 0, component = 3) out float b;

Looking at the first declaration, we see that VARYING_SLOT_VAR0 needs 24
components worth of space (vec3 padded out to a vec4, 4 * 6 = 24).  But
looking at the second declaration, we would think that VARYING_SLOT_VAR0
needs only 4 components of space (a single float padded out to a vec4).

nir_setup_outputs() only considered the space requirements of the first
declaration it happened to see, so if 'float b' came first, it would
underallocate the output register space, causing brw_fs_validator.cpp
to assert fail about inst->dst.offset exceeding the register size.

Fixes Piglit's tests/spec/arb_enhanced_layouts/execution/component-layout/
vs-to-fs-array-interleave-single-location.shader_test.

Thanks to Tim Arceri for finding this bug and writing a test!

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

nir: bump loop unroll limit to 96.

With the ssao demo from Vulkan demos:
radv/rx480: 440->440fps
anv/haswell: 24->34 fps

The demo does a 0->32 loop across a ubo with 32 members.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

anv: fix assert in wsi image code.

This assert was firing just running demos.

Jason said it should be this.

Fixes: 6c7720ed78 (anv/wsi: Allocate enough memory for the entire image)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/st: fix atomic buffer sizing to align with ssbo.

This respects the size from the range setting like ssbo.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/bufferobj: consolidate some buffer binding code.

These paths are again 90% the same, consolidate them into
one.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/bufferobj: consolidate some codepaths between ubo/ssbo/atomics.

These are 90% the same code, consolidate them into a couple of
common codepaths.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: rename various buffer bindings to one struct.

One binding to bind them all, these are all the same thing.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: align atomic buffer handling code with ubo/ssbo (v1.1)

this adds automatic size support to the atomic buffer code,
but also realigns the code to act like the ubo/ssbo code.

v1.1:
add missing blank lines.
reindent one block properly.
check for NullBufferObj.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

i965: Don't try to decode types for non-existent src1.

KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks has a MOV that hits
this validation path.  MOVs don't have a src1 file, but calling
brw_inst_src1_type() was tripping on src1.file being BRW_IMMEDIATE_VALUE
and the hw_type being something invalid for immediates.

To work around this, just pretend src1 is src0 if there isn't a src1.

Fixes: 2572c2771d0cab0b9bc489d354ede44dfc88547b (i965: Validate "Special
       Requirements for Handling Double Precision Data Types")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102680
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

main/format: skip format conversion if src and dst format are equal

Fixes 'KHR-GL45.copy_image.functional' on Nouveau and i965.

v2: (by Kenneth Graunke)
    Rewrite patch according to Jason Ekstrand's review feedback.
    This makes it handle differing strides, which i965 needed.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

mesa: Make _mesa_get_format_bytes handle array formats.

This is easier than making callers handle a bunch of special cases.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radv: Only set the MTYPE flags on GFX9+.

Older kernels fail the va_op with this flag set. If the kernel
supports GFX9 usefully, it will also support this flag.

Fixes: e8d57802fea "radv/gfx9: allocate events from uncached VA space"
Reviewed-by: Dave Airlie <airlied@redhat.com>

i965: Disable auxiliary buffers when there are self-dependencies.

Jason and I investigated several OpenGL CTS failures where the tests
bind the same texture for rendering and texturing, at the same time.
This has defined results as long as the reads happen before writes,
or the regions are non-overlapping.  Normally, this just works out.

However, CCS can cause problems.  If the shader is reading one set of
pixels, and writing to different pixels that are adjacent, they may end
up being covered by the same CCS block.  So rendering may be writing a
CCS block, while the sampler is trying to read it.  Corruption ensues.

Disabling CCS is unfortunate, but safe.

Fixes several KHR-GL45.texture_barrier.* subtests.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

r600: cleanup llvm ir target selection.

Only r600 target used now for compute IR.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: drop tc_L2_dirty bit, this was SI only.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radeonsi: lower ffma in nir to mad.

This lowers ffma to a * b + c.

This seems like it should keep Marek happiest, so
we'd never get to the fma instruction emission code.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: lower ffma in nir.

So it appears the Vulkan SPIR-V fma opcode can be equivalent to a
mad operation, and the fma hw opcode on AMD hw is issued like a double
opcode so is slower. Also the radeonsi stack does this.

This appears to improve performance on a number of games from Feral,
and thanks to Feral for noticing the problem.

I'm reposting this one as Marek indicated he thinks this is what
we should be doing on AMD hw.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: Add R16G16B16A16_SNORM fast clear support

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

broadcom/vc5: Fix handling of 5551 textures using the new gallium format.

Like vc4, we have the alpha in the low bit.  Fixes a bunch of piglit
texwrap failures.

broadcom/vc5: Set the RCL's MSAA mode to match the BCL's MSAA state.