Clifford Wolf [Thu, 12 Oct 2017 09:59:11 +0000 (11:59 +0200)]
Add Verific fairness/liveness support
Clifford Wolf [Wed, 11 Oct 2017 11:58:51 +0000 (13:58 +0200)]
Update ABC to hg rev
6283c5d99b06
Clifford Wolf [Tue, 10 Oct 2017 13:16:45 +0000 (15:16 +0200)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Tue, 10 Oct 2017 13:16:39 +0000 (15:16 +0200)]
Start work on pre-processor for Verific SVA properties
Clifford Wolf [Tue, 10 Oct 2017 11:32:58 +0000 (13:32 +0200)]
Rewrite ABC output to include proper net names in timing report
Clifford Wolf [Tue, 10 Oct 2017 11:32:04 +0000 (13:32 +0200)]
Add timing constraints to osu035 example
Clifford Wolf [Tue, 10 Oct 2017 10:00:48 +0000 (12:00 +0200)]
Remove some dead code
Clifford Wolf [Tue, 10 Oct 2017 09:59:32 +0000 (11:59 +0200)]
Allow $past, $stable, $rose, $fell in $global_clock blocks
Clifford Wolf [Sat, 7 Oct 2017 11:40:54 +0000 (13:40 +0200)]
Add $shiftx support to verilog front-end
Clifford Wolf [Fri, 6 Oct 2017 08:07:33 +0000 (10:07 +0200)]
Update ABC to hg rev
0fc1803a77c0
Larry Doolittle [Thu, 5 Oct 2017 00:01:30 +0000 (17:01 -0700)]
Clean whitespace and permissions in techlibs/intel
Clifford Wolf [Thu, 5 Oct 2017 12:38:32 +0000 (14:38 +0200)]
Improve handling of Verific errors
Clifford Wolf [Wed, 4 Oct 2017 16:56:28 +0000 (18:56 +0200)]
Improve Verific error handling, check VHDL static asserts
Clifford Wolf [Wed, 4 Oct 2017 16:30:42 +0000 (18:30 +0200)]
Add blackbox command
Clifford Wolf [Wed, 4 Oct 2017 15:23:42 +0000 (17:23 +0200)]
Fix nasty bug in Verific bindings
Clifford Wolf [Tue, 3 Oct 2017 16:23:45 +0000 (18:23 +0200)]
Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosys
Clifford Wolf [Tue, 3 Oct 2017 16:20:08 +0000 (18:20 +0200)]
Merge branch 'fix_shift_reduce_conflict' of https://github.com/udif/yosys
Clifford Wolf [Tue, 3 Oct 2017 15:33:43 +0000 (17:33 +0200)]
Merge branch 'dh73-master'
Clifford Wolf [Tue, 3 Oct 2017 15:31:21 +0000 (17:31 +0200)]
Rename "write_verilog -nobasenradix" to "write_verilog -decimal"
dh73 [Mon, 2 Oct 2017 00:59:45 +0000 (19:59 -0500)]
Tested and working altsyncarm without init files
dh73 [Sun, 1 Oct 2017 16:11:32 +0000 (11:11 -0500)]
Fixed wrong declaration in Verilog backend
dh73 [Sun, 1 Oct 2017 16:04:17 +0000 (11:04 -0500)]
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
Udi Finkelstein [Sat, 30 Sep 2017 04:37:38 +0000 (07:37 +0300)]
Turned a few member functions into const, esp. dumpAst(), dumpVlog().
Udi Finkelstein [Sat, 30 Sep 2017 03:39:07 +0000 (06:39 +0300)]
Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution
(Oreilly 'Flex & Bison' page 189)
Clifford Wolf [Fri, 29 Sep 2017 15:53:43 +0000 (17:53 +0200)]
Add first draft of eASIC back-end
Clifford Wolf [Fri, 29 Sep 2017 15:52:57 +0000 (17:52 +0200)]
Fix synth_ice40 doc regarding -top default
Clifford Wolf [Fri, 29 Sep 2017 09:56:43 +0000 (11:56 +0200)]
Allow $size and $bits in verilog mode, actually check test case
Clifford Wolf [Fri, 29 Sep 2017 09:39:36 +0000 (11:39 +0200)]
Merge pull request #425 from udif/udif_dollar_bits
Add $bits() and $size()
Clifford Wolf [Thu, 28 Sep 2017 12:45:47 +0000 (14:45 +0200)]
Merge pull request #421 from stephengroat/osx-travis
Add osx tests using brew bundle
Stephen [Wed, 27 Sep 2017 23:52:20 +0000 (16:52 -0700)]
delete bad backslash
Stephen [Wed, 27 Sep 2017 23:51:50 +0000 (16:51 -0700)]
forgot to install bundles
Stephen Groat [Wed, 27 Sep 2017 23:49:03 +0000 (16:49 -0700)]
Add osx tests using brew bundle
Clifford Wolf [Wed, 27 Sep 2017 13:27:42 +0000 (15:27 +0200)]
Increase maximum LUT size in blifparse to 12 bits
Udi Finkelstein [Tue, 26 Sep 2017 17:34:24 +0000 (20:34 +0300)]
$size() now works correctly for all cases!
It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
Udi Finkelstein [Tue, 26 Sep 2017 16:18:25 +0000 (19:18 +0300)]
$size() seems to work now with or without the optional parameter.
Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
Clifford Wolf [Tue, 26 Sep 2017 12:37:03 +0000 (14:37 +0200)]
Parse reals as string in JSON front-end
Clifford Wolf [Tue, 26 Sep 2017 12:02:57 +0000 (14:02 +0200)]
Merge branch 'vlogpp-inc-fixes'
Clifford Wolf [Tue, 26 Sep 2017 11:50:14 +0000 (13:50 +0200)]
Minor coding style fix
Clifford Wolf [Tue, 26 Sep 2017 11:48:13 +0000 (13:48 +0200)]
Merge branch 'master' of https://github.com/combinatorylogic/yosys into combinatorylogic-master
Udi Finkelstein [Tue, 26 Sep 2017 06:19:56 +0000 (09:19 +0300)]
enable $bits() and $size() functions only when the SystemVerilog flag is enabled for read_verilog
Udi Finkelstein [Tue, 26 Sep 2017 06:11:25 +0000 (09:11 +0300)]
Added $bits() for memories as well.
Udi Finkelstein [Tue, 26 Sep 2017 05:36:45 +0000 (08:36 +0300)]
$size() now works with memories as well!
Udi Finkelstein [Tue, 26 Sep 2017 03:25:42 +0000 (06:25 +0300)]
Add $size() function. At the moment it works only on expressions, not on memories.
Clifford Wolf [Mon, 25 Sep 2017 23:52:59 +0000 (01:52 +0200)]
Fix ignoring of simulation timings so that invalid module parameters cause syntax errors
combinatorylogic [Thu, 21 Sep 2017 17:25:02 +0000 (18:25 +0100)]
Adding support for string macros and macros with arguments after include
Clifford Wolf [Sat, 16 Sep 2017 09:31:37 +0000 (11:31 +0200)]
Merge pull request #413 from azonenberg/extract-reduce-tweaks
Added support for off-chain loads in extract_reduce
Andrew Zonenberg [Sat, 16 Sep 2017 00:54:07 +0000 (17:54 -0700)]
Added missing "break"
Andrew Zonenberg [Fri, 15 Sep 2017 20:56:00 +0000 (13:56 -0700)]
Implemented off-chain support for extract_reduce
Andrew Zonenberg [Fri, 15 Sep 2017 17:52:09 +0000 (10:52 -0700)]
extract_reduce now only removes the head of the chain, relying on "clean" to delete upstream cells. Added "-allow-off-chain" flag, but it's currently ignored.
Clifford Wolf [Fri, 15 Sep 2017 19:28:16 +0000 (21:28 +0200)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Fri, 15 Sep 2017 19:25:59 +0000 (21:25 +0200)]
Update ABC to hg rev
cd6984ee82d4
Clifford Wolf [Thu, 14 Sep 2017 20:36:25 +0000 (22:36 +0200)]
Merge pull request #412 from azonenberg/reduce-fixes
extract_reduce: Fix segfault on "undriven" inputs
Robert Ou [Tue, 12 Sep 2017 21:21:04 +0000 (14:21 -0700)]
extract_reduce: Fix segfault on "undriven" inputs
This is easily triggered when un-techmapping if the technology-specific
cell library isn't loaded. Outputs of technology-specific cells will be
seen as inputs, and nets using those outputs will be seen as undriven.
Just ignore these cells because they can't be part of a reduce chain
anyways.
Clifford Wolf [Thu, 14 Sep 2017 19:44:26 +0000 (21:44 +0200)]
Merge pull request #411 from azonenberg/counter-extraction-fixes
Various improvements and bug fixes to extract_counter
Clifford Wolf [Thu, 14 Sep 2017 19:42:34 +0000 (21:42 +0200)]
Merge pull request #410 from azonenberg/opt_demorgan
Added "opt_demorgan" pass (fixes #408)
Andrew Zonenberg [Thu, 14 Sep 2017 17:34:45 +0000 (10:34 -0700)]
Minor changes to opt_demorgan requested during code review
Andrew Zonenberg [Thu, 14 Sep 2017 17:18:49 +0000 (10:18 -0700)]
Fixed bug where counter extraction on non-GreenPAK devices incorrectly handled parallel counter output
Andrew Zonenberg [Wed, 13 Sep 2017 22:57:17 +0000 (15:57 -0700)]
Added support for inferring counters with reset to full scale instead of zero
Andrew Zonenberg [Wed, 13 Sep 2017 22:47:06 +0000 (15:47 -0700)]
Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.
Andrew Zonenberg [Wed, 13 Sep 2017 22:32:20 +0000 (15:32 -0700)]
Added support for inferring counters with active-low reset
Andrew Zonenberg [Wed, 13 Sep 2017 17:58:41 +0000 (10:58 -0700)]
Initial support for extraction of counters with clock enable
Andrew Zonenberg [Tue, 5 Sep 2017 04:49:56 +0000 (21:49 -0700)]
Fixed typo in comment. Fixed bug where extract_counter would create up counters when it meant to create down counters.
Andrew Zonenberg [Tue, 12 Sep 2017 00:18:26 +0000 (17:18 -0700)]
Initial version of opt_demorgan is functioning for AND/OR gates. Not the prettiest results for bus inputs, but this can be improved
Clifford Wolf [Sat, 9 Sep 2017 08:18:08 +0000 (10:18 +0200)]
Add src attribute to extra cells generated by proc_dlatch
Clifford Wolf [Sat, 9 Sep 2017 08:16:48 +0000 (10:16 +0200)]
Add src arguments to all cell creator helper functions
Clifford Wolf [Sat, 2 Sep 2017 14:37:42 +0000 (16:37 +0200)]
Further improve extract_fa (but still buggy)
Clifford Wolf [Sat, 2 Sep 2017 11:43:51 +0000 (13:43 +0200)]
Merge pull request #406 from azonenberg/coolrunner-techmap
Coolrunner techmapping improvements
Clifford Wolf [Sat, 2 Sep 2017 11:43:36 +0000 (13:43 +0200)]
Merge pull request #405 from azonenberg/gpak-refactoring
Gpak refactoring
Robert Ou [Thu, 31 Aug 2017 00:02:28 +0000 (17:02 -0700)]
coolrunner2: Finish fixing special-use p-terms
Robert Ou [Wed, 30 Aug 2017 23:46:32 +0000 (16:46 -0700)]
coolrunner2: Generate a feed-through AND term when necessary
Robert Ou [Wed, 30 Aug 2017 23:38:04 +0000 (16:38 -0700)]
coolrunner2: Initial fixes for special p-terms
Certain signals can only be controlled by a product term and not a
sum-of-products. Do the initial work for fixing this.
Robert Ou [Tue, 29 Aug 2017 21:56:02 +0000 (14:56 -0700)]
coolrunner2: Fix mapping of flip-flops
Robert Ou [Tue, 29 Aug 2017 21:55:45 +0000 (14:55 -0700)]
coolrunner2: Combine some for loops together
Andrew Zonenberg [Fri, 1 Sep 2017 13:41:39 +0000 (06:41 -0700)]
Fixed typo in error message
Andrew Zonenberg [Tue, 29 Aug 2017 21:17:29 +0000 (14:17 -0700)]
Added blackbox $__COUNT_ cell model
Andrew Zonenberg [Tue, 29 Aug 2017 20:23:23 +0000 (13:23 -0700)]
Refactoring: moved modules still in cells_sim to cells_sim_wip
Clifford Wolf [Fri, 1 Sep 2017 10:35:09 +0000 (12:35 +0200)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Fri, 1 Sep 2017 10:33:47 +0000 (12:33 +0200)]
Merge branch 'ChipScan-master'
Clifford Wolf [Fri, 1 Sep 2017 10:26:55 +0000 (12:26 +0200)]
Update more stuff to use get_src_attribute() and set_src_attribute()
Jason Lowdermilk [Thu, 31 Aug 2017 20:51:56 +0000 (14:51 -0600)]
updated to use get_src_attribute() and set_src_attribute().
Clifford Wolf [Thu, 31 Aug 2017 15:54:28 +0000 (17:54 +0200)]
Merge pull request #399 from azonenberg/counter-extraction
Refactored counter extraction to not be GreenPAK specific. Fixes #396.
Andrew Zonenberg [Thu, 31 Aug 2017 01:16:15 +0000 (18:16 -0700)]
Merge branch 'counter-extraction' of github.com:azonenberg/yosys into counter-extraction
Andrew Zonenberg [Thu, 31 Aug 2017 01:14:22 +0000 (18:14 -0700)]
extract_counter: Added optimizations to remove unused high-order bits
Andrew Zonenberg [Wed, 30 Aug 2017 23:40:41 +0000 (16:40 -0700)]
Merge branch 'master' of https://github.com/cliffordwolf/yosys into counter-extraction
Andrew Zonenberg [Wed, 30 Aug 2017 23:27:18 +0000 (16:27 -0700)]
extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos
Jason Lowdermilk [Wed, 30 Aug 2017 17:47:06 +0000 (11:47 -0600)]
Merge remote-tracking branch 'upstream/master'
Jason Lowdermilk [Wed, 30 Aug 2017 17:46:41 +0000 (11:46 -0600)]
fix indent level
Clifford Wolf [Wed, 30 Aug 2017 09:53:44 +0000 (11:53 +0200)]
Merge pull request #397 from azonenberg/gpak-libfixes
Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're…
Clifford Wolf [Wed, 30 Aug 2017 09:39:11 +0000 (11:39 +0200)]
Add {get,set}_src_attribute() methods on RTLIL::AttrObject
Jason Lowdermilk [Tue, 29 Aug 2017 20:46:35 +0000 (14:46 -0600)]
Add support for source line tracking through synthesis phase
Andrew Zonenberg [Tue, 29 Aug 2017 05:13:36 +0000 (22:13 -0700)]
Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells.
Andrew Zonenberg [Tue, 29 Aug 2017 04:48:20 +0000 (21:48 -0700)]
Refactored extract_counter to be generic vs GreenPAK specific
Andrew Zonenberg [Tue, 29 Aug 2017 03:52:08 +0000 (20:52 -0700)]
Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass
Andrew Zonenberg [Mon, 28 Aug 2017 16:06:37 +0000 (09:06 -0700)]
Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're multi-edge-sensitive and getting confused.
Clifford Wolf [Mon, 28 Aug 2017 17:52:51 +0000 (19:52 +0200)]
Merge branch 'azonenberg-recover-reduce'
Clifford Wolf [Mon, 28 Aug 2017 17:52:06 +0000 (19:52 +0200)]
Rename recover_reduce to extract_reduce, fix args handling
Clifford Wolf [Mon, 28 Aug 2017 17:46:17 +0000 (19:46 +0200)]
Merge branch 'recover-reduce' of https://github.com/azonenberg/yosys into azonenberg-recover-reduce
Clifford Wolf [Mon, 28 Aug 2017 17:43:26 +0000 (19:43 +0200)]
Further improve extract_fa pass
Clifford Wolf [Mon, 28 Aug 2017 13:29:58 +0000 (15:29 +0200)]
Merge pull request #392 from azonenberg/greenpak-portfixes
Fixed bug causing GP_SPI model to not synthesize
Andrew Zonenberg [Mon, 14 Aug 2017 22:32:07 +0000 (15:32 -0700)]
Fixed bug causing GP_SPI model to not synthesize