openpower-isa.git
3 years agotemporary reordering after the DCT schedule is carried out, this removes
Luke Kenneth Casson Leighton [Tue, 20 Jul 2021 14:56:43 +0000 (15:56 +0100)]
temporary reordering after the DCT schedule is carried out, this removes
the need for *data* swaps.

3 years agorealised that SVSHAPE0-3 is not privileged
Luke Kenneth Casson Leighton [Tue, 20 Jul 2021 13:08:06 +0000 (14:08 +0100)]
realised that SVSHAPE0-3 is not privileged

3 years agoadd inner sub-loop testing from svstep Rc=1
Luke Kenneth Casson Leighton [Tue, 20 Jul 2021 13:06:04 +0000 (14:06 +0100)]
add inner sub-loop testing from svstep Rc=1

3 years agocomments
Luke Kenneth Casson Leighton [Tue, 20 Jul 2021 09:01:08 +0000 (10:01 +0100)]
comments

3 years agocomments
Luke Kenneth Casson Leighton [Tue, 20 Jul 2021 08:58:09 +0000 (09:58 +0100)]
comments

3 years agobit of a reorg, adding option to test end of inner loops of SVSTATE(s)
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 19:45:25 +0000 (20:45 +0100)]
bit of a reorg, adding option to test end of inner loops of SVSTATE(s)
needed to pass the immediate to svstep as an option of which
SVSTATE0-3 to test

3 years agodo in-place swap
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 15:24:48 +0000 (16:24 +0100)]
do in-place swap

3 years agoannoying: missed out something in the unit test, not working yet
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 14:59:03 +0000 (15:59 +0100)]
annoying: missed out something in the unit test, not working yet

3 years agosimplify DCT code
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 14:53:17 +0000 (15:53 +0100)]
simplify DCT code

3 years agocreate coefficient table for DCT outside of loops
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 14:50:23 +0000 (15:50 +0100)]
create coefficient table for DCT outside of loops

3 years agoupdate comments
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 14:48:17 +0000 (15:48 +0100)]
update comments

3 years agomore comments
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 14:13:25 +0000 (15:13 +0100)]
more comments

3 years agoupdate comments and license
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 14:05:26 +0000 (15:05 +0100)]
update comments and license

3 years agoremove unneeded code
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 13:47:59 +0000 (14:47 +0100)]
remove unneeded code

3 years agono need for len(j) > 1 test, half of 1 is zero which stops swap anyway
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 13:46:25 +0000 (14:46 +0100)]
no need for len(j) > 1 test, half of 1 is zero which stops swap anyway

3 years agoremove unneeded code
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 13:44:20 +0000 (14:44 +0100)]
remove unneeded code

3 years agoswap the indices rather than the data in DCT top half: bizarrely this works!
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 13:41:04 +0000 (14:41 +0100)]
swap the indices rather than the data in DCT top half: bizarrely this works!

3 years agoremove copy, use in-place with post-inner-loop swap
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 12:25:51 +0000 (13:25 +0100)]
remove copy, use in-place with post-inner-loop swap

3 years agoadd experimental order-reversing code (commented out) to DCT
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 11:56:51 +0000 (12:56 +0100)]
add experimental order-reversing code (commented out) to DCT

3 years agocode comments
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 11:08:38 +0000 (12:08 +0100)]
code comments

3 years agowhitespace cleanup
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 11:08:00 +0000 (12:08 +0100)]
whitespace cleanup

3 years agomove bit-reversing to before MULs in DCT
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 10:57:37 +0000 (11:57 +0100)]
move bit-reversing to before MULs in DCT

3 years agoreverse bit-order of in-place outer DCT butterfly
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 10:53:33 +0000 (11:53 +0100)]
reverse bit-order of in-place outer DCT butterfly

3 years agofinallygot the DCT outer butterfly correct
Luke Kenneth Casson Leighton [Mon, 19 Jul 2021 10:48:45 +0000 (11:48 +0100)]
finallygot the DCT outer butterfly correct

3 years agogot cos intermediate working on iterative dct
Luke Kenneth Casson Leighton [Sun, 18 Jul 2021 20:29:36 +0000 (21:29 +0100)]
got cos intermediate working on iterative dct

3 years agoexperimenting to create iterative version of dct
Luke Kenneth Casson Leighton [Sun, 18 Jul 2021 16:24:28 +0000 (17:24 +0100)]
experimenting to create iterative version of dct

3 years agouse lists rather than list incomprehension
Luke Kenneth Casson Leighton [Sun, 18 Jul 2021 10:09:29 +0000 (11:09 +0100)]
use lists rather than list incomprehension

3 years agoprint out some debug statements in fastdctlee
Luke Kenneth Casson Leighton [Sat, 17 Jul 2021 17:03:30 +0000 (18:03 +0100)]
print out some debug statements in fastdctlee

3 years agowhitespace
Luke Kenneth Casson Leighton [Sat, 17 Jul 2021 16:07:29 +0000 (17:07 +0100)]
whitespace

3 years agoadd naive dct, remove fft variant
Luke Kenneth Casson Leighton [Sat, 17 Jul 2021 16:06:38 +0000 (17:06 +0100)]
add naive dct, remove fft variant

3 years agoadd nayuki dct
Luke Kenneth Casson Leighton [Sat, 17 Jul 2021 15:29:11 +0000 (16:29 +0100)]
add nayuki dct

3 years agoworking RADIX-2 FFT with bit-reversed LD/ST
Luke Kenneth Casson Leighton [Sat, 17 Jul 2021 13:59:55 +0000 (14:59 +0100)]
working RADIX-2 FFT with bit-reversed LD/ST

3 years agoadd FP LOAD bit-reversed operations to ISACaller simulator
Luke Kenneth Casson Leighton [Sat, 17 Jul 2021 12:07:40 +0000 (13:07 +0100)]
add FP LOAD bit-reversed operations to ISACaller simulator

3 years agomake a test for if size of FFT is less than 8, if so call a separate function
Luke Kenneth Casson Leighton [Fri, 16 Jul 2021 19:03:17 +0000 (20:03 +0100)]
make a test for if size of FFT is less than 8, if so call a separate function
idea is to replace that function with assembler

3 years agoadd fsins and fcoss to simulator
Luke Kenneth Casson Leighton [Fri, 16 Jul 2021 17:15:31 +0000 (18:15 +0100)]
add fsins and fcoss to simulator
WARNING: THESE ARE **NOT** APPROVED BY OPF ISA WG, CONSIDER TO BE DRAFT
in particular, they have had to be added to minor opcode 59 (alongside
fcfids) because there is not enough space to add them to "sandbox" 22

3 years agocode clean-up, simplify, use float not double
Luke Kenneth Casson Leighton [Fri, 16 Jul 2021 16:23:26 +0000 (17:23 +0100)]
code clean-up, simplify, use float not double

3 years agoadd fft makefile
Luke Kenneth Casson Leighton [Fri, 16 Jul 2021 16:14:06 +0000 (17:14 +0100)]
add fft makefile

3 years agoadd nayuki project reference code
Luke Kenneth Casson Leighton [Fri, 16 Jul 2021 15:59:41 +0000 (16:59 +0100)]
add nayuki project reference code
https://www.nayuki.io/page/free-small-fft-in-multiple-languages

3 years agouse coincidence of svremap "persistence" to remove one more instruction
Luke Kenneth Casson Leighton [Thu, 15 Jul 2021 18:07:38 +0000 (19:07 +0100)]
use coincidence of svremap "persistence" to remove one more instruction
from FFT example

3 years agoenable use of svremap "persist" mode, remove 4 instructions from FFT example
Luke Kenneth Casson Leighton [Thu, 15 Jul 2021 17:58:34 +0000 (18:58 +0100)]
enable use of svremap "persist" mode, remove 4 instructions from FFT example

3 years agostop using MSR vfirst bit, move to SVSTATE bit 63 instead
Luke Kenneth Casson Leighton [Thu, 15 Jul 2021 17:49:45 +0000 (18:49 +0100)]
stop using MSR vfirst bit, move to SVSTATE bit 63 instead

3 years agoadd extra "persistence" bit to svremap instruction
Luke Kenneth Casson Leighton [Thu, 15 Jul 2021 17:44:13 +0000 (18:44 +0100)]
add extra "persistence" bit to svremap instruction

3 years agobig intrusive update: merge SVREMAP with SVSTATE, remove SVREMAP
Luke Kenneth Casson Leighton [Thu, 15 Jul 2021 12:51:08 +0000 (13:51 +0100)]
big intrusive update: merge SVREMAP with SVSTATE, remove SVREMAP
this also involved creating an SVP64State class similar to the REMAPP
class (now removed).
unit tests had to be altered to the new API

3 years agouse fmadds and fmsubs in complex fft example
Luke Kenneth Casson Leighton [Wed, 14 Jul 2021 20:37:38 +0000 (21:37 +0100)]
use fmadds and fmsubs in complex fft example
reduces inner loop instruction count by 2

3 years agoupdate SVSTATE to 64 bit length
Luke Kenneth Casson Leighton [Wed, 14 Jul 2021 19:01:24 +0000 (20:01 +0100)]
update SVSTATE to 64 bit length

3 years agosubtract one from SVi field for setvl assembler
Luke Kenneth Casson Leighton [Wed, 14 Jul 2021 18:29:49 +0000 (19:29 +0100)]
subtract one from SVi field for setvl assembler
update all uses to match

3 years agochange order of log printout for "writing gpr NN"
Luke Kenneth Casson Leighton [Tue, 13 Jul 2021 16:24:30 +0000 (17:24 +0100)]
change order of log printout for "writing gpr NN"

3 years agosuccessful complex FFT butterfly, in-place, using Vertical-First SVP64
Luke Kenneth Casson Leighton [Mon, 12 Jul 2021 20:02:55 +0000 (21:02 +0100)]
successful complex FFT butterfly, in-place, using Vertical-First SVP64

3 years agoadd a Discrete FFT butterfly unit test as an intermediary (incremental)
Luke Kenneth Casson Leighton [Mon, 12 Jul 2021 14:20:02 +0000 (15:20 +0100)]
add a Discrete FFT butterfly unit test as an intermediary (incremental)
step towards full complex butterfly.

this test uses fp24 as an intermediary for storing the result of the
multiply, source from butterfly-scheduled operands.

that scalar reg is then used as a source in a butterfly-scheduled
twin +/- in-place ADD-SUB

3 years agominor reordering of setvl and svshape: svshape is now capable of setting VL
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 23:02:00 +0000 (00:02 +0100)]
minor reordering of setvl and svshape: svshape is now capable of setting VL

3 years agoadd svremap instruction into ISACaller
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 19:17:51 +0000 (20:17 +0100)]
add svremap instruction into ISACaller
alter FFT and Matrix-Multiply SVP64 tests to use new svremap
generic redirect of any register to a SVSHAPE(0-3) rather than hard-coded

3 years agoupdate svremap instruction to correctly store immediate args in SPR
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 17:49:42 +0000 (18:49 +0100)]
update svremap instruction to correctly store immediate args in SPR

3 years agowhoops 0b00002 is not binary
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 16:11:27 +0000 (17:11 +0100)]
whoops 0b00002 is not binary

3 years agoadd SVREMAP new Form / Fields and CSV entry
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 16:09:44 +0000 (17:09 +0100)]
add SVREMAP new Form / Fields and CSV entry

3 years agoadd SVREMAP SPR to ISACaller and parser
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 15:08:00 +0000 (16:08 +0100)]
add SVREMAP SPR to ISACaller and parser

3 years agoadd SVREMAP SPR
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 15:02:15 +0000 (16:02 +0100)]
add SVREMAP SPR

3 years agoadd SVP64REMAP Record
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 11:35:08 +0000 (12:35 +0100)]
add SVP64REMAP Record

3 years agorename SVP64REMAP to SVP64SHAPE
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 11:34:50 +0000 (12:34 +0100)]
rename SVP64REMAP to SVP64SHAPE

3 years agorename svremap to svshape
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 11:22:03 +0000 (12:22 +0100)]
rename svremap to svshape

3 years agorename svremap to svshape
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 11:17:50 +0000 (12:17 +0100)]
rename svremap to svshape

3 years agoadd scalar ffadds unit test
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 16:25:25 +0000 (17:25 +0100)]
add scalar ffadds unit test

3 years agowhoops forgot elif in SVP64Asm translation, detection of ffmadds overwritten
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 16:24:10 +0000 (17:24 +0100)]
whoops forgot elif in SVP64Asm translation, detection of ffmadds overwritten

3 years agoin scalar case do not increment RB for FFT mode
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 16:08:24 +0000 (17:08 +0100)]
in scalar case do not increment RB for FFT mode

3 years agoadd sv.ffadds unit test, inversion of subtract needed in svfparith pseudocode
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 11:37:20 +0000 (12:37 +0100)]
add sv.ffadds unit test, inversion of subtract needed in svfparith pseudocode

3 years agomore generic allow fft mode 2nd output detection. REALLY need a CSV Out2 column
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 11:36:43 +0000 (12:36 +0100)]
more generic allow fft mode 2nd output detection.  REALLY need a CSV Out2 column

3 years agoadd ffadds decoding:
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 11:11:19 +0000 (12:11 +0100)]
add ffadds decoding:
- SVP64 trans manual creation of opcode with XO=0b01101
- add to power enums ISA list
- add to minor 59 and SVP64 CSV

3 years agoadd more generic detection of FFT mode, really needs to be a new column in CSV file...
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 11:10:08 +0000 (12:10 +0100)]
add more generic detection of FFT mode, really needs to be a new column in CSV file for Out2

3 years agoadd (disabled) FFT complex unit test under development
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 11:09:10 +0000 (12:09 +0100)]
add (disabled) FFT complex unit test under development

3 years agocorrections to remaining fft madd/msub
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 10:46:49 +0000 (11:46 +0100)]
corrections to remaining fft madd/msub

3 years agoupdate comments
Luke Kenneth Casson Leighton [Fri, 9 Jul 2021 18:42:16 +0000 (19:42 +0100)]
update comments

3 years agofor scalar destination or scalar source on ffmadd, only offset by one
Luke Kenneth Casson Leighton [Fri, 9 Jul 2021 16:12:37 +0000 (17:12 +0100)]
for scalar destination or scalar source on ffmadd, only offset by one

3 years agoadd svstep variant of fpmadds fft test
Luke Kenneth Casson Leighton [Fri, 9 Jul 2021 16:03:31 +0000 (17:03 +0100)]
add svstep variant of fpmadds fft test

3 years agoadd "odd" SVP64 unit tests which alter SVSTATE
Luke Kenneth Casson Leighton [Fri, 9 Jul 2021 15:52:37 +0000 (16:52 +0100)]
add "odd" SVP64 unit tests which alter SVSTATE

3 years agocomments in unit test
Luke Kenneth Casson Leighton [Fri, 9 Jul 2021 11:48:57 +0000 (12:48 +0100)]
comments in unit test

3 years agoadd Vertical-First explicit branch-loop using svstep, with an sv.add. works!
Luke Kenneth Casson Leighton [Fri, 9 Jul 2021 11:44:22 +0000 (12:44 +0100)]
add Vertical-First explicit branch-loop using svstep, with an sv.add. works!

3 years agoend SVP64 "Vertical First" mode on rollover when end of svstep reached
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 22:09:49 +0000 (23:09 +0100)]
end SVP64 "Vertical First" mode on rollover when end of svstep reached

3 years agoadd CR0 setting and unit test on svstep
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 22:04:51 +0000 (23:04 +0100)]
add CR0 setting and unit test on svstep

3 years agowhoops asmcode length (number of instructions) went over 256, caused
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 21:34:29 +0000 (22:34 +0100)]
whoops asmcode length (number of instructions) went over 256, caused
asmcode in simulator to "wrap" and get the wrong instruction name,
and then execute totally the wrong simulated instruction

3 years agotest MSR.SVF bit set after setvl Vertical-First mode set
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 21:26:30 +0000 (22:26 +0100)]
test MSR.SVF bit set after setvl Vertical-First mode set

3 years agowhoops must not reset last_op_svstate except when out of SVP64 mode
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 21:10:03 +0000 (22:10 +0100)]
whoops must not reset last_op_svstate except when out of SVP64 mode

3 years agotesting new setvl "svstep" mode
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 21:03:55 +0000 (22:03 +0100)]
testing new setvl "svstep" mode

3 years agowhoops sv.lfs registers must be even numbers (match SVP6 EXTRA2 encoding)
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 20:46:56 +0000 (21:46 +0100)]
whoops sv.lfs registers must be even numbers (match SVP6 EXTRA2 encoding)

3 years agoadd ability to explicitly increment SVSTATE srcstep/dststep
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 18:02:37 +0000 (19:02 +0100)]
add ability to explicitly increment SVSTATE srcstep/dststep

3 years agoadd (new) extra argument to setvl (Vertical-First mode, set to zero here)
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 15:21:49 +0000 (16:21 +0100)]
add (new) extra argument to setvl (Vertical-First mode, set to zero here)

3 years agoadd in extra "vertical" mode into SVP64 setvl
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 15:12:14 +0000 (16:12 +0100)]
add in extra "vertical" mode into SVP64 setvl

3 years agoclean up imports and unit test name
Luke Kenneth Casson Leighton [Wed, 7 Jul 2021 15:43:40 +0000 (16:43 +0100)]
clean up imports and unit test name

3 years agoffmuls test, had to add to b not a in expected results
Luke Kenneth Casson Leighton [Wed, 7 Jul 2021 15:31:08 +0000 (16:31 +0100)]
ffmuls test, had to add to b not a in expected results

3 years agoget butterfly RADIX2 SVP64 example working, breaks the fpmadds one though
Luke Kenneth Casson Leighton [Wed, 7 Jul 2021 15:27:46 +0000 (16:27 +0100)]
get butterfly RADIX2 SVP64 example working, breaks the fpmadds one though

3 years agoadd in DFT test from Project Nayuki to verify results of butterfly schedule
Luke Kenneth Casson Leighton [Wed, 7 Jul 2021 13:07:27 +0000 (14:07 +0100)]
add in DFT test from Project Nayuki to verify results of butterfly schedule

3 years agochange coefficients in FFT REMAP example so as not to get alternating zeros
Luke Kenneth Casson Leighton [Tue, 6 Jul 2021 20:15:02 +0000 (21:15 +0100)]
change coefficients in FFT REMAP example so as not to get alternating zeros

3 years agowhen REMAP shape is zero, skip it in ISACaller.
Luke Kenneth Casson Leighton [Tue, 6 Jul 2021 20:14:33 +0000 (21:14 +0100)]
when REMAP shape is zero, skip it in ISACaller.
also use srcstep only for FFT butterfly mode (for now)
bit of a hack

3 years agoon FRS for FFT with REMAP use scheduled offset
Luke Kenneth Casson Leighton [Tue, 6 Jul 2021 20:13:50 +0000 (21:13 +0100)]
on FRS for FFT with REMAP use scheduled offset

3 years agoadd FFT REMAP butterfly unit test
Luke Kenneth Casson Leighton [Tue, 6 Jul 2021 19:34:40 +0000 (20:34 +0100)]
add FFT REMAP butterfly unit test

3 years agoadd FFT SHAPE pseudocode in svremap, and a schedule in ISACaller
Luke Kenneth Casson Leighton [Tue, 6 Jul 2021 18:55:41 +0000 (19:55 +0100)]
add FFT SHAPE pseudocode in svremap, and a schedule in ISACaller

3 years agoadd FFT butterfly iteration to SVSHAPE REMAP class for ISACaller
Luke Kenneth Casson Leighton [Tue, 6 Jul 2021 16:03:53 +0000 (17:03 +0100)]
add FFT butterfly iteration to SVSHAPE REMAP class for ISACaller

3 years agowhen FFT madd detected, only enable VL offset in non-REMAP mode
Luke Kenneth Casson Leighton [Tue, 6 Jul 2021 16:03:16 +0000 (17:03 +0100)]
when FFT madd detected, only enable VL offset in non-REMAP mode

3 years agoadd 2nd matrix multiply unit test with SV REMAP
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 22:16:11 +0000 (23:16 +0100)]
add 2nd matrix multiply unit test with SV REMAP

3 years agofix ISACaller FFT-enable detection, fixes sv.fmadds, matrix multiply works
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 21:29:51 +0000 (22:29 +0100)]
fix ISACaller FFT-enable detection, fixes sv.fmadds, matrix multiply works

3 years agofix svremap field offsets
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 21:03:15 +0000 (22:03 +0100)]
fix svremap field offsets

3 years agowhoops, REMAP inverted
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 19:07:49 +0000 (20:07 +0100)]
whoops, REMAP inverted