Sebastien Bourdeauducq [Fri, 15 Mar 2013 17:17:33 +0000 (18:17 +0100)]
Make ClockDomains part of fragments
Sebastien Bourdeauducq [Thu, 14 Mar 2013 11:20:18 +0000 (12:20 +0100)]
flow/actor/filter_endpoints: deterministic order
Sebastien Bourdeauducq [Wed, 13 Mar 2013 22:07:44 +0000 (23:07 +0100)]
bank/csrgen/BankArray: create banks in sorted order
Sebastien Bourdeauducq [Wed, 13 Mar 2013 18:46:34 +0000 (19:46 +0100)]
bank/description: modify reg/mem in-place
Sebastien Bourdeauducq [Tue, 12 Mar 2013 15:59:24 +0000 (16:59 +0100)]
examples/pytholite: use new APIs
Sebastien Bourdeauducq [Tue, 12 Mar 2013 15:54:01 +0000 (16:54 +0100)]
sim/generic: support implicit get_fragment
Sebastien Bourdeauducq [Tue, 12 Mar 2013 15:51:58 +0000 (16:51 +0100)]
vpi: make it work by default on Arch
Sebastien Bourdeauducq [Tue, 12 Mar 2013 15:45:28 +0000 (16:45 +0100)]
examples/basic: use new APIs
Sebastien Bourdeauducq [Tue, 12 Mar 2013 15:16:06 +0000 (16:16 +0100)]
fhdl/verilog: implicit get_fragment
Sebastien Bourdeauducq [Tue, 12 Mar 2013 14:58:39 +0000 (15:58 +0100)]
fhdl/specials/Memory: automatic name#
Sebastien Bourdeauducq [Tue, 12 Mar 2013 14:45:24 +0000 (15:45 +0100)]
bank: automatic register naming
Sebastien Bourdeauducq [Tue, 12 Mar 2013 12:48:09 +0000 (13:48 +0100)]
fhdl/tracer: recognize CALL_FUNCTION_VAR opcode
Sebastien Bourdeauducq [Tue, 12 Mar 2013 09:31:56 +0000 (10:31 +0100)]
fhdl/tracer: recognize LOAD_DEREF opcode
Sebastien Bourdeauducq [Mon, 11 Mar 2013 21:21:58 +0000 (22:21 +0100)]
fhdl/tracer: remove leading underscores from names
Sebastien Bourdeauducq [Mon, 11 Mar 2013 19:29:47 +0000 (20:29 +0100)]
README: update
Sebastien Bourdeauducq [Mon, 11 Mar 2013 16:11:59 +0000 (17:11 +0100)]
bus/asmibus: use implicit finalization
Sebastien Bourdeauducq [Sun, 10 Mar 2013 18:47:21 +0000 (19:47 +0100)]
Fix Register name conflict between Pytholite and Bank
Sebastien Bourdeauducq [Sun, 10 Mar 2013 18:29:05 +0000 (19:29 +0100)]
bank/eventmanager: use module and autoreg
Sebastien Bourdeauducq [Sun, 10 Mar 2013 18:28:22 +0000 (19:28 +0100)]
bus/asmibus: use fhdl.module API
Sebastien Bourdeauducq [Sun, 10 Mar 2013 18:27:55 +0000 (19:27 +0100)]
fhdl/module: replace autofragment
Sebastien Bourdeauducq [Sun, 10 Mar 2013 17:11:29 +0000 (18:11 +0100)]
bank/description/AutoReg: check that get_memories and get_registers are callable
Sebastien Bourdeauducq [Sat, 9 Mar 2013 23:45:16 +0000 (00:45 +0100)]
bank/csrgen: BankArray
Sebastien Bourdeauducq [Sat, 9 Mar 2013 23:43:16 +0000 (00:43 +0100)]
bank/description: AutoReg
Sebastien Bourdeauducq [Sat, 9 Mar 2013 22:23:24 +0000 (23:23 +0100)]
migen/fhdl/autofragment: factorize
Sebastien Bourdeauducq [Sat, 9 Mar 2013 22:05:45 +0000 (23:05 +0100)]
fhdl/autofragment: remove legacy functions
Sebastien Bourdeauducq [Sat, 9 Mar 2013 22:03:15 +0000 (23:03 +0100)]
fhdl/tools/flat_iteration: generalize
Sebastien Bourdeauducq [Sat, 9 Mar 2013 20:15:38 +0000 (21:15 +0100)]
fhdl/autofragment: fix submodules
Sebastien Bourdeauducq [Sat, 9 Mar 2013 18:10:47 +0000 (19:10 +0100)]
fhdl/autofragment: empty build_fragment by default
Sebastien Bourdeauducq [Sat, 9 Mar 2013 18:03:13 +0000 (19:03 +0100)]
Use common definition for FinalizeError
Sebastien Bourdeauducq [Fri, 8 Mar 2013 23:50:57 +0000 (00:50 +0100)]
csr/SRAM: support for writes with memory widths larger than bus words
Sebastien Bourdeauducq [Wed, 6 Mar 2013 10:30:52 +0000 (11:30 +0100)]
fhdl/verilog: tristate outputs are always wire
Sebastien Bourdeauducq [Sun, 3 Mar 2013 18:27:13 +0000 (19:27 +0100)]
bus/csr: support memories with larger word width than the bus (read only)
Sebastien Bourdeauducq [Sun, 3 Mar 2013 16:53:06 +0000 (17:53 +0100)]
fhdl/autofragment: bugfixes + add auto_attr
Sebastien Bourdeauducq [Sat, 2 Mar 2013 22:30:54 +0000 (23:30 +0100)]
fhdl/autofragment: FModule
Sebastien Bourdeauducq [Fri, 1 Mar 2013 11:06:12 +0000 (12:06 +0100)]
csr/SRAM: prefix page register with memory name
Sebastien Bourdeauducq [Wed, 27 Feb 2013 17:10:04 +0000 (18:10 +0100)]
fhdl/verilog: insert reset before listing signals
Sebastien Bourdeauducq [Mon, 25 Feb 2013 22:14:15 +0000 (23:14 +0100)]
bank/description: memprefix
Sebastien Bourdeauducq [Mon, 25 Feb 2013 22:14:03 +0000 (23:14 +0100)]
fhdl/specials: allow setting memory name
Sebastien Bourdeauducq [Mon, 25 Feb 2013 22:13:38 +0000 (23:13 +0100)]
uio/ioo: fix specials
Sebastien Bourdeauducq [Sun, 24 Feb 2013 12:08:01 +0000 (13:08 +0100)]
fhdl/specials/Instance: _printintbool -> verilog_printexpr
Sebastien Bourdeauducq [Sat, 23 Feb 2013 18:14:31 +0000 (19:14 +0100)]
examples/psync: cleanup
Sebastien Bourdeauducq [Sat, 23 Feb 2013 18:04:11 +0000 (19:04 +0100)]
examples/basic/psync: demonstrate the new features
Sebastien Bourdeauducq [Sat, 23 Feb 2013 18:03:35 +0000 (19:03 +0100)]
genlib: clock domain crossing elements
Sebastien Bourdeauducq [Sat, 23 Feb 2013 18:03:16 +0000 (19:03 +0100)]
fhdl/verilog: support special lowering and overrides
Sebastien Bourdeauducq [Fri, 22 Feb 2013 22:19:56 +0000 (23:19 +0100)]
examples/fir: better filter
Sebastien Bourdeauducq [Fri, 22 Feb 2013 22:19:37 +0000 (23:19 +0100)]
corelogic -> genlib
Sebastien Bourdeauducq [Fri, 22 Feb 2013 18:10:02 +0000 (19:10 +0100)]
fhdl: inline synthesis directive support
Sebastien Bourdeauducq [Fri, 22 Feb 2013 17:12:42 +0000 (18:12 +0100)]
doc: new 'specials' API
Sebastien Bourdeauducq [Fri, 22 Feb 2013 16:56:35 +0000 (17:56 +0100)]
New 'specials' API
Sebastien Bourdeauducq [Tue, 19 Feb 2013 16:52:57 +0000 (17:52 +0100)]
doc: tristates
Sebastien Bourdeauducq [Tue, 19 Feb 2013 16:26:02 +0000 (17:26 +0100)]
fhdl: TSTriple
Sebastien Bourdeauducq [Thu, 14 Feb 2013 23:17:24 +0000 (00:17 +0100)]
fhdl: tristate support
Sebastien Bourdeauducq [Mon, 11 Feb 2013 17:34:01 +0000 (18:34 +0100)]
fhdl/autofragment: from_attributes
Sebastien Bourdeauducq [Sun, 10 Feb 2013 18:39:18 +0000 (19:39 +0100)]
doc: fix signal desc layout
Sebastien Bourdeauducq [Sun, 10 Feb 2013 18:03:32 +0000 (19:03 +0100)]
Merge branch 'master' of github.com:milkymist/migen
Sebastien Bourdeauducq [Sun, 10 Feb 2013 18:03:18 +0000 (19:03 +0100)]
doc/dataflow: remove ActorNode
Sebastien Bourdeauducq [Sun, 10 Feb 2013 17:57:03 +0000 (18:57 +0100)]
doc/dataflow: remove ALA
Sebastien Bourdeauducq [Sun, 10 Feb 2013 17:56:45 +0000 (18:56 +0100)]
doc: multiple clock domains
Sebastien Bourdeauducq [Sun, 10 Feb 2013 17:45:06 +0000 (18:45 +0100)]
doc: do not inline examples as this never works with most Sphinx setups ...
Sebastien Bourdeauducq [Sun, 10 Feb 2013 17:42:47 +0000 (18:42 +0100)]
doc: update to new Migen APIs
Sebastien Bourdeauducq [Sat, 9 Feb 2013 16:04:53 +0000 (17:04 +0100)]
sim: default runner to Icarus Verilog
Sebastien Bourdeauducq [Sat, 9 Feb 2013 16:03:48 +0000 (17:03 +0100)]
flow/perftools: finish removing ActorNode
Sebastien Bourdeauducq [Thu, 24 Jan 2013 12:49:49 +0000 (13:49 +0100)]
fhdl/structure: store clock domain name
Sebastien Bourdeauducq [Wed, 23 Jan 2013 14:13:06 +0000 (15:13 +0100)]
fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
Sebastien Bourdeauducq [Sat, 5 Jan 2013 13:18:36 +0000 (14:18 +0100)]
corelogic: complex arithmetic support
Sebastien Bourdeauducq [Sat, 5 Jan 2013 13:18:15 +0000 (14:18 +0100)]
fhdl: support nested statement lists
Sebastien Bourdeauducq [Wed, 19 Dec 2012 15:21:57 +0000 (16:21 +0100)]
pytholite: fix bug with constant assignment to register
Sebastien Bourdeauducq [Wed, 19 Dec 2012 15:03:05 +0000 (16:03 +0100)]
pytholite: prune unused registers
Sebastien Bourdeauducq [Tue, 18 Dec 2012 13:54:33 +0000 (14:54 +0100)]
Do not use super()
Sebastien Bourdeauducq [Sun, 16 Dec 2012 19:26:23 +0000 (20:26 +0100)]
examples/pytholite: fix imports
Sebastien Bourdeauducq [Fri, 14 Dec 2012 22:56:16 +0000 (23:56 +0100)]
fhdl/tools: bitreverse
Sebastien Bourdeauducq [Fri, 14 Dec 2012 22:56:03 +0000 (23:56 +0100)]
actorlib/sim/SimActor: do not drive busy low when generator yields None
Sebastien Bourdeauducq [Fri, 14 Dec 2012 18:16:22 +0000 (19:16 +0100)]
Token: support idle_wait
Sebastien Bourdeauducq [Fri, 14 Dec 2012 14:55:38 +0000 (15:55 +0100)]
Move Token to migen.flow.transactions
Sebastien Bourdeauducq [Wed, 12 Dec 2012 21:36:45 +0000 (22:36 +0100)]
replace some forgotten is_abstract()
Sebastien Bourdeauducq [Wed, 12 Dec 2012 21:20:48 +0000 (22:20 +0100)]
Remove ActorNode
Sebastien Bourdeauducq [Thu, 6 Dec 2012 19:57:30 +0000 (20:57 +0100)]
Merge branch 'master' of github.com:milkymist/migen
Sebastien Bourdeauducq [Thu, 6 Dec 2012 19:56:46 +0000 (20:56 +0100)]
fhdl/structure: do not create Signal in Instance when parameter is int
Sebastien Bourdeauducq [Thu, 6 Dec 2012 16:34:48 +0000 (17:34 +0100)]
elsewhere: do not create interface in default param
Sebastien Bourdeauducq [Thu, 6 Dec 2012 16:28:28 +0000 (17:28 +0100)]
migen/bank: do not create interface in default param
Sebastien Bourdeauducq [Thu, 6 Dec 2012 16:16:17 +0000 (17:16 +0100)]
bus/csr: add SRAM
Sebastien Bourdeauducq [Thu, 6 Dec 2012 16:15:34 +0000 (17:15 +0100)]
bank/csrgen: interface -> bus
Sebastien Bourdeauducq [Wed, 5 Dec 2012 15:40:44 +0000 (16:40 +0100)]
bank/description: define reset value of read signal
Sebastien Bourdeauducq [Wed, 5 Dec 2012 15:40:12 +0000 (16:40 +0100)]
actorlib/sim: drive busy high until generator is finished
Sebastien Bourdeauducq [Sat, 1 Dec 2012 12:04:22 +0000 (13:04 +0100)]
bus/wishbone/sram: accept memories < 32 bits
Sebastien Bourdeauducq [Sat, 1 Dec 2012 11:59:09 +0000 (12:59 +0100)]
bus/wishbone: add SRAM
Sebastien Bourdeauducq [Fri, 30 Nov 2012 16:07:32 +0000 (17:07 +0100)]
pytholite: fix bit width of selection signal
Sebastien Bourdeauducq [Fri, 30 Nov 2012 16:07:12 +0000 (17:07 +0100)]
pytholite: support signed registers
Sebastien Bourdeauducq [Thu, 29 Nov 2012 22:47:51 +0000 (23:47 +0100)]
corelogic/roundrobin: fix request width (again)
Sebastien Bourdeauducq [Thu, 29 Nov 2012 22:47:08 +0000 (23:47 +0100)]
corelogic/roundrobin: fix request width
Sebastien Bourdeauducq [Thu, 29 Nov 2012 22:36:55 +0000 (23:36 +0100)]
Fix various errors from new bitwidth/signedness system conversion
Sebastien Bourdeauducq [Thu, 29 Nov 2012 21:59:54 +0000 (22:59 +0100)]
fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
See http://jandecaluwe.com/hdldesign/counting.html
Sebastien Bourdeauducq [Thu, 29 Nov 2012 21:52:57 +0000 (22:52 +0100)]
fhdl/structure: add unary minus
Sebastien Bourdeauducq [Thu, 29 Nov 2012 20:53:36 +0000 (21:53 +0100)]
Replace Signal(bits_for(... with Signal(max=...
Sebastien Bourdeauducq [Thu, 29 Nov 2012 20:22:38 +0000 (21:22 +0100)]
New specification for width and signedness
Sebastien Bourdeauducq [Thu, 29 Nov 2012 00:11:15 +0000 (01:11 +0100)]
Refactor Case
Sebastien Bourdeauducq [Wed, 28 Nov 2012 23:09:35 +0000 (00:09 +0100)]
pytholite/reg: use source id in dictionary
Sebastien Bourdeauducq [Wed, 28 Nov 2012 22:18:43 +0000 (23:18 +0100)]
Remove Constant
Sebastien Bourdeauducq [Wed, 28 Nov 2012 21:44:14 +0000 (22:44 +0100)]
examples/sim/dataflow: update to new APIs
Sebastien Bourdeauducq [Wed, 28 Nov 2012 21:42:01 +0000 (22:42 +0100)]
examples/dataflow/dma: update to new APIs
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