Miodrag Milanovic [Mon, 17 Feb 2020 11:54:36 +0000 (12:54 +0100)]
No new error if already failing
Miodrag Milanovic [Fri, 14 Feb 2020 12:12:05 +0000 (13:12 +0100)]
remove whitespace
Miodrag Milanovic [Fri, 14 Feb 2020 11:21:16 +0000 (12:21 +0100)]
Add expect option to logger command
Miodrag Milanovic [Thu, 13 Feb 2020 12:35:29 +0000 (13:35 +0100)]
Add new logger pass
Eddie Hung [Mon, 10 Feb 2020 18:17:23 +0000 (10:17 -0800)]
abc9: cleanup
Eddie Hung [Mon, 10 Feb 2020 16:31:01 +0000 (08:31 -0800)]
Merge pull request #1670 from rodrigomelo9/master
$readmem[hb] file inclusion is now relative to the Verilog file
N. Engelhardt [Mon, 10 Feb 2020 11:38:28 +0000 (12:38 +0100)]
Merge pull request #1669 from thasti/pyosys-attrs
Make RTLIL attributes accessible via pyosys
whitequark [Sun, 9 Feb 2020 20:29:16 +0000 (20:29 +0000)]
Merge pull request #1695 from whitequark/manual-explain-wire-upto-offset
manual: explain RTLIL::Wire::{upto,offset}
whitequark [Sun, 9 Feb 2020 14:54:07 +0000 (14:54 +0000)]
manual: explain RTLIL::Wire::{upto,offset}.
Eddie Hung [Fri, 7 Feb 2020 20:45:07 +0000 (12:45 -0800)]
Remove unnecessary comma
Eddie Hung [Fri, 7 Feb 2020 20:32:08 +0000 (12:32 -0800)]
Merge pull request #1687 from YosysHQ/eddie/fix_ystests
Fix shiftx2mux, fix yosys-tests
Eddie Hung [Fri, 7 Feb 2020 19:02:48 +0000 (11:02 -0800)]
techmap: fix shiftx2mux decomposition
Eddie Hung [Fri, 7 Feb 2020 16:27:45 +0000 (08:27 -0800)]
Fix misc.abc9.abc9_abc9_luts
Marcin Kościelnicki [Mon, 3 Feb 2020 17:37:28 +0000 (18:37 +0100)]
xilinx: Add support for LUT RAM on LUT4-based devices.
There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.
Fixes #1549
Marcin Kościelnicki [Mon, 3 Feb 2020 15:19:24 +0000 (16:19 +0100)]
xilinx: Initial support for LUT4 devices.
Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.
Fixes #1547
Eddie Hung [Fri, 7 Feb 2020 04:59:21 +0000 (20:59 -0800)]
Merge pull request #1685 from dh73/gowin
Removing cells_sim from GoWin bram techmap
whitequark [Fri, 7 Feb 2020 02:54:04 +0000 (02:54 +0000)]
Merge pull request #1683 from whitequark/write_verilog-memattrs
write_verilog: dump $mem cell attributes
Marcin Kościelnicki [Tue, 4 Feb 2020 14:35:47 +0000 (15:35 +0100)]
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
Marcin Kościelnicki [Mon, 3 Feb 2020 17:50:33 +0000 (18:50 +0100)]
xilinx: Add support for Spartan 3A DSP block RAMs.
Part of #1550
Eddie Hung [Thu, 6 Feb 2020 21:51:23 +0000 (13:51 -0800)]
Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_map
Fix/cleanup +/xilinx/arith_map.v
Diego H [Thu, 6 Feb 2020 20:38:29 +0000 (14:38 -0600)]
Removing cells_sim.v from bram techmap pass
Eddie Hung [Thu, 6 Feb 2020 19:25:07 +0000 (11:25 -0800)]
Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk
Eddie Hung [Tue, 21 Jan 2020 16:42:37 +0000 (08:42 -0800)]
Fix/cleanup +/xilinx/arith_map.v
Marcin Kościelnicki [Sat, 1 Feb 2020 14:27:27 +0000 (15:27 +0100)]
edif: more resilience to mismatched port connection sizes.
Fixes #1653.
whitequark [Thu, 6 Feb 2020 16:22:22 +0000 (16:22 +0000)]
write_verilog: dump $mem cell attributes.
The Verilog backend already dumps attributes on RTLIL::Memory objects
but not on `$mem` cells.
Rodrigo Alejandro Melo [Thu, 6 Feb 2020 13:45:40 +0000 (10:45 -0300)]
Added 'set -e' into tests/memfile/run-test.sh
Also added two checks for situations where the execution must fail.
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
Rodrigo Alejandro Melo [Thu, 6 Feb 2020 13:10:29 +0000 (10:10 -0300)]
Modified $readmem[hb] to use '\' or '/' according the OS
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
Eddie Hung [Thu, 6 Feb 2020 04:21:40 +0000 (20:21 -0800)]
Merge pull request #1682 from YosysHQ/eddie/opt_after_techmap
synth_*: call 'opt -fast' after 'techmap'
Eddie Hung [Thu, 6 Feb 2020 02:39:01 +0000 (18:39 -0800)]
synth_*: call 'opt -fast' after 'techmap'
Eddie Hung [Thu, 6 Feb 2020 00:41:09 +0000 (16:41 -0800)]
shiftx2mux: fix select out of bounds
Eddie Hung [Wed, 5 Feb 2020 22:56:26 +0000 (14:56 -0800)]
Merge pull request #1576 from YosysHQ/eddie/opt_merge_init
opt_merge: discard \init of '$' cells with 'Q' port when merging
Eddie Hung [Wed, 5 Feb 2020 22:55:57 +0000 (14:55 -0800)]
Merge pull request #1650 from YosysHQ/eddie/shiftx2mux
techmap LSB-first for compatible $shift/$shiftx cells
Eddie Hung [Wed, 5 Feb 2020 22:46:48 +0000 (14:46 -0800)]
abc9_ops: -reintegrate to use derived_type for box_ports
Eddie Hung [Wed, 5 Feb 2020 18:47:31 +0000 (10:47 -0800)]
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
Eddie Hung [Wed, 5 Feb 2020 18:31:18 +0000 (19:31 +0100)]
Merge pull request #1638 from YosysHQ/eddie/fix1631
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
Eddie Hung [Wed, 5 Feb 2020 17:59:40 +0000 (18:59 +0100)]
Merge pull request #1661 from YosysHQ/eddie/abc9_required
abc9: add support for required times
Stefan Biereigel [Mon, 3 Feb 2020 19:54:32 +0000 (20:54 +0100)]
remove namespace mention from inheritance information
Stefan Biereigel [Mon, 3 Feb 2020 19:21:02 +0000 (20:21 +0100)]
expose polymorphism through python wrappers
Rodrigo A. Melo [Mon, 3 Feb 2020 14:07:51 +0000 (11:07 -0300)]
Merge branch 'master' into master
Marcelina Kościelnicka [Mon, 3 Feb 2020 13:57:17 +0000 (14:57 +0100)]
Add opt_lut_ins pass. (#1673)
Rodrigo Alejandro Melo [Mon, 3 Feb 2020 13:56:11 +0000 (10:56 -0300)]
Merge branch 'master' of https://github.com/YosysHQ/yosys
Solved a conflict into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
Rodrigo Alejandro Melo [Mon, 3 Feb 2020 13:30:33 +0000 (10:30 -0300)]
Replaced strlen by GetSize into simplify.cc
As recommended in CodingReadme.
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
David Shah [Sun, 2 Feb 2020 18:12:28 +0000 (18:12 +0000)]
Merge pull request #1516 from YosysHQ/dave/dotstar
sv: Add support for wildcard port connections (.*)
David Shah [Fri, 22 Nov 2019 15:32:46 +0000 (15:32 +0000)]
Update CHANGELOG and README
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 22 Nov 2019 15:07:55 +0000 (15:07 +0000)]
sv: Improve handling of wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 22 Nov 2019 12:57:51 +0000 (12:57 +0000)]
sv: More tests for wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 22 Nov 2019 09:21:35 +0000 (09:21 +0000)]
hierarchy: Correct handling of wildcard port connections with default values
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 22 Nov 2019 09:16:37 +0000 (09:16 +0000)]
sv: Add tests for wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 22 Nov 2019 09:04:54 +0000 (09:04 +0000)]
hierarchy: Resolve SV wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 22 Nov 2019 08:24:01 +0000 (08:24 +0000)]
sv: Add lexing and parsing of .* (wildcard port conns)
Signed-off-by: David Shah <dave@ds0.me>
Rodrigo Alejandro Melo [Sun, 2 Feb 2020 15:33:34 +0000 (12:33 -0300)]
Removed 'synth' into tests/memfile/run-test.sh
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
Rodrigo Alejandro Melo [Sun, 2 Feb 2020 15:18:34 +0000 (12:18 -0300)]
Added content1.dat into tests/memfile
Modified run-test.sh to use it.
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
David Shah [Sun, 2 Feb 2020 14:53:46 +0000 (14:53 +0000)]
Merge pull request #1647 from YosysHQ/dave/sprintf
ast: Add support for $sformatf system function
David Shah [Sun, 2 Feb 2020 14:53:32 +0000 (14:53 +0000)]
Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly
synth_xilinx: add -dsp-multonly
Marcin Kościelnicki [Sun, 2 Feb 2020 10:26:00 +0000 (11:26 +0100)]
xilinx: use RAM32M/RAM64M for memories with two read ports
This fixes inefficient LUT RAM usage for memories with one write
and two read ports (commonly used as register files).
Rodrigo Alejandro Melo [Sun, 2 Feb 2020 01:48:03 +0000 (22:48 -0300)]
Removed a line jump into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
Rodrigo Alejandro Melo [Sun, 2 Feb 2020 01:44:06 +0000 (22:44 -0300)]
Added tests/memfile to 'make test' with an extra testcase
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
Rodrigo Alejandro Melo [Sat, 1 Feb 2020 20:41:10 +0000 (17:41 -0300)]
Added a test for the Memory Content File inclusion using $readmemb
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
Rodrigo Alejandro Melo [Sat, 1 Feb 2020 20:03:56 +0000 (17:03 -0300)]
Fixed a bug in the new feature of $readmem[hb] when an empty string is provided
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
David Shah [Mon, 27 Jan 2020 11:19:27 +0000 (11:19 +0000)]
xilinx_dsp: Add multonly scratchpad var to bypass
Signed-off-by: David Shah <dave@ds0.me>
Marcin Kościelnicki [Sat, 1 Feb 2020 09:21:19 +0000 (10:21 +0100)]
json: remove the 32-bit parameter special case
Before, the rules for encoding parameters in JSON were as follows:
- if the parameter is not a string:
- if it is exactly 32 bits long and there are no z or x bits, emit it
as an int
- otherwise, emit it as a string made of 0/1/x/z characters
- if the parameter is a string:
- if it contains only 0/1/x/z characters, append a space at the end
to distinguish it from a non-string
- otherwise, emit it directly
However, this caused a problem in the json11 parser used in nextpnr:
yosys emits unsigned ints, and nextpnr parses them as signed, using
the value of INT_MIN for values that overflow the signed int range.
This caused destruction of LUT5 initialization values. Since both
nextpnr and yosys parser can also accept 32-bit parameters in the
same encoding as other widths, let's just remove that special case.
The old behavior is still left behind a `-compat-int` flag, in case
someone relies on it.
Rodrigo Alejandro Melo [Sat, 1 Feb 2020 01:10:51 +0000 (22:10 -0300)]
Modified the new search for files of $readmem[hb] to be backward compatible
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
Rodrigo Alejandro Melo [Fri, 31 Jan 2020 21:20:22 +0000 (18:20 -0300)]
$readmem[hb] file inclusion is now relative to the Verilog file
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
Eddie Hung [Fri, 31 Jan 2020 09:34:13 +0000 (09:34 +0000)]
Merge pull request #1668 from gsomlo/gls-abc9-external
abc9: Fix regression breaking support for use of ABCEXTERNAL
Stefan Biereigel [Thu, 30 Jan 2020 20:26:37 +0000 (21:26 +0100)]
add inheritance for pywrap generators
Gabriel Somlo [Thu, 30 Jan 2020 20:12:43 +0000 (15:12 -0500)]
abc9: restore ability to use ABCEXTERNAL
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Claire Wolf [Thu, 30 Jan 2020 18:55:53 +0000 (19:55 +0100)]
Merge pull request #1667 from YosysHQ/clifford/verificnand
Add Verific support for OPER_REDUCE_NAND
Claire Wolf [Thu, 30 Jan 2020 17:05:16 +0000 (18:05 +0100)]
Merge pull request #1503 from YosysHQ/eddie/verific_help
`verific` pass to print help message when command syntax error
Claire Wolf [Thu, 30 Jan 2020 17:03:35 +0000 (18:03 +0100)]
Merge pull request #1654 from YosysHQ/eddie/sby_fix69
verific: unflatten struct ports
Claire Wolf [Thu, 30 Jan 2020 17:01:13 +0000 (18:01 +0100)]
Add Verific support for OPER_REDUCE_NAND
Signed-off-by: Claire Wolf <clifford@clifford.at>
Claire Wolf [Wed, 29 Jan 2020 16:01:24 +0000 (17:01 +0100)]
Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys
Also some minor fixes to the original PR.
Claire Wolf [Wed, 29 Jan 2020 14:27:11 +0000 (15:27 +0100)]
Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-check
opt_reduce: Call check() per run rather than per optimised cell
Claire Wolf [Wed, 29 Jan 2020 14:25:56 +0000 (15:25 +0100)]
Merge pull request #1665 from YosysHQ/clifford/edifkeep
Preserve wires with keep attribute in EDIF back-end
Claire Wolf [Wed, 29 Jan 2020 14:25:03 +0000 (15:25 +0100)]
Merge pull request #1659 from YosysHQ/clifford/experimental
Add log_experimental() and experimental() API and "yosys -x"
N. Engelhardt [Wed, 29 Jan 2020 14:21:28 +0000 (15:21 +0100)]
Merge pull request #1510 from pumbor/master
handle anonymous unions to fix #1080
Claire Wolf [Wed, 29 Jan 2020 13:07:11 +0000 (14:07 +0100)]
Preserve wires with keep attribute in EDIF back-end
Signed-off-by: Claire Wolf <clifford@clifford.at>
Miodrag Milanović [Wed, 29 Jan 2020 10:18:06 +0000 (11:18 +0100)]
Merge pull request #1559 from YosysHQ/efinix_test_fix
Fix for non-deterministic test
Eddie Hung [Wed, 29 Jan 2020 02:11:34 +0000 (18:11 -0800)]
Add "help -all" and "help -celltypes" sanity test
Eddie Hung [Wed, 29 Jan 2020 01:48:43 +0000 (17:48 -0800)]
synth_xilinx: cleanup help
Eddie Hung [Wed, 29 Jan 2020 01:41:57 +0000 (17:41 -0800)]
synth_xilinx: fix help when no active_design; fixes #1664
Marcin Kościelnicki [Thu, 21 Nov 2019 12:05:30 +0000 (13:05 +0100)]
xilinx: Add simulation model for DSP48 (Virtex 4).
Eddie Hung [Tue, 28 Jan 2020 20:46:18 +0000 (12:46 -0800)]
Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init
Eddie Hung [Tue, 28 Jan 2020 19:55:51 +0000 (11:55 -0800)]
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
Unpermute LUT ordering for ice40/ecp5/xilinx
Eddie Hung [Tue, 28 Jan 2020 18:37:16 +0000 (10:37 -0800)]
Add and use SigSpec::reverse()
Eddie Hung [Tue, 28 Jan 2020 18:17:47 +0000 (10:17 -0800)]
Fix unresolved conflict from #1573
Miodrag Milanovic [Tue, 28 Jan 2020 17:26:10 +0000 (18:26 +0100)]
Updated test to use assert-max
Claire Wolf [Tue, 28 Jan 2020 16:51:50 +0000 (17:51 +0100)]
Improve logging use of experimental features
Signed-off-by: Claire Wolf <clifford@clifford.at>
Claire Wolf [Tue, 28 Jan 2020 16:40:28 +0000 (17:40 +0100)]
Merge pull request #1567 from YosysHQ/eddie/sat_init_warning
sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
N. Engelhardt [Tue, 28 Jan 2020 16:24:54 +0000 (17:24 +0100)]
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate
synth_xilinx: error out if tristate without '-iopad'
David Shah [Tue, 28 Jan 2020 09:42:01 +0000 (09:42 +0000)]
opt_reduce: Call check() per run rather than per optimised cell
Signed-off-by: David Shah <dave@ds0.me>
Pepijn de Vos [Tue, 26 Nov 2019 11:56:06 +0000 (12:56 +0100)]
redirect fuser stderr to /dev/null
Claire Wolf [Tue, 28 Jan 2020 08:41:08 +0000 (09:41 +0100)]
Merge pull request #1553 from whitequark/manual-dffx
Document $dffe, $dffsr, $_DFFE_*, $_DFFSR_* cells
Eddie Hung [Mon, 27 Jan 2020 22:22:46 +0000 (14:22 -0800)]
abc9_ops: -check for negative arrival/required times
Eddie Hung [Mon, 27 Jan 2020 22:02:13 +0000 (14:02 -0800)]
Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
Just like Verilog...
Eddie Hung [Mon, 27 Jan 2020 21:56:16 +0000 (13:56 -0800)]
Import tests from #1628
Eddie Hung [Tue, 21 Jan 2020 20:29:07 +0000 (12:29 -0800)]
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
Now done in read_aiger
Eddie Hung [Mon, 27 Jan 2020 21:29:15 +0000 (13:29 -0800)]
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
Refactor `abc9` pass
Eddie Hung [Mon, 27 Jan 2020 20:30:39 +0000 (12:30 -0800)]
Fix typo
Eddie Hung [Mon, 27 Jan 2020 20:29:28 +0000 (12:29 -0800)]
Merge branch 'eddie/abc9_refactor' into eddie/abc9_required
Eddie Hung [Mon, 27 Jan 2020 19:18:21 +0000 (11:18 -0800)]
abc9_ops: add comments