ilo: mark some states dirty when they are really changed

The checks may seem redundant because cso_context handles them, but
util_blitter does not have access to cso_context.

ilo: clean up ilo_blitter_pipe_begin()

Document why certain states need to be saved, and fix a bug when blitting with
scissor enabled.

r600g: don't use the CB/DB CP COHER logic on r6xx

There are hw bugs.  Flush and inv event is sufficient.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=66837

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

configure: Avoid use of AC_CHECK_FILE for cross compiling

The AC_CHECK_FILE macro can't be used for cross compiling as it will
result in "error: cannot check for file existence when cross compiling".
Replace it with the AS_IF macro.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Jonathan Liu <net147@gmail.com>

nv30: fix KILL_IF breakage

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66858

gallium: fixup definitions of the rsq and sqrt

GLSL spec says that rsq is undefined for src<=0, but the D3D10
spec says it needs to be a NaN, so lets stop taking an absolute
value of the source which completely breaks that behavior. For
the gl program we can simply insert an extra abs instrunction
which produces the desired behavior there.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

util/u_format: Comment out half float denormal test case.

So that lp_test_format doesn't fail until we decide what should be done.

gallivm: Eliminate redundant lp_build_select calls.

lp_build_cmp already returns 0 / ~0, so the lp_build_select call is
unnecessary.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

tgsi: rename the TGSI fragment kill opcodes

TGSI_OPCODE_KIL and KILP had confusing names.  The former was conditional
kill (if any src component < 0).  The later was unconditional kill.
At one time KILP was supposed to work with NV-style condition
codes/predicates but we never had that in TGSI.

This patch renames both opcodes:
  TGSI_OPCODE_KIL -> KILL_IF   (kill if src.xyzw < 0)
  TGSI_OPCODE_KILP -> KILL     (unconditional kill)

Note: I didn't just transpose the opcode names to help ensure that I
didn't miss updating any code anywhere.

I believe I've updated all the relevant code and comments but I'm
not 100% sure that some drivers had this right in the first place.
For example, the radeon driver might have llvm.AMDGPU.kill and
llvm.AMDGPU.kilp mixed up.  Driver authors should review their code.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

tgsi: fix-up KILP comments

KILP is really unconditional fragment kill.

We've had KIL and KILP transposed forever.  I'll fix that next.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

tgsi: exec TGSI_OPCODE_SQRT as a scalar instruction, not vector

To align with the docs and the state tracker.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

tgsi: use X component of the second operand in exec_scalar_binary()

The code happened to work in the past since the (scalar) src args
effectively always have a swizzle of .xxxx, .yyyy, .zzzz, or .wwww so
whether you grab the X or Y component doesn't really matter.  Just
fixing the code to make it look right.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa: update glext.h to version 20130708

This update fixes the problem with duplicated typedefs for
GLclampf and GLclampd in the previous version.

It also changes some parameter types for glDebugMessageCallbackARB()
and glTransformFeedbackVaryingsEXT().

Note we should someday update the glapi-gen code so that it
understands void pointer parameters.  Currently, the Python code
only understands "GLvoid *" but not "void *".  Luckily, the
compilers don't seem to complain about mixing GLvoid and void.

mesa: fix Address Sanitizer (ASan) issue in _mesa_add_parameter()

If the size argument isn't a multiple of four, we would have read/
copied uninitialized memory.

Fixes an issue reported by Myles C. Maxfield <myles.maxfield@gmail.com>

mesa: simplify some _mesa_IsEnabled() queries

No need to test array->Enabled != 0 since the Enabled field can
only be 0 or 1.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>

os: add os_get_process_name() function

v2: explicitly test for BSD/APPLE, #warning for unexpected
environments.

mesa: whitespace, formatting, 80-column wrapping

softpipe: silence some MSVC warnings

hud: silence some MSVC warnings

util: add casts to silence MSVC warnings in u_blit.c

tgsi: s/unsigned/int/ to silence MSVC warning

mesa: s/unsigned/int/ to fix MSVC warning in uniforms.c

mesa: s/GLuint/GLint/ to silence MSVC warning in textore.c

mesa: add casts to fix MSVC warnings in multisample.c

mesa: s/GLint/GLuint/ to fix MSVC warnings in mipmap.c

mesa: fix inconsistent function declaration, definitions

To silence MSVC warnings that the declaration and definitions
were different.

mesa: add cast to silence MSVC warning

radeon/uvd: fall back to shader based decoding for MPEG2 on UVD 2.x v2

UVD 2.x doesn't support hardware decoding of MPEG2, just use shader
based decoding for those chipsets.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=66450
v2: fix interlacing as well

Signed-off-by: Christian König <christian.koenig@amd.com>

glsl: Avoid variable length arrays.

They are a non-standard GCC extension that's not widely supported by
other C/C++ compilers.

Use a dynamic array instead.

Trivial. Should fix the MSVC build.

glsl: Add support for C-style initializers.

Required by GL_ARB_shading_language_420pack.

Parts based on work done by Todd Previte and Ken Graunke, implementing
basic support for C-style initializers of arrays.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Add infrastructure for aggregate initializers.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Add an is_declaration field to ast_struct_specifier.

Will be used in a later commit to differentiate between a structure type
declaration and a variable declaration of a struct type. I.e., the
difference between

   struct S { float x; }; (is_declaration = true)

and

   S s;                   (is_declaration = false)

Also note that is_declaration = true for

   struct S { float x; } s;

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Track structs' ast_type_specifiers in symbol table.

Will be used in a future commit. An ast_type_specifier is stored (rather
than an ast_struct_specifier) with the idea that we may have more
general uses for this in the future. struct names are prefixed with
'#ast.' to avoid collisions with the glsl_types in the symbol table.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Add process_vec_mat_constructor() function.

Based largely on process_array_constructor().

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Separate code into process_record_constructor().

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Add copy-constructor for ast_struct_specifier.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Add a constructor for ast_type_specifier.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Clean up and clarify comment explaining initializer rules.

Reviewed-by: Ian Romanick <ian.d.romainck@intel.com>

glsl: Change type of is_array to bool.

Reviewed-by: Ian Romanick <ian.d.romainck@intel.com>

glsl: Add a comment to note what an exec_list is a list of.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romainck@intel.com>

glsl: Fix inverted conditional in error message.

The code float a[2] = float[2]( 3.4, 4.2, 5.0 ); previously generated
this:

   error: array constructor must have at least 2 parameters

when in fact it requires exactly two.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romainck@intel.com>

glsl: Add missing return error_value(ctx) in error path.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romainck@intel.com>

glsl: Remove unnecessary #include from ast_type.cpp.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romainck@intel.com>

glsl/build: build builtin_compiler with VISIBILITY_CFLAGS

libglslcore.la and libglcpp.la that are built with builtin_compiler are also
linked to by drivers not using libdricore.  Since there is no public symbol in
them, it is better to mark all symbols hidden.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Add comment explaining "row_major" parsing.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Mark "row_major" as not a reserved word in GLSL ES 3.0.

We mark ARB_uniform_buffer_object as enabled under ES 3 since it
contains that functionality, which tricked the compiler into tokenizing
"row_major".

Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Remove outdated FINISHME comment.

Explicit index support was added by commit 1256a5dc.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

radeon: bump libdrm_radeon requirement for CIK support

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

r600g: x/y coordinates must be divided by block dim in dma blit

Note: this is a candidate for the 9.1 branch.

Reviewed-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

r600g/sb: Fix Android build v2

Add the sb CXX files to the Android Makefile and also stop using some
c++11 features.

v2 (Vadim Girlin): use &bc[0] instead of bc.begin()

r600g/sb: improve math optimizations v2

This patch adds support for some math optimizations that are generally
considered unsafe, that's why they are currently disabled for compute
shaders.

GL requirements are less strict, so they are enabled for
for GL shaders by default. In case of any issues with
applications that rely on higher precision than guaranteed by GL,
'sbsafemath' option in R600_DEBUG allows to disable them.

v2 - always set proper src vector size for transformed instructions
   - check for clamp modifier in the expr_handler::fold_assoc

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>

st/xvmc/tests: avoid non portable error.h functions

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Christian König <christian.koenig@amd.com>

i965/blorp: Fix clear rectangle alignment in fast color clear

From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel >
Pixel Backend > MCS Buffer for Render Target(s) [DevIVB+]:
[DevHSW:GT3]: Clear rectangle must be aligned to two times
the number of pixels in the table shown below...
Observed no piglit, gles3conform regressions with this patch.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65744

winsys/intel: build with VISIBILITY_CFLAGS

There is no public symbol in this winsys.

ilo: reduce PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS to 12

So that there are at most (2^22 * 6) texels, lower than the 2^26 limit.

ilo: correctly initialize undefined registers in fs

Initialize all 4 channels of undefined registers (that is, TEMPs that are used
before being assigned) in FS.

radeonsi: Handle TGSI_OPCODE_DDX/Y using local memory

16 more little piglits.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

radeonsi: Handle TGSI_OPCODE_TXD

One more little piglit.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

util/u_math: Use xmmintrin.h whenever possible.

It seems  __builtin_ia32_ldmxcsr is only available on gcc and only when
-msse is used. xmmintrin.h/pmmintrin.h provide portable intrinsics, but
these too are only available with gcc when -msse/-msse3 are set.

scons build always sets -msse on x86 builds, but autotools doesn't seem
to.

We could try to get this working on gcc x86 without -msse by emitting
assembly, but I believe that in this day and age we really should be
building Mesa with -msse and -msse2.

ilo: honor surface padding requirements

The PRM specifies several padding requirements that we failed to honor.

util: treat denorm'ed floats like zero

The D3D10 spec is very explicit about treatment of denorm floats and
the behavior is exactly the same for them as it would be for -0 or
+0. This makes our shading code match that behavior, since OpenGL
doesn't care and on a few cpu's it's faster (worst case the same).
Float16 conversions will likely break but we'll fix them in a follow
up commit.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa: Set ProfileMask properly for core profile.

Fixes MESA_GL_VERSION_OVERRIDE=3.2 egl-create-context-verify-gl-flavor.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Delete intel_context entirely.

This makes brw_context inherit directly from gl_context; that was the
only thing left in intel_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::gen and gt fields to brw_context.

Most functions no longer use intel_context, so this patch additionally
removes the local "intel" variables to avoid compiler warnings.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::has_llc to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::is_<platform> flags to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move must_use/has_separate_stencil fields to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::has_hiz to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Free brw, not intel.

Things worked out in the past because both brw and intel share the same
memory address (by virtue of intel being the first member of brw).

However, brw is what actually gets rzalloc'd (brw_context.c:285), so
freeing that seems safer and more obvious.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Shorten context base class dereference chains.

ctx->DrawBuffer is much more sensible than brw->intel.ctx.DrawBuffer.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::has_swizzling to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::intelScreen to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Delete unused intel_context::driFd field.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Store brw_context as the DRI driver private, not intel_context.

Right now, they're interchangeable.  In the future, intel_context will
either go away or change purpose.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::driContext to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::NewGLState to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::upload to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::max_gtt_map_object_size to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::perf_debug to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::no_batch_wrap to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context's framerate throttling fields to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::stats_wm to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::batch to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::hw_ctx to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::bufmgr to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context's driconf flags to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::reduced_primitive to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move front buffer rendering fields from intel_context to brw.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::vtbl to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move intel_context::optionCache to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Pass brw_context to functions rather than intel_context.

This makes brw_context available in every function that used
intel_context.  This makes it possible to start migrating fields from
intel_context to brw_context.

Surprisingly, this actually removes some code, as functions that use
OUT_BATCH don't need to declare "intel"; they just use "brw."

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Remove pointless intel_context parameter from try_copy_propagate.

It's already part of the visitor class.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Add forward declarations of brw_context to a few places.

These files have forward declarations for intel_context.  This makes
brw_context available in the same places without further #include
monkeying.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Replace #include "intel_context.h" with brw_context.h.

brw_context.h includes intel_context.h, but additionally makes the
brw_context structure available.  Switching this allows us to start
using brw_context in more places.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move ctx->Const setup from intelInitContext to the new helper.

This also requires moving _mesa_init_point() to after the ctx->Const
initialization.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Split code to set ctx->Const values into a helper function.

brwCreateContext() has a lot of random things to do.  Factoring out the
part that initializes ctx->Const values and shader compiler options
makes the main function a bit easier to read.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i915: Remove i965+ chip names.

i965+ chipsets shouldn't ever hit this driver.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Remove i915 chip names.

i915 chipsets shouldn't ever hit this driver.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Replace intel_context:needs_ff_sync with intel->gen == 5.

Technically, needs_ff_sync was set on Gen5+, but it was only consulted
in the clipper threads and quad/lineloop decomposition code, which are
both Gen4-5 only.  So in reality it only identified Ironlake.

The named flag doesn't really clarify things, and seems like overkill.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Add missing newline to blorp color clear perf_debug message.

perf_debug() doesn't add a newline for you; without this, all the
INTEL_DEBUG=perf output was jumbled together.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>