mesa.git
5 years agodriconf: add Civ6Sub executable for Civilization 6
Marek Olšák [Tue, 19 Feb 2019 22:29:52 +0000 (17:29 -0500)]
driconf: add Civ6Sub executable for Civilization 6

I'm getting Civ6Sub instead of Civ6.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agoradeonsi: always enable NIR for Civilization 6 to fix corruption
Marek Olšák [Tue, 19 Feb 2019 22:21:20 +0000 (17:21 -0500)]
radeonsi: always enable NIR for Civilization 6 to fix corruption

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104602

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agoradeonsi: add driconf option radeonsi_enable_nir
Marek Olšák [Tue, 19 Feb 2019 22:20:01 +0000 (17:20 -0500)]
radeonsi: add driconf option radeonsi_enable_nir

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agomesa: Align doubles to a 64-bit starting boundary, even if packing.
Kenneth Graunke [Wed, 16 Jan 2019 06:35:02 +0000 (22:35 -0800)]
mesa: Align doubles to a 64-bit starting boundary, even if packing.

In the new Intel Iris driver, I am using Tim's new packed uniform
storage system.  It works great, with one caveat: our scalar compiler
backend assumes that uniform offsets will be aligned to the underlying
data type.  For example, doubles must be 64-bit aligned, floats 32-bit,
half-floats 16-bit, and so on.  It does not need any other padding.

Currently, _mesa_add_parameter aligns everything to 32-bit offsets,
creating doubles that have an unaligned offset.  This patch alters
that code to align doubles to 64-bit offsets.

This may be slightly less optimal for drivers which can support full
packing, and allow reads from unaligned offsets at no penalty.  We could
make this extra alignment optional.  However, it only comes into play
when intermixing double and single precision uniforms.  Doubles are
already not too common, and intermixed values (floats then doubles)
is probably even less common.  At most, we burn a single 32-bit slot
to the alignment, which is not that expensive.  So, it doesn't seem
worthwhile to add the extra complexity.

Eventually, we'll likely want to update this code to allow half-float
values to be packed tighter than 32-bit offsets.  At that point, we'll
probably want to revisit what drivers ultimately want, and add options.

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agocompiler: Make is_64bit(GL_*) helper more broadly available
Kenneth Graunke [Wed, 16 Jan 2019 08:03:39 +0000 (00:03 -0800)]
compiler: Make is_64bit(GL_*) helper more broadly available

I'd like to use this in the prog_parameter.c code, so I need to move it
into C, make it non-static, and so on.  This probably isn't the ideal
place for it, but I couldn't think of a better one.

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agogitlab-ci: automatically run the CI on pushes to `ci/*` branches
Eric Engestrom [Tue, 19 Feb 2019 13:09:11 +0000 (13:09 +0000)]
gitlab-ci: automatically run the CI on pushes to `ci/*` branches

Last commit limited the CI to master and MRs, but to avoid having to
manually trigger CI runs, let's add a 3rd, automatic way: by pushing to
a branch named `ci/*` (or `ci-*` or just `ci`) (which you can delete
afterwards, the pipeline results will remain).

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
5 years agogitlab-ci: limit the automatic CI to master and MRs
Eric Engestrom [Mon, 18 Feb 2019 19:01:28 +0000 (19:01 +0000)]
gitlab-ci: limit the automatic CI to master and MRs

Runs on random other branches (stables RCs, personal forks) can still be
triggered manually via the web interface, or an app using the API.

This should massively help with the current voracious state of our CI.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
5 years agotegra/autotools: add missing libdrm cflags
Eric Engestrom [Tue, 19 Feb 2019 11:18:07 +0000 (11:18 +0000)]
tegra/autotools: add missing libdrm cflags

Fixes: f1374805a86d0d506557 "drm-uapi: use local files, not system libdrm"
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109647
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
5 years agotegra/meson: add missing dep_libdrm
Eric Engestrom [Tue, 19 Feb 2019 10:57:58 +0000 (10:57 +0000)]
tegra/meson: add missing dep_libdrm

Fixes: f1374805a86d0d506557 "drm-uapi: use local files, not system libdrm"
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109645
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
5 years agoac/nir: implement half-float nir_op_ldexp
Rhys Perry [Thu, 6 Dec 2018 14:36:56 +0000 (14:36 +0000)]
ac/nir: implement half-float nir_op_ldexp

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoac/nir: implement half-float nir_op_frsq
Rhys Perry [Thu, 6 Dec 2018 14:35:23 +0000 (14:35 +0000)]
ac/nir: implement half-float nir_op_frsq

v2: don't use ac_get_onef()

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoac/nir: implement half-float nir_op_frcp
Rhys Perry [Thu, 6 Dec 2018 14:33:21 +0000 (14:33 +0000)]
ac/nir: implement half-float nir_op_frcp

v2: don't use ac_get_onef()

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoac/nir: make ac_build_fdiv support 16-bit floats
Rhys Perry [Thu, 6 Dec 2018 14:22:17 +0000 (14:22 +0000)]
ac/nir: make ac_build_fdiv support 16-bit floats

v2: don't use ac_get_onef()

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoac/nir: make ac_build_isign work on all bit sizes
Rhys Perry [Thu, 6 Dec 2018 14:27:01 +0000 (14:27 +0000)]
ac/nir: make ac_build_isign work on all bit sizes

v2: don't use ac_get_zero(), ac_get_one() and ac_int_of_size()

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoac/nir: make ac_build_clamp work on all bit sizes
Rhys Perry [Thu, 6 Dec 2018 14:23:31 +0000 (14:23 +0000)]
ac/nir: make ac_build_clamp work on all bit sizes

v2: don't use ac_get_zerof() and ac_get_onef()
v3: rename "intr" to "name"

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoac/nir: fix 64-bit nir_op_f2f16_rtz
Rhys Perry [Thu, 6 Dec 2018 15:00:21 +0000 (15:00 +0000)]
ac/nir: fix 64-bit nir_op_f2f16_rtz

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoac/nir: implement 8-bit nir_load_const_instr
Rhys Perry [Thu, 6 Dec 2018 14:41:11 +0000 (14:41 +0000)]
ac/nir: implement 8-bit nir_load_const_instr

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoradv: ensure export arguments are always float
Rhys Perry [Thu, 6 Dec 2018 12:11:00 +0000 (12:11 +0000)]
radv: ensure export arguments are always float

So that the signature is correct and consistent, the inputs to a export
intrinsic should always be 32-bit floats.

This and the previous commit fixes a large amount crashes from
dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_*
tests

Fixes: b722b29f10d ('radv: add support for 16bit input/output')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoradv: bitcast 16-bit outputs to integers
Rhys Perry [Thu, 6 Dec 2018 12:10:41 +0000 (12:10 +0000)]
radv: bitcast 16-bit outputs to integers

16-bit outputs are stored as 16-bit floats in the outputs array, so they
have to be bitcast.

Fixes: b722b29f10d ('radv: add support for 16bit input/output')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agogitlab-ci: use ccache to speed up builds
Eric Engestrom [Tue, 12 Feb 2019 16:59:27 +0000 (16:59 +0000)]
gitlab-ci: use ccache to speed up builds

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agov3d: Move i2b and f2b support into emit_comparison.
Eric Anholt [Tue, 19 Feb 2019 02:15:59 +0000 (18:15 -0800)]
v3d: Move i2b and f2b support into emit_comparison.

This lets us save a resolve to NIR true/false for ifs and discard_if.  No
change in shader-db.

5 years agov3d: Emit a simpler negate for the iabs implementation.
Eric Anholt [Tue, 19 Feb 2019 02:13:09 +0000 (18:13 -0800)]
v3d: Emit a simpler negate for the iabs implementation.

One program affected in my shader-db.

instructions in affected programs: 110 -> 108 (-1.82%)

5 years agov3d: Delay emitting ldvpm on V3D 4.x until it's actually used.
Eric Anholt [Fri, 15 Feb 2019 05:11:20 +0000 (21:11 -0800)]
v3d: Delay emitting ldvpm on V3D 4.x until it's actually used.

For V3D 3.x, we emitted the ldvpms all at the top so that we didn't need
to do VPM setup when the load_inputs are out of order.  For V3D 4.x, we
can reduce register pressure by delaying our loads until they're actually
needed.  This also avoids a bunch of silly MOVs in the pre-opt VIR dump.

total instructions in shared programs: 6421415 -> 6419933 (-0.02%)
total uniforms in shared programs: 2393139 -> 2393140 (<.01%)
total threads in shared programs: 153864 -> 153906 (0.03%)

5 years agov3d: Stop tracking num_inputs for VPM loads.
Eric Anholt [Fri, 15 Feb 2019 05:01:05 +0000 (21:01 -0800)]
v3d: Stop tracking num_inputs for VPM loads.

It's unused in the VS (since we need vattr_sizes[] anyway), so move it to
FS prog data.

5 years agov3d: Add a function to describe what the c->execute.file check means.
Eric Anholt [Thu, 14 Feb 2019 17:34:33 +0000 (09:34 -0800)]
v3d: Add a function to describe what the c->execute.file check means.

This is what pointed out that we were misusing the check for last_thrsw in
the previous commit.

5 years agov3d: Fix the check for "is the last thrsw inside control flow"
Eric Anholt [Thu, 14 Feb 2019 17:42:38 +0000 (09:42 -0800)]
v3d: Fix the check for "is the last thrsw inside control flow"

The execute.file check used to be good enough, until I stopped setting up
the execute mask for uniform ifs.

No known tests fixed, noticed while doing a refactor.

Fixes: 080506057310 ("v3d: Handle dynamically uniform IF statements with uniform control flow.")
5 years agov3d: Fix f2b32 behavior.
Eric Anholt [Wed, 13 Feb 2019 20:21:01 +0000 (12:21 -0800)]
v3d: Fix f2b32 behavior.

Now that we don't have the vir_PF() magic, it's obvious that we were doing
the wrong thing for f2b32 by allowing -0.0 to produce true instead of
false.

5 years agov3d: Kill off vir_PF(), which is hard to use right.
Eric Anholt [Wed, 13 Feb 2019 20:09:02 +0000 (12:09 -0800)]
v3d: Kill off vir_PF(), which is hard to use right.

You were allowed to pass in any old temp so that you could hopefully fold
the PF up into the def of the temp.  If we couldn't find one, it
implicitly generated a MOV(nop, reg).  However, that PF could have
different behavior depending on whether the def being folded into was a
float or int opcode, which the caller doesn't necessarily control.

Due to the fragility of the function, just switch all callers over to
vir_set_pf().  This also encourages the callers to use a _dest call for
the inst they're putting the PF on, eliminating a bunch of temps in the
pre-optimization VIR.

shader-db says the change is in the noise:

total instructions in shared programs: 6226247 -> 6227184 (0.02%)
instructions in affected programs: 851068 -> 852005 (0.11%)

5 years agov3d: Do bool-to-cond for discard_if as well.
Eric Anholt [Wed, 13 Feb 2019 21:42:41 +0000 (13:42 -0800)]
v3d: Do bool-to-cond for discard_if as well.

Turns this minimal conditional discard (glsl-fs-discard-01.shader_test):

0x3de0b086c5fe9000 fcmp.pushn  -, r1, r5; mov  r2, 0
0x3dec3086bbfc001f nop                  ; mov.ifa  r2, -1
0x3c047186bbe80000 nop                  ; mov.pushz  -, r2
0x3dea3186ba837000 setmsf.ifna  -, 0    ; nop

into:

0x3c00b186c582a000 fcmp.pushn  -, r2, r5; nop
0x3de83186ba837000 setmsf.ifa  -, 0     ; nop

total instructions in shared programs: 6229820 -> 6226247 (-0.06%)

5 years agov3d: Refactor bcsel and if condition handling.
Eric Anholt [Wed, 13 Feb 2019 20:39:08 +0000 (12:39 -0800)]
v3d: Refactor bcsel and if condition handling.

Both were doing the same thing to try to get a condition to predicate on.
Noticed when I wanted to do this for discard_if as well.

No change in shader-db.

5 years agov3d: Add a helper function for getting a nop register.
Eric Anholt [Wed, 13 Feb 2019 19:59:10 +0000 (11:59 -0800)]
v3d: Add a helper function for getting a nop register.

Just a little refactor to explain what's going on with QFILE_NULL.

5 years agov3d: Drop our hand-lowered nir_op_ffract.
Eric Anholt [Wed, 13 Feb 2019 19:22:07 +0000 (11:22 -0800)]
v3d: Drop our hand-lowered nir_op_ffract.

The NIR lowering works fine, though it causes some slight noise due to
what looks like choices about propagating constants up multiply chains
changing.

total instructions in shared programs: 6229671 -> 6229820 (<.01%)
total uniforms in shared programs: 2312171 -> 2312324 (<.01%)

5 years agov3d: Drop a perf note about merging unpack_half_*, which has been implemented.
Eric Anholt [Wed, 6 Feb 2019 21:19:06 +0000 (13:19 -0800)]
v3d: Drop a perf note about merging unpack_half_*, which has been implemented.

This is handled with copy-propagation now.

5 years agov3d: Fix incorrect flagging of ldtmu as writing r4 on v3d 4.x.
Eric Anholt [Tue, 5 Feb 2019 21:14:12 +0000 (13:14 -0800)]
v3d: Fix incorrect flagging of ldtmu as writing r4 on v3d 4.x.

Fixes some stalls in 3DMMES's main vertex shader.

total instructions in shared programs: 6280751 -> 6211270 (-1.11%)
instructions in affected programs: 2935050 -> 2865569 (-2.37%)

5 years agov3d: Use the early_fragment_tests flag for the shader's disable-EZ field.
Eric Anholt [Tue, 12 Feb 2019 22:39:40 +0000 (14:39 -0800)]
v3d: Use the early_fragment_tests flag for the shader's disable-EZ field.

Apparently we need disable-EZ flagged, not just "does Z writes".

Fixes
dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_depth_fbo
on 7278, even though it passed in simulation.

Signed-off-by: Eric Anholt <eric@anholt.net>
Fixes: 051a41d3d56e ("v3d: Add support for the early_fragment_tests flag.")
5 years agov3d: Sync indirect draws on the last rendering.
Eric Anholt [Fri, 8 Feb 2019 18:41:25 +0000 (10:41 -0800)]
v3d: Sync indirect draws on the last rendering.

Fixes intermittent fails in
dEQP-GLES31.functional.draw_indirect.compute_interop.separate.drawelements_compute_cmd_and_data_and_indices
and others (particularly when run as part of a CTS run)

5 years agov3d: Clear the GMP on initialization of the simulator.
Eric Anholt [Thu, 31 Jan 2019 00:22:02 +0000 (16:22 -0800)]
v3d: Clear the GMP on initialization of the simulator.

Otherwise, we might have pages accessible that shouldn't be and miss out
on errors.  This is unlikely for most tests since v3d_hw_get_mem() is big
enough that it'll be a freshly zeroed mmap, but if screens are destroyed
and recreated then we'd be reusing the old v3d_hw_get_mem() contents.

5 years agodocs: update calendar, add news item and link release notes for 18.3.4
Emil Velikov [Mon, 18 Feb 2019 18:38:14 +0000 (18:38 +0000)]
docs: update calendar, add news item and link release notes for 18.3.4

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
5 years agodocs: add sha256 checksums for 18.3.4
Emil Velikov [Mon, 18 Feb 2019 18:33:16 +0000 (18:33 +0000)]
docs: add sha256 checksums for 18.3.4

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit bfb5bdaa97272537567cdf1e6caf1c7db9f28aba)

5 years agodocs: add release notes for 18.3.4
Emil Velikov [Mon, 18 Feb 2019 18:23:55 +0000 (18:23 +0000)]
docs: add release notes for 18.3.4

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit b26488deadc3a8221d558a323dbe81dcf09115ab)

5 years agoi965: always enable EXT_float_blend
Ilia Mirkin [Wed, 13 Feb 2019 03:35:47 +0000 (22:35 -0500)]
i965: always enable EXT_float_blend

From the table in isl_format.c, it appears that all generations
support blending on 32-bit float surfaces.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agost/mesa: enable GL_EXT_float_blend when possible
Ilia Mirkin [Wed, 13 Feb 2019 03:34:25 +0000 (22:34 -0500)]
st/mesa: enable GL_EXT_float_blend when possible

If the driver supports PIPE_BIND_BLENABLE on RGBA32F, flip
EXT_float_blend on (which will affect ES3 contexts).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
5 years agomesa: add explicit enable for EXT_float_blend, and error condition
Ilia Mirkin [Wed, 13 Feb 2019 02:32:27 +0000 (21:32 -0500)]
mesa: add explicit enable for EXT_float_blend, and error condition

If EXT_float_blend is not supported, error out on blending of FP32
attachments in an ES2 context.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoradv: fix writing the alpha channel of MRT0 when alpha coverage is enabled
Samuel Pitoiset [Mon, 18 Feb 2019 16:42:10 +0000 (17:42 +0100)]
radv: fix writing the alpha channel of MRT0 when alpha coverage is enabled

This version is better and safer.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agofreedreno/ir3: handle quirky atomic dst for a6xx
Rob Clark [Mon, 18 Feb 2019 16:15:52 +0000 (11:15 -0500)]
freedreno/ir3: handle quirky atomic dst for a6xx

The new encoding returns a value via the 2nd src.  The legalize pass
needs to be aware of this to set the correct needs_sy flag, otherwise we
can, in cases where the atomic dst is not used, overwrite the register
that hardware will asynchronously load result into without (sy) flag, so
it gets clobbered by the atomic result.

This fixes a whole lot of rando ssbo+atomic fails, like
dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.highp_vec4.

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/a6xx: fix helper_invocation (sampler mask/id)
Rob Clark [Mon, 18 Feb 2019 15:34:06 +0000 (10:34 -0500)]
freedreno/a6xx: fix helper_invocation (sampler mask/id)

Since gl_HelperInvocation is lowered to:

  !((1 << sample_id) & sample_mask_in))

Not setting these enable bits was causing it be broken.  (And probably a
bunch of other stuff too.)

Fixes dEQP-GLES31.functional.shaders.helper_invocation.*

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agoradv: remove unused variable in gather_push_constant_info()
Samuel Pitoiset [Mon, 18 Feb 2019 12:30:16 +0000 (13:30 +0100)]
radv: remove unused variable in gather_push_constant_info()

Trivial.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoi965: scale factor changes should trigger recompile
Lionel Landwerlin [Fri, 15 Feb 2019 13:47:48 +0000 (13:47 +0000)]
i965: scale factor changes should trigger recompile

Found by inspection.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 3da858a6b990c5 ("intel/compiler: add scale_factors to sampler_prog_key_data")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
5 years agoradv: write the alpha channel of MRT0 when alpha coverage is enabled
Samuel Pitoiset [Fri, 15 Feb 2019 17:02:52 +0000 (18:02 +0100)]
radv: write the alpha channel of MRT0 when alpha coverage is enabled

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109597
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: use new LLVM 8 intrinsic when loading 16-bit values
Samuel Pitoiset [Thu, 14 Feb 2019 13:42:30 +0000 (14:42 +0100)]
ac: use new LLVM 8 intrinsic when loading 16-bit values

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: add ac_build_llvm8_tbuffer_load() helper
Samuel Pitoiset [Thu, 14 Feb 2019 13:42:29 +0000 (14:42 +0100)]
ac: add ac_build_llvm8_tbuffer_load() helper

It uses the new LLVM intrinsics.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agomesa: return NULL if we exceed MaxColorAttachments in get_fb_attachment
Tapani Pälli [Thu, 14 Feb 2019 07:02:31 +0000 (09:02 +0200)]
mesa: return NULL if we exceed MaxColorAttachments in get_fb_attachment

This fixes invalid access to Attachment array which would occur if caller
would exceed MaxColorAttachments. In practice this should not ever happen
because DiscardFramebufferEXT specifies only GL_COLOR_ATTACHMENT0 to be
valid and InvalidateFramebuffer will error out before but this should
make coverity happy.

v2: const, remove _EXT (Ian)

CID: 1442559
Fixes: 0c42b5f3cb9 "mesa: wire up InvalidateFramebuffer"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
5 years agopanfrost: Fix clipping region
Alyssa Rosenzweig [Sat, 16 Feb 2019 01:04:07 +0000 (01:04 +0000)]
panfrost: Fix clipping region

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Preserve w sign in perspective division
Alyssa Rosenzweig [Fri, 15 Feb 2019 06:38:23 +0000 (06:38 +0000)]
panfrost: Preserve w sign in perspective division

This fixes issues where polygons that should be culled (due to negative
w, for instance) may not be.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Cleanup mali_viewport (clipping) code
Alyssa Rosenzweig [Fri, 15 Feb 2019 06:45:07 +0000 (06:45 +0000)]
panfrost: Cleanup mali_viewport (clipping) code

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Swap order of tiled texture (de)alloc
Alyssa Rosenzweig [Fri, 15 Feb 2019 00:28:46 +0000 (00:28 +0000)]
panfrost: Swap order of tiled texture (de)alloc

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Free imported BOs
Alyssa Rosenzweig [Fri, 15 Feb 2019 00:15:14 +0000 (00:15 +0000)]
panfrost: Free imported BOs

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Fix various leaks unmapping resources
Alyssa Rosenzweig [Thu, 14 Feb 2019 06:17:19 +0000 (06:17 +0000)]
panfrost: Fix various leaks unmapping resources

v2: Don't check for NULL before free()

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agonir: Don't reassociate add/mul chains containing only constants
Kenneth Graunke [Fri, 15 Feb 2019 22:52:20 +0000 (14:52 -0800)]
nir: Don't reassociate add/mul chains containing only constants

The idea here is to reassociate a * (b * c) into (a * c) * b, when
b is a non-constant value, but a and c are constants, allowing them
to be combined.

But nothing was enforcing that 'b' must be non-constant, which meant
that running opt_algebraic in a loop would never terminate if the IR
contained non-folded constant expressions like 256 * 0.5 * 2.  Normally,
we call constant folding in such a loop too, but IMO it's better for
nir_opt_algebraic to be robust and not rely on that.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109581
Fixes: 32e266a9a58 i965: Compile fp64 funcs only if we do not have 64-bit hardware support
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
5 years agoi965: Assert the execobject handles match for this device
Chris Wilson [Thu, 14 Feb 2019 12:04:59 +0000 (12:04 +0000)]
i965: Assert the execobject handles match for this device

Object handles are local to the device fd, so double check we are not
mixing together objects from multiple screens on execbuf submission.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agofreedreno/a6xx: cache flush harder
Rob Clark [Fri, 8 Feb 2019 18:01:27 +0000 (13:01 -0500)]
freedreno/a6xx: cache flush harder

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/a6xx: compute support
Rob Clark [Thu, 7 Feb 2019 13:20:25 +0000 (08:20 -0500)]
freedreno/a6xx: compute support

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/a6xx: image/ssbo state emit
Rob Clark [Mon, 4 Feb 2019 18:30:34 +0000 (13:30 -0500)]
freedreno/a6xx: image/ssbo state emit

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/a6xx: border-color offset helper
Rob Clark [Wed, 6 Feb 2019 15:23:50 +0000 (10:23 -0500)]
freedreno/a6xx: border-color offset helper

Soon we'll need this logic to deal w/ image/SSBO case, so split out a
helper rather than duplicate the logic.

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/ir3: HIGH reg w/a for a6xx
Rob Clark [Mon, 11 Feb 2019 16:39:43 +0000 (11:39 -0500)]
freedreno/ir3: HIGH reg w/a for a6xx

It seems like some instructions (noticed this w/ cat3), cannot read HIGH
regs.. cat1 (mov/cov) can, and possibly some/all of cat2.

The blob seems to stick w/ an extra mov into low regs.  So lets do the
same.

This fixes WGID on a6xx, which unsurprisingly is related to a lot of
deqp compute fails.

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/ir3: add a6xx+ SSBO/image support
Rob Clark [Wed, 14 Nov 2018 20:49:49 +0000 (15:49 -0500)]
freedreno/ir3: add a6xx+ SSBO/image support

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/ir3: add a6xx instruction encoding
Rob Clark [Thu, 7 Feb 2019 16:02:45 +0000 (11:02 -0500)]
freedreno/ir3: add a6xx instruction encoding

For the handful of instructions that use a new encoding.

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/ir3: add image/ssbo <-> ibo/tex mapping
Rob Clark [Tue, 5 Feb 2019 20:33:57 +0000 (15:33 -0500)]
freedreno/ir3: add image/ssbo <-> ibo/tex mapping

Images and SSBOs don't map directly to the hw.  They end up being part
texture and part something else.  Starting with a6xx, the hack used for
a5xx to smash the image tex state into hw texture state starting from
MAX counting down won't work, because we start using tex state also for
SSBO read.

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/ir3: fix ncomp for _store_image() src
Rob Clark [Mon, 4 Feb 2019 15:22:38 +0000 (10:22 -0500)]
freedreno/ir3: fix ncomp for _store_image() src

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/ir3: split out a4xx+ instructions
Rob Clark [Wed, 14 Nov 2018 20:20:13 +0000 (15:20 -0500)]
freedreno/ir3: split out a4xx+ instructions

Note that image/ssbo support is currently only implemented for a5xx.
But the instruction encoding is the same for a4xx.

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/ir3: split out image helpers
Rob Clark [Wed, 14 Nov 2018 19:54:44 +0000 (14:54 -0500)]
freedreno/ir3: split out image helpers

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/a6xx: clean up some open-coded bits
Rob Clark [Thu, 7 Feb 2019 13:11:34 +0000 (08:11 -0500)]
freedreno/a6xx: clean up some open-coded bits

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/a6xx: move stream-out emit to helper
Rob Clark [Wed, 6 Feb 2019 13:01:31 +0000 (08:01 -0500)]
freedreno/a6xx: move stream-out emit to helper

Split out of the main fd6_emit() code, since it was already getting to
be a pretty giant function.

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/ir3: fix varying packing vs. tex sharp edge
Rob Clark [Thu, 14 Feb 2019 14:46:06 +0000 (09:46 -0500)]
freedreno/ir3: fix varying packing vs. tex sharp edge

We probably need to rethink how we detect which instruction first
defines higher register classes.  But for now, this at least fixes
the symptom.

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agoradv: fix invalid element type when filling vertex input default values
Samuel Pitoiset [Fri, 15 Feb 2019 13:14:03 +0000 (14:14 +0100)]
radv: fix invalid element type when filling vertex input default values

The elements added into a vector should have the same type as the
first one, otherwise this hits an assertion in LLVM.

Fixes: 4b3549c0846 ("radv: reduce the number of loaded channels for vertex input fetches")
reported-by: Philip Rebohle <philip.rebohle@tu-dortmund.de>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoi965: Removed the field etc_format from the struct intel_mipmap_tree
Eleni Maria Stea [Fri, 15 Feb 2019 13:29:44 +0000 (15:29 +0200)]
i965: Removed the field etc_format from the struct intel_mipmap_tree

After the previous changes to emulate the ETC/EAC formats using the
secondary shadow miptree, the etc_format field of the intel_mipmap_tree
struct became redundant and the remaining check that used it has been
replaced. (Nanley Chery)

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
5 years agoi965: Enabled the OES_copy_image extension on Gen 7 GPUs
Eleni Maria Stea [Fri, 15 Feb 2019 13:29:43 +0000 (15:29 +0200)]
i965: Enabled the OES_copy_image extension on Gen 7 GPUs

OES_copy_image extension was disabled on Gen7 due to the lack of support
for ETC2 images. Enabled it back. (Kenneth Graunke)

v2:
  - Removed the blank lines in the comments above OES_copy_image and
  OES_texture_view extensions in intel_extensions.c (Nanley Chery)

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
5 years agoi965: Fixed the CopyImageSubData for ETC2 on Gen < 8
Eleni Maria Stea [Fri, 15 Feb 2019 13:29:42 +0000 (15:29 +0200)]
i965: Fixed the CopyImageSubData for ETC2 on Gen < 8

For CopyImageSubData to copy the data during the 1st draw call, we need
to update the shadow tree right before the rendering.

v2:
  - Added assertion that the miptree doesn't need update at the time we
  update the texture surface. (Nanley Chery)

v3:
  - As we now update the tree before the rendering we don't need to copy
  the data during the unmap anymore. Removed the unnecessary update from
  the intel_miptree_unmap in intel_mipmap_tree.c (Nanley Chery)

v4:
  - Fixed unrelated empty line removal (Nanley Chery)
  - As now the intel_upate_etc_shadow of intel_mipmap_tree.c is only
  called inside its following function, we don't need to declare it at
  the top of the file anymore. (Nanley Chery)

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
5 years agoi965: Faking the ETC2 compression on Gen < 8 GPUs using two miptrees.
Eleni Maria Stea [Fri, 15 Feb 2019 13:29:41 +0000 (15:29 +0200)]
i965: Faking the ETC2 compression on Gen < 8 GPUs using two miptrees.

GPUs Gen < 8 cannot sample ETC2 formats. So far, they converted the
compressed EAC/ETC2 images to non-compressed RGBA images. When
GetCompressed* functions were called, the pixels were returned in this
RGBA format and not the compressed format that was expected.

Trying to fix this problem, we use a secondary shadow miptree to store the
decompressed data for the rendering and the main miptree to store the
compressed for the Get functions to work. Each time that the main miptree
is written with compressed data, we decompress them to RGB and update the
shadow. Then we use the shadow for rendering.

v2:
   - Fixes in the commit message (Nanley Chery)
   - Reversed the changes in brw_get_texture_swizzle and swapped the b, g
   values at the time that we decompress the data in the function:
   intel_miptree_update_etc_shadow of intel_mipmap_tree.c (Nanley Chery)
   - Simplified the format checks in the miptree_create function of the
   intel_mipmap_tree.c and reserved the call of the
   intel_lower_compressed_format for the case that we are faking the ETC
   support (Nanley Chery)
   - Removed the check for the auxiliary usage for the shadow miptree at
   creation (miptree_create of intel_mipmap_tree.c) as we won't use
   auxiliary buffers with these types of trees (Nanley Chery)
   - Set the etc_format of the non-ETC miptrees to MESA_FORMAT_NONE and
   removed the unecessary checks (Nanley Chery)
   - Fixed an unrelated indentation change (Nanley Chery)
   - Modified the function intel_miptree_finish_write to set the
   mt->shadow_needs_update to true to catch all the cases when we need to
   update the miptree (Nanley Chery)
   - In order to update the shadow miptree during the unmap of the
   main and always map the main (Nanley Chery) the following change was
   necessary: Splitted the previous update function that was updating all
   the mipmap levels and use two functions instead: one that updates one
   level and one that updates all of them. Used the first during unmap
   and the second before the rendering.
   - Removed the BRW_MAP_ETC_BIT flag and the mechanism to decide which
   miptree should be mapped each time and reversed all the changes in the
   higher level texture functions that upload data to textures as they
   aren't needed anymore.
   - Replaced the boolean needs_fake_etc with an inline function that
   checks when we need to fake the ETC compression (Nanley Chery)
   - Removed the initialization of the strides in the update function as
   the values will be overwritten by the intel_miptree_map call (Nanley
   Chery)
   - Used minify instead of division in the new update function
   intel_miptree_update_etc_shadow_levels in intel_mipmap_tree.c (Nanley
   Chery)
   - Removed the depth from the calculation of the number of slices in
   the new update function (intel_miptree_update_etc_shadow_levels of
   intel_mipmap_tree.c) as we don't need to support 3D ETC images.
   (Nanley Chery)

v3:
  - Renamed the rgba_fmt in function miptree_create
  (intel_mipmap_tree.c) to decomp_format as the format is not always in
  rgba order. (Nanley Chery)
  - Documented the new usage for the shadow miptree in the comment above
  the field in the intel_miptree struct in intel_mipmap_tree.h (Nanley
  Chery)
  - Removed the redundant flags from the mapping of the miptrees in
  intel_miptree_update_etc_shadow of intel_mipmap_tree.c (Nanley Chery)
  - Fixed the switch from surface's logical level to physical level in
  the intel_miptree_update_etc_shadow_levels of intel_mipmap_tree.c
  (Nanley Chery)
  - Excluded the Baytrail GPUs from the check for the ETC emulation as
  they support the ETC formats natively. (Nanley Chery)
  - Simplified the check if the format is BGRA in
  intel_miptree_update_etc_shadow of intel_mipmap_tree.c (Nanley Chery)

v4:
  - Removed the functions intel_miptree_(map|unmap)_etc and the check if
   we need to call them as with the new changes, they became unreachable.
   (Nanley Chery)
  - We'd rather calculate the level width and height using the shadow
  miptree instead of the main in intel_miptree_update_etc_shadow_levels of
  intel_mipmap_tree.c (Nanley Chery)
  - Fixed the format in the mt_surface_usage, set at the miptree creation,
   in miptree_create of intel_mipmap_tree.c (Nanley Chery)

v5:
  - Fixed the levels calculations in intel_mipmap_tree.c (Nanley Chery)
  - Update the flag shadow_needs_update outside the function
  intel_miptree_update_etc_shadow (Nanley Chery)
  - Fixed indentation error (Nanley Chery)

v6:
  - Fixed typo in commit message (Nanley Chery)
  - Simplified the assignment of the mt_fmt in the miptree_create of the
  intel_mipmap_tree.c (Nanley Chery)
  - Combined declarations and assignments where it was possible in the
  intel_miptree_update_etc_shadow and
  intel_miptree_update_etc_shadow_levels of the intel_mipmap_tree.c
  (Nanley Chery)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81843
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104272
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
5 years agoi965: Rename intel_mipmap_tree::r8stencil_* -> ::shadow_*
Nanley Chery [Thu, 14 Feb 2019 00:22:34 +0000 (16:22 -0800)]
i965: Rename intel_mipmap_tree::r8stencil_* -> ::shadow_*

Use more generic field names. We'll reuse these fields for a workaround
with ASTC miptrees.

Reviewed-by: Eleni Maria Stea <estea@igalia.com>
5 years agonir: remove simple dead if detection from nir_opt_dead_cf()
Timothy Arceri [Thu, 14 Feb 2019 01:27:25 +0000 (12:27 +1100)]
nir: remove simple dead if detection from nir_opt_dead_cf()

This was probably useful when it was first written, however it
looks to be no longer necessary.

As far as I can tell these days dce is smart enough to remove useless
instructions from if branches. Once this is done
nir_opt_peephole_select() will end up removing the empty if.

Removing this support reduces the dolphin uber shader compilation
time spent in nir_opt_dead_cf() by a little over 7x.

No shader-db changes on i965 or radeonsi.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
5 years agoswr/rast: Add translation support to streamout
Alok Hota [Fri, 14 Sep 2018 14:45:26 +0000 (09:45 -0500)]
swr/rast: Add translation support to streamout

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
5 years agoswr/rast: simdlib cleanup, clipper stack space fixes
Alok Hota [Thu, 13 Sep 2018 21:12:12 +0000 (16:12 -0500)]
swr/rast: simdlib cleanup, clipper stack space fixes

Reduce stack space used by clipper, which had lead to crashes in some
versions for MSVC

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
5 years agoswr/rast: convert DWORD->uint32_t, QWORD->uint64_t
Alok Hota [Wed, 12 Sep 2018 15:51:36 +0000 (10:51 -0500)]
swr/rast: convert DWORD->uint32_t, QWORD->uint64_t

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
5 years agoswr/rast: Refactor scratch space variable names
Alok Hota [Tue, 11 Sep 2018 22:20:19 +0000 (17:20 -0500)]
swr/rast: Refactor scratch space variable names

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
5 years agoswr/rast: FP consistency between POSH/RENDER pipes
Alok Hota [Tue, 28 Aug 2018 17:23:31 +0000 (12:23 -0500)]
swr/rast: FP consistency between POSH/RENDER pipes

- Ensure all threads have optimal floating-point control state
- Disable auto-generation of fused FP ops for VERTEX shader stage
- Disable "fast" FP ops for VERTEX shader stage

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
5 years agoswr/rast: Move knob defaults to generated cpp file
Alok Hota [Fri, 24 Aug 2018 00:25:39 +0000 (19:25 -0500)]
swr/rast: Move knob defaults to generated cpp file

Reduces amount of compile churn when testing different default values

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
5 years agoswr/rast: Flip BitScanReverse index calculation
Alok Hota [Tue, 14 Aug 2018 17:36:00 +0000 (12:36 -0500)]
swr/rast: Flip BitScanReverse index calculation

The intrinsic returns the number of leading zeros, not the bit number of
the first nonzero, so just flip it based on the mask size

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
5 years agoswr/rast: Correctly align 64-byte spills/fills
Alok Hota [Mon, 13 Aug 2018 23:14:45 +0000 (18:14 -0500)]
swr/rast: Correctly align 64-byte spills/fills

Fixes crashes on some compute shaders when running on AVX512

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
5 years agoswr/rast: Disable use of __forceinline by default
Alok Hota [Thu, 2 Aug 2018 17:03:29 +0000 (12:03 -0500)]
swr/rast: Disable use of __forceinline by default

- Was not useful to inline in release builds
- FORCEINLINE can be used if absolutely necessary

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
5 years agoswr/rast: Convert system memory pointers to gfxptr_t
Alok Hota [Thu, 19 Jul 2018 15:32:55 +0000 (10:32 -0500)]
swr/rast: Convert system memory pointers to gfxptr_t

Fulfills an unused internal interface

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
5 years agoradv: Use correct num formats to detect whether we should be use 1.0 or 1.
Bas Nieuwenhuizen [Fri, 15 Feb 2019 17:02:46 +0000 (18:02 +0100)]
radv: Use correct num formats to detect whether we should be use 1.0 or 1.

normalized and scaled formats also return floats.

Fixes: 4b3549c0846 ("radv: reduce the number of loaded channels for vertex input fetches")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agonir/algebraic: Simplify comparison with sequential integers starting with 0
Ian Romanick [Tue, 12 Feb 2019 00:47:34 +0000 (16:47 -0800)]
nir/algebraic: Simplify comparison with sequential integers starting with 0

All of the affected shaders are Unreal4 demos.

All Gen6+ platforms had similar results. (Skylake shown)
total instructions in shared programs: 15437170 -> 15437001 (<.01%)
instructions in affected programs: 21536 -> 21367 (-0.78%)
helped: 43
HURT: 0
helped stats (abs) min: 1 max: 4 x̄: 3.93 x̃: 4
helped stats (rel) min: 0.68% max: 1.01% x̄: 0.80% x̃: 0.80%
95% mean confidence interval for instructions value: -4.07 -3.79
95% mean confidence interval for instructions %-change: -0.83% -0.77%
Instructions are helped.

total cycles in shared programs: 383007896 -> 383007378 (<.01%)
cycles in affected programs: 158640 -> 158122 (-0.33%)
helped: 38
HURT: 4
helped stats (abs) min: 1 max: 48 x̄: 13.89 x̃: 6
helped stats (rel) min: 0.03% max: 1.01% x̄: 0.33% x̃: 0.19%
HURT stats (abs)   min: 2 max: 3 x̄: 2.50 x̃: 2
HURT stats (rel)   min: 0.06% max: 0.09% x̄: 0.08% x̃: 0.08%
95% mean confidence interval for cycles value: -16.90 -7.77
95% mean confidence interval for cycles %-change: -0.39% -0.19%
Cycles are helped.

Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 8213746 -> 8213745 (<.01%)
instructions in affected programs: 127 -> 126 (-0.79%)
helped: 1
HURT: 0

total cycles in shared programs: 187734146 -> 187734144 (<.01%)
cycles in affected programs: 2132 -> 2130 (-0.09%)
helped: 1
HURT: 0

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agonir/algebraic: Convert some f2u to f2i
Ian Romanick [Wed, 13 Feb 2019 03:59:39 +0000 (19:59 -0800)]
nir/algebraic: Convert some f2u to f2i

Section 5.4.1 (Conversion and Scalar Constructors) of the GLSL 4.60 spec
says:

     It is undefined to convert a negative floating-point value to an
     uint.

Assuming that (uint)some_float behaves like (uint)(int)some_float allows
some optimizations in the i965 backend to proceed.

This basically undoes the small amount of damage done by
"intel/compiler: Avoid propagating inequality cmods if types are
different".

v2: Replicate part of the commit message as a comment in the code.
Suggested by Jason.

shader-db results compairing *before* "intel/compiler: Avoid propagating
inequality cmods if types are different" and after this commit:

Skylake
total cycles in shared programs: 383007996 -> 383007896 (<.01%)
cycles in affected programs: 85208 -> 85108 (-0.12%)
helped: 13
HURT: 8
helped stats (abs) min: 2 max: 26 x̄: 10.77 x̃: 6
helped stats (rel) min: 0.09% max: 0.65% x̄: 0.28% x̃: 0.14%
HURT stats (abs)   min: 2 max: 12 x̄: 5.00 x̃: 3
HURT stats (rel)   min: 0.04% max: 0.32% x̄: 0.12% x̃: 0.07%
95% mean confidence interval for cycles value: -9.31 -0.21
95% mean confidence interval for cycles %-change: -0.24% <.01%
Cycles are helped.

Broadwell
total cycles in shared programs: 415251194 -> 415251370 (<.01%)
cycles in affected programs: 83750 -> 83926 (0.21%)
helped: 7
HURT: 13
helped stats (abs) min: 10 max: 12 x̄: 11.43 x̃: 12
helped stats (rel) min: 0.30% max: 0.30% x̄: 0.30% x̃: 0.30%
HURT stats (abs)   min: 2 max: 36 x̄: 19.69 x̃: 22
HURT stats (rel)   min: 0.05% max: 0.89% x̄: 0.44% x̃: 0.47%
95% mean confidence interval for cycles value: 0.76 16.84
95% mean confidence interval for cycles %-change: <.01% 0.37%
Inconclusive result (%-change mean confidence interval includes 0).

Haswell
total instructions in shared programs: 13823885 -> 13823886 (<.01%)
instructions in affected programs: 2249 -> 2250 (0.04%)
helped: 0
HURT: 1

total cycles in shared programs: 390094243 -> 390094001 (<.01%)
cycles in affected programs: 85640 -> 85398 (-0.28%)
helped: 15
HURT: 6
helped stats (abs) min: 4 max: 26 x̄: 18.53 x̃: 18
helped stats (rel) min: 0.09% max: 0.66% x̄: 0.47% x̃: 0.42%
HURT stats (abs)   min: 2 max: 14 x̄: 6.00 x̃: 2
HURT stats (rel)   min: 0.04% max: 0.37% x̄: 0.15% x̃: 0.04%
95% mean confidence interval for cycles value: -17.36 -5.69
95% mean confidence interval for cycles %-change: -0.44% -0.14%
Cycles are helped.

Ivy Bridge
total cycles in shared programs: 180986448 -> 180986552 (<.01%)
cycles in affected programs: 34835 -> 34939 (0.30%)
helped: 0
HURT: 10
HURT stats (abs)   min: 2 max: 18 x̄: 10.40 x̃: 10
HURT stats (rel)   min: 0.06% max: 0.36% x̄: 0.28% x̃: 0.30%
95% mean confidence interval for cycles value: 4.67 16.13
95% mean confidence interval for cycles %-change: 0.20% 0.35%
Cycles are HURT.

Sandy Bridge
total cycles in shared programs: 154603969 -> 154603970 (<.01%)
cycles in affected programs: 171514 -> 171515 (<.01%)
helped: 25
HURT: 14
helped stats (abs) min: 1 max: 4 x̄: 1.80 x̃: 1
helped stats (rel) min: 0.02% max: 0.10% x̄: 0.04% x̃: 0.04%
HURT stats (abs)   min: 1 max: 8 x̄: 3.29 x̃: 3
HURT stats (rel)   min: 0.03% max: 0.28% x̄: 0.10% x̃: 0.11%
95% mean confidence interval for cycles value: -0.91 0.96
95% mean confidence interval for cycles %-change: -0.02% 0.04%
Inconclusive result (value mean confidence interval includes 0).

No changes on Iron Lake or GM45.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agointel/compiler/test: Add unit test for mismatched signedness comparison
Matt Turner [Mon, 11 Feb 2019 21:41:32 +0000 (13:41 -0800)]
intel/compiler/test: Add unit test for mismatched signedness comparison

v2 (idr): Move adding the test to after adding the fix.  Reordering the
two commits prevents possible headaches for git-bisect with scripts that
always do 'ninja check'.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109404
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
5 years agointel/compiler: Avoid propagating inequality cmods if types are different
Matt Turner [Tue, 12 Feb 2019 00:02:15 +0000 (16:02 -0800)]
intel/compiler: Avoid propagating inequality cmods if types are different

v2: Fix silly bug in logic.  s/||/&&/

All but one of the affected shaders is in an Unreal4 demo.  The other is
in Tomb Raider.  All of the cases that Ian investigated appear to be
sequences like the following

    if (int(uint(some_float)) < 0) /* other relations too */
        ...

At least in Tomb Raider, it's not obvious that this sequence came from
the original shader.

In some of the Unreal demos, the shader contains code like

    if (int(uint(textureLod(...))) > 0)
        ...

which explicitly generates the offending sequence.

All Gen6+ platforms had similar results (Skylake shown):
total instructions in shared programs: 15437170 -> 15437187 (<.01%)
instructions in affected programs: 4492 -> 4509 (0.38%)
helped: 0
HURT: 17
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.05% max: 0.73% x̄: 0.66% x̃: 0.73%
95% mean confidence interval for instructions value: 1.00 1.00
95% mean confidence interval for instructions %-change: 0.57% 0.75%
Instructions are HURT.

total cycles in shared programs: 383007996 -> 383007992 (<.01%)
cycles in affected programs: 20542 -> 20538 (-0.02%)
helped: 6
HURT: 7
helped stats (abs) min: 2 max: 6 x̄: 5.33 x̃: 6
helped stats (rel) min: 0.11% max: 0.36% x̄: 0.32% x̃: 0.36%
HURT stats (abs)   min: 4 max: 4 x̄: 4.00 x̃: 4
HURT stats (rel)   min: 0.27% max: 0.27% x̄: 0.27% x̃: 0.27%
95% mean confidence interval for cycles value: -3.30 2.69
95% mean confidence interval for cycles %-change: -0.19% 0.19%
Inconclusive result (value mean confidence interval includes 0).

No changes on Iron Lake or GM45.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109404
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: nagrigoriadis@gmail.com
Tested-by: Danylo Piliaiev <danylo.piliaiev@gmail.com>
5 years agointel/compiler/test: Set devinfo->gen = 7
Matt Turner [Mon, 11 Feb 2019 20:23:16 +0000 (12:23 -0800)]
intel/compiler/test: Set devinfo->gen = 7

We emit an FBL instruction which only exists since Gen7. This prevents
the test from segfaulting when run with TEST_DEBUG=1.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
5 years agogallium/auxiliary/vl: Add video compositor compute shader render
James Zhu [Fri, 1 Feb 2019 15:01:59 +0000 (10:01 -0500)]
gallium/auxiliary/vl: Add video compositor compute shader render

Add compute shader initilization, assign and cleanup in vl_compositor API.
Set video compositor compute shader render as default when pipe support it.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
5 years agogallium/auxiliary/vl: Add compute shader to support video compositor render
James Zhu [Fri, 1 Feb 2019 14:24:48 +0000 (09:24 -0500)]
gallium/auxiliary/vl: Add compute shader to support video compositor render

Add compute shader to support video compositor render.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
5 years agogallium/auxiliary/vl: Rename csc_matrix and increase its size.
James Zhu [Fri, 1 Feb 2019 14:56:13 +0000 (09:56 -0500)]
gallium/auxiliary/vl: Rename csc_matrix and increase its size.

Rename csc_matrix to shader_params, and increase shader_params size
to store more constants for compute shader,

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>