Florent Kermarrec [Wed, 20 Feb 2019 21:45:19 +0000 (22:45 +0100)]
platforms/versa_ecp5: add ddram pins
Florent Kermarrec [Fri, 15 Feb 2019 23:08:24 +0000 (00:08 +0100)]
soc/tools/remote/comm_uart: be sure to flush in waiting bytes before read and write
Florent Kermarrec [Thu, 14 Feb 2019 09:41:13 +0000 (10:41 +0100)]
soc/cores/clock: add actual clk_freqs to config
Florent Kermarrec [Tue, 12 Feb 2019 11:12:40 +0000 (12:12 +0100)]
soc_sdram: add use_full_memory_we parameter to allow disabling vivado workaround on small l2 caches
Florent Kermarrec [Mon, 11 Feb 2019 18:41:12 +0000 (19:41 +0100)]
build/lattice/common/LatticeECXTrellisImpl: add support for nbits == 1
Florent Kermarrec [Mon, 11 Feb 2019 08:23:39 +0000 (09:23 +0100)]
soc_sdram: don't generate sdram initialization error message when integrated_main_ram is used
Florent Kermarrec [Thu, 7 Feb 2019 15:23:55 +0000 (16:23 +0100)]
build/lattice/common: add LatticeiCE40DDROutput
Florent Kermarrec [Fri, 1 Feb 2019 22:39:17 +0000 (23:39 +0100)]
platforms/nexys_video: add LPC transceivers pins
Florent Kermarrec [Wed, 30 Jan 2019 13:01:19 +0000 (14:01 +0100)]
build/sim: add jtagremote module (thanks LamdaConcept)
Florent Kermarrec [Tue, 29 Jan 2019 11:45:59 +0000 (12:45 +0100)]
soc/integration/soc_core: allow disabling wishbone timeout
Florent Kermarrec [Sun, 27 Jan 2019 07:23:44 +0000 (08:23 +0100)]
soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles
Florent Kermarrec [Wed, 23 Jan 2019 07:40:47 +0000 (08:40 +0100)]
boards/platform/kc705: add sfp pins (both tx and rx)
Florent Kermarrec [Tue, 22 Jan 2019 11:50:05 +0000 (12:50 +0100)]
soc/cores/clock: add USIDELAYCTRL
Florent Kermarrec [Tue, 22 Jan 2019 08:08:35 +0000 (09:08 +0100)]
soc/integration/soc_sdram: round port.data_width/l2_size to nearest power of 2 when it's not the case
With ECC configurations, native port data_width is not necessarily a power of 2.
Florent Kermarrec [Mon, 21 Jan 2019 09:39:34 +0000 (10:39 +0100)]
boards/targets: improve presentation
Florent Kermarrec [Mon, 21 Jan 2019 09:36:28 +0000 (10:36 +0100)]
boards/platforms/kcu105: add si570_refclk
Florent Kermarrec [Mon, 21 Jan 2019 09:21:19 +0000 (10:21 +0100)]
boards/platforms/kc705: use vivado as default programmer
Florent Kermarrec [Wed, 16 Jan 2019 21:05:52 +0000 (22:05 +0100)]
soc/cores/clock: allow ClockSignal to be used for clkin
Florent Kermarrec [Fri, 11 Jan 2019 14:01:58 +0000 (15:01 +0100)]
build/sim/core: fix coverage
Florent Kermarrec [Fri, 11 Jan 2019 12:51:15 +0000 (13:51 +0100)]
build/sim/core: set -Wno-BLKANDNBLK (prevent blocking/non-blocking assigns on a same structure in system verilog)
Florent Kermarrec [Fri, 11 Jan 2019 12:39:09 +0000 (13:39 +0100)]
build/sim/core: set unroll-count to 256 to prevent Error-BLKLOOPINIT
Florent Kermarrec [Thu, 10 Jan 2019 15:03:09 +0000 (16:03 +0100)]
build/sim: disable Warning-WIDTH
Florent Kermarrec [Wed, 9 Jan 2019 09:28:24 +0000 (10:28 +0100)]
soc/cores/cpu/vexriscv: set default variant to None in add_sources
Florent Kermarrec [Wed, 9 Jan 2019 07:32:17 +0000 (08:32 +0100)]
soc/cores/cpu/vexriscv: move verilog variant selection to add_sources
Florent Kermarrec [Tue, 8 Jan 2019 13:14:28 +0000 (14:14 +0100)]
targets/kcu105: use USMMCM
Florent Kermarrec [Tue, 8 Jan 2019 12:50:12 +0000 (13:50 +0100)]
targets: pass speedgrade to S7PLL/S7MMCM
Florent Kermarrec [Tue, 8 Jan 2019 12:19:49 +0000 (13:19 +0100)]
soc/cores/clock: add Xilinx Ultrascale PLL/MMCM
Florent Kermarrec [Sun, 6 Jan 2019 17:59:37 +0000 (18:59 +0100)]
boards: avoid duplicating platforms that can be found in migen/litex-buildenv
The platforms that are kept are the ones used for litex development.
Florent Kermarrec [Sat, 5 Jan 2019 09:57:37 +0000 (10:57 +0100)]
soc/integration/cpu_interface: generate name for Memories in get_csr_header
Florent Kermarrec [Thu, 3 Jan 2019 09:38:14 +0000 (10:38 +0100)]
utils/litex_server: allow specify uart_baudrate as float
Florent Kermarrec [Fri, 28 Dec 2018 14:58:28 +0000 (15:58 +0100)]
targets/ulx3s: use pll for phase shift, enable refresh, memtest ok
Florent Kermarrec [Fri, 28 Dec 2018 14:14:28 +0000 (15:14 +0100)]
targets/versa_ecp5: use pll for phase shift, enable refresh, memtest ok
Florent Kermarrec [Fri, 28 Dec 2018 14:03:05 +0000 (15:03 +0100)]
soc/cores/clock/ECP5PLL: add basic phase support
Florent Kermarrec [Thu, 27 Dec 2018 19:36:50 +0000 (20:36 +0100)]
litex_sim: simplify, change sdram module and enable sdram refresh.
Florent Kermarrec [Sun, 23 Dec 2018 18:47:48 +0000 (19:47 +0100)]
.gitmodules: use our copy of tapcfg since https://github.com/nizox/tapcfg no longer exists.
Florent Kermarrec [Fri, 21 Dec 2018 08:57:52 +0000 (09:57 +0100)]
build/sim/verilator: compile sim just before running and not when building.
Tim Ansell [Thu, 20 Dec 2018 19:35:42 +0000 (11:35 -0800)]
Merge pull request #144 from mithro/nextpnr-migen-update
Integrate latest migen changes for lattice/icestorm.
Tim 'mithro' Ansell [Thu, 20 Dec 2018 19:31:07 +0000 (11:31 -0800)]
Integrate latest migen changes for lattice/icestorm.
Integrated up to
37db6bb52532b6d1c6bc8b724c2e8c6a38546c2a.
Florent Kermarrec [Thu, 20 Dec 2018 09:33:32 +0000 (10:33 +0100)]
build/sim: handle verilog $finish and if coverage is enabled, write report at the end of the simulation.
Florent Kermarrec [Wed, 19 Dec 2018 10:33:32 +0000 (11:33 +0100)]
platforms/kcu105: change internal vref to 0.84v (recommended value for ddr4)
Florent Kermarrec [Wed, 19 Dec 2018 10:19:47 +0000 (11:19 +0100)]
bios/sdram: only show read delays when they are valid.
Florent Kermarrec [Wed, 19 Dec 2018 10:18:19 +0000 (11:18 +0100)]
bios/sdram: reduce write leveling scan range
Florent Kermarrec [Wed, 19 Dec 2018 08:14:26 +0000 (09:14 +0100)]
soc/cores/clock: remove return on S7PLL.create_clkout
Florent Kermarrec [Tue, 18 Dec 2018 20:38:23 +0000 (21:38 +0100)]
platforms/kcu105: set internal vref on ddr4 banks
Florent Kermarrec [Tue, 18 Dec 2018 10:25:21 +0000 (11:25 +0100)]
update Ultrascale DDRPHY
Tim Ansell [Tue, 18 Dec 2018 05:24:15 +0000 (21:24 -0800)]
Merge pull request #141 from mithro/xst-fix
Fix `-vlgincdir` for xst.
Tim 'mithro' Ansell [Tue, 18 Dec 2018 05:11:14 +0000 (21:11 -0800)]
Fix `-vlgincdir` for xst.
The command line is of the form;
```
-vlgincdir {"path1" "path2"}
```
Fixes the following error;
```
WARNING:Xst:3164 - Option "-vlgincdir" found multiple times in the command line. Only the first occurence is considered.
```
Florent Kermarrec [Mon, 17 Dec 2018 15:00:44 +0000 (16:00 +0100)]
bios/sdram: reduce scans verbosity on ultrascale
Florent Kermarrec [Mon, 17 Dec 2018 10:43:21 +0000 (11:43 +0100)]
bios/sdram: use ddrphy_half_sys8x_taps_read() for KUSDDRPHY
Tim Ansell [Sun, 16 Dec 2018 22:42:36 +0000 (14:42 -0800)]
Merge pull request #138 from mithro/mainram-hack
Hack to fix #136.
Tim 'mithro' Ansell [Sun, 16 Dec 2018 22:40:10 +0000 (14:40 -0800)]
Hack to fix #136.
Tim Ansell [Sun, 16 Dec 2018 22:04:19 +0000 (14:04 -0800)]
Merge pull request #135 from mithro/icestorm-ice40up5k
Add uwg30 package and up3k part.
Tim 'mithro' Ansell [Sat, 15 Dec 2018 23:47:47 +0000 (15:47 -0800)]
Add uwg30 package and up3k part.
Florent Kermarrec [Wed, 12 Dec 2018 09:01:49 +0000 (10:01 +0100)]
soc/cores/cpu/vexriscv: add add_debug method for debug variants
Florent Kermarrec [Wed, 12 Dec 2018 08:39:30 +0000 (09:39 +0100)]
soc/cores/cpu/vexriscv: add support for the new variants.
Florent Kermarrec [Wed, 12 Dec 2018 08:38:53 +0000 (09:38 +0100)]
soc/cores/cpu/vexriscv: update submodule
Florent Kermarrec [Wed, 12 Dec 2018 08:38:10 +0000 (09:38 +0100)]
soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v)
Florent Kermarrec [Wed, 12 Dec 2018 08:37:24 +0000 (09:37 +0100)]
build/sim/verilator: add support for plaform.sources, some cleanup
Florent Kermarrec [Wed, 12 Dec 2018 08:34:43 +0000 (09:34 +0100)]
build/microsemi/libero_soc: fix typos
Florent Kermarrec [Sun, 9 Dec 2018 08:46:10 +0000 (09:46 +0100)]
gen/sim/core: add args support on Display
Florent Kermarrec [Sun, 9 Dec 2018 08:45:17 +0000 (09:45 +0100)]
gen/fhdl: add simulation Display, Finish support.
In some simulation cases, it's easier to add debug traces directly in the code
than in the verilog/Migen testbench. This adds support for verilog $display in
Migen code.
Being able to terminate a simulation from the code is also useful, this also
add support for verilog $finish.
Florent Kermarrec [Sun, 9 Dec 2018 07:10:50 +0000 (08:10 +0100)]
build/sim: add coverage parameter to enable code coverage
Florent Kermarrec [Sat, 8 Dec 2018 00:24:08 +0000 (01:24 +0100)]
soc/interconnect/stream: add support for buffered async fifo
Florent Kermarrec [Tue, 4 Dec 2018 20:06:51 +0000 (21:06 +0100)]
gen: integrate migen changes
Florent Kermarrec [Fri, 30 Nov 2018 22:12:30 +0000 (23:12 +0100)]
soc/interconnect/stream/gearbox: remove bit reversing by changing words order
Florent Kermarrec [Tue, 27 Nov 2018 16:45:07 +0000 (17:45 +0100)]
Merge branch 'master' of github.com/enjoy-digital/litex
Florent Kermarrec [Tue, 27 Nov 2018 16:42:39 +0000 (17:42 +0100)]
build/xilinx/vivado: disable xpm by default (can be enabled by passing enable_xpm=True to build).
Old version of Vivado don't have XPM support and enable it break the build.
Enabling XPM is only useful in some cases, we can do it manually.
enjoy-digital [Tue, 27 Nov 2018 16:35:03 +0000 (17:35 +0100)]
Merge pull request #130 from jfng/master
litex_sim: add --trace argument
Florent Kermarrec [Tue, 27 Nov 2018 16:31:53 +0000 (17:31 +0100)]
targets/ulx3s, versa_ecp5: use ECP5PLL
Jean-François Nguyen [Tue, 27 Nov 2018 16:26:32 +0000 (17:26 +0100)]
litex_sim: add --trace argument
Florent Kermarrec [Tue, 27 Nov 2018 16:24:22 +0000 (17:24 +0100)]
cores/clock: test and fix ECP5PLL, phase still not implemented.
Florent Kermarrec [Tue, 27 Nov 2018 13:15:35 +0000 (14:15 +0100)]
boards/platforms/ulx3s: add gpios 0-3
Florent Kermarrec [Mon, 26 Nov 2018 17:37:45 +0000 (18:37 +0100)]
bios/sdram: flush l2 cache only when present
Florent Kermarrec [Mon, 26 Nov 2018 14:21:00 +0000 (15:21 +0100)]
bios: allow testing main_ram at init when using an external controller
Florent Kermarrec [Mon, 26 Nov 2018 10:35:06 +0000 (11:35 +0100)]
build/microsemi/libero_soc: small cleanup
enjoy-digital [Mon, 26 Nov 2018 08:48:10 +0000 (09:48 +0100)]
Merge pull request #128 from mithro/small-fix
Two small fixes
Tim 'mithro' Ansell [Sun, 25 Nov 2018 20:57:11 +0000 (12:57 -0800)]
stream.Endpoint: Pass extra arguments to superclass.
Tim 'mithro' Ansell [Sun, 25 Nov 2018 20:56:37 +0000 (12:56 -0800)]
wishbone.SRAM: Support non-32bit wishbone widths.
Florent Kermarrec [Fri, 23 Nov 2018 23:47:38 +0000 (00:47 +0100)]
cores/clock: add ECP5PLL
Florent Kermarrec [Fri, 23 Nov 2018 17:34:24 +0000 (18:34 +0100)]
soc/interconnect/stream/gearbox: inverse bit order
Florent Kermarrec [Fri, 23 Nov 2018 17:33:53 +0000 (18:33 +0100)]
soc/cores/spi_flash: add missing endianness parameter
Florent Kermarrec [Fri, 23 Nov 2018 11:47:45 +0000 (12:47 +0100)]
platforms/avalanche: add IOStandard on ddram pins
Florent Kermarrec [Fri, 23 Nov 2018 08:30:13 +0000 (09:30 +0100)]
build/microsemi/libero_soc: associate timings constraints with synthesis/place&route/timing verification
Florent Kermarrec [Fri, 23 Nov 2018 08:04:42 +0000 (09:04 +0100)]
build/microsemi/libero_soc: add additional_timing_constraints
Florent Kermarrec [Fri, 23 Nov 2018 07:26:31 +0000 (08:26 +0100)]
build/microsemi/libero_soc: use die/package/speed from platform.device and add tcl_name helper
Florent Kermarrec [Fri, 23 Nov 2018 07:24:29 +0000 (08:24 +0100)]
platforms/avalanche: add package/speed to platform.device
Florent Kermarrec [Fri, 23 Nov 2018 07:11:57 +0000 (08:11 +0100)]
build/microsemi/libero_soc: remove previous impl directory if exists
Florent Kermarrec [Fri, 23 Nov 2018 07:03:55 +0000 (08:03 +0100)]
build/microsemi/libero_soc: give better names to pdc files: io/fp
Florent Kermarrec [Thu, 22 Nov 2018 17:40:19 +0000 (18:40 +0100)]
build/microsemi/libero_soc: add additional_constraints
Florent Kermarrec [Thu, 22 Nov 2018 17:13:33 +0000 (18:13 +0100)]
platforms/avalanche: fix ddram dq7
Florent Kermarrec [Thu, 22 Nov 2018 16:37:03 +0000 (17:37 +0100)]
build/microsemi/libero_soc: add {} around port name.
Florent Kermarrec [Thu, 22 Nov 2018 16:33:46 +0000 (17:33 +0100)]
utils/litex_read_verilog: fix generated indent on instance
Florent Kermarrec [Wed, 21 Nov 2018 07:39:52 +0000 (08:39 +0100)]
soc/integration/soc_core: add csr_map_update function
Tim Ansell [Wed, 21 Nov 2018 05:15:50 +0000 (21:15 -0800)]
Merge pull request #127 from cr1901/picorv32-data
libbase/crt0-picorv32: Add support for .data sections.
William D. Jones [Wed, 21 Nov 2018 05:13:13 +0000 (00:13 -0500)]
libbase/crt0-picorv32: Add support for .data sections.
Florent Kermarrec [Tue, 20 Nov 2018 17:49:01 +0000 (18:49 +0100)]
build/sim/verilator: add trace parameter to enable tracer
Florent Kermarrec [Tue, 20 Nov 2018 16:45:11 +0000 (17:45 +0100)]
soc_core: convert cpu_type="None" string to None
Florent Kermarrec [Mon, 19 Nov 2018 14:54:33 +0000 (15:54 +0100)]
build/microsemi/libero_soc: only associate timings constraint to timing check (otherwise we loose io constraints...), use default settings for place & route
Florent Kermarrec [Mon, 19 Nov 2018 12:15:34 +0000 (13:15 +0100)]
build/microsemi/common: add async reset synchronizer (using DFN1P0)
Florent Kermarrec [Mon, 19 Nov 2018 11:50:07 +0000 (12:50 +0100)]
build/microsemi/libero_soc: pass timing constraints to synthesis, place & route and timing verification tools