Ali Saidi [Tue, 5 Jun 2012 14:36:59 +0000 (10:36 -0400)]
cpt: update some comments in the checkpoint migration script
Ali Saidi [Tue, 5 Jun 2012 05:23:16 +0000 (01:23 -0400)]
all: Update stats for memory per master and total fix.
William Wang [Tue, 5 Jun 2012 05:23:11 +0000 (01:23 -0400)]
stats: when applying an operation to two vectors sum the components first.
Previously writing X/Y in a formula would result in:
x[0]/y[0] + x[1]/y[1]
In reality you want:
(x[0] +x[1])/(y[0] + y[1])
Dam Sunwoo [Tue, 5 Jun 2012 05:23:11 +0000 (01:23 -0400)]
Mem: add per-master stats to physmem
Added per-master stats (similar to cache stats) to physmem.
Geoffrey Blake [Tue, 5 Jun 2012 05:23:11 +0000 (01:23 -0400)]
ARM: Add PCIe support to VExpress_EMM model and remove deprecated ELT
Chander Sudanthi [Tue, 5 Jun 2012 05:23:10 +0000 (01:23 -0400)]
ARM: removed extra white space
Extra white space fixes in miscregs.hh
Chander Sudanthi [Tue, 5 Jun 2012 05:23:10 +0000 (01:23 -0400)]
ARM: Fix MPIDR and MIDR register implementation.
This change allows designating a system as MP capable or not as some
bootloaders/kernels care that it's set right. You can have a single
processor MP capable system, but you can't have a multi-processor
UP only system. This change also fixes the initialization of the MIDR
register.
Chander Sudanthi [Tue, 5 Jun 2012 05:23:10 +0000 (01:23 -0400)]
ARM: PS2 encoding fix
Fixed Disable encoding and added SetDefaults.
See http://wiki.osdev.org/Mouse_Input for encodings.
Ali Saidi [Tue, 5 Jun 2012 05:23:10 +0000 (01:23 -0400)]
sim: Provide a framework for detecting out of data checkpoints and migrating them.
Ali Saidi [Tue, 5 Jun 2012 05:23:10 +0000 (01:23 -0400)]
stats: Add stats unittest for total calculations.
Ali Saidi [Tue, 5 Jun 2012 05:23:09 +0000 (01:23 -0400)]
O3: Clean up the O3 structures and try to pack them a bit better.
DynInst is extremely large the hope is that this re-organization will put the
most used members close to each other.
Ali Saidi [Tue, 5 Jun 2012 05:23:09 +0000 (01:23 -0400)]
sim: Add support for tcmalloc if it's installed and available.
This package is available in Ubuntu, Debian, and Redhat as google-perftools.
With multiple tests on a single machine I've seen a little over 10% performance
gain with tcmalloc.
Ali Saidi [Tue, 5 Jun 2012 05:23:08 +0000 (01:23 -0400)]
sim: Remove FastAlloc
While FastAlloc provides a small performance increase (~1.5%) over regular malloc it isn't thread safe.
After removing FastAlloc and using tcmalloc I've seen a performance increase of 12% over libc malloc
when running twolf for ARM.
Ali Saidi [Tue, 5 Jun 2012 05:23:08 +0000 (01:23 -0400)]
ARM: Fix over-eager assert in gic.
Mitchell Hayenga [Tue, 5 Jun 2012 05:23:08 +0000 (01:23 -0400)]
stats: Provide a mechanism to get a callback when stats are dumped.
This mechanism is useful for dumping output that is correlated with stats
dumping, but isn't tracked by the gem5 statistics.
Ali Saidi [Tue, 5 Jun 2012 05:23:08 +0000 (01:23 -0400)]
ARM: Fix compilation on ARM after Gabe's change.
Gabe Black [Mon, 4 Jun 2012 17:57:23 +0000 (10:57 -0700)]
ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.
This eliminates a use of the ExtMachInst type outside of the ISAs.
Gabe Black [Mon, 4 Jun 2012 17:43:11 +0000 (10:43 -0700)]
X86: Update stats for the CPUID change.
Gabe Black [Mon, 4 Jun 2012 17:43:09 +0000 (10:43 -0700)]
X86: Ensure that the CPUID instruction always writes its outputs.
The CPUID instruction was implemented so that it would only write its results
if the instruction was successful. This works fine on the simple CPU where
unwritten registers retain their old values, but on a CPU like O3 with
renaming this is broken. The instruction needs to write the old values back
into the registers explicitly if they aren't being changed.
Gabe Black [Mon, 4 Jun 2012 17:43:08 +0000 (10:43 -0700)]
X86: Ensure that the decoder's internal ExtMachInst is completely initialized.
There are some bits of some fields of the ExtMachInst which are not actually
used for anything but are included in the hash of an ExtMachInst for
simplicity and efficiency. This change makes sure the decoder's internal
working ExtMachInst is completely initialized, even these unused bits, so that
there isn't any nondeterministic behavior, no valgrind messages about
uninitialized variables, and no potential false misses/redundant entries in
the decode cache.
Andreas Hansson [Thu, 31 May 2012 17:30:04 +0000 (13:30 -0400)]
Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
Andreas Hansson [Wed, 9 May 2012 18:52:14 +0000 (11:52 -0700)]
Stats: Fix stats to match output after changeset
8800b05e1cb3
This patch updates the stats for parser to be aligned with the most
up-to-date behaviour. Somehow the wrong results got committed as part
of
8800b05e1cb3 (see details below) when fixing the no_value -> nan
stats.
changeset: 8983:
8800b05e1cb3
user: Nathan Binkert <nate@binkert.org>
summary: stats: update stats for no_value -> nan
Andreas Hansson [Wed, 30 May 2012 09:31:48 +0000 (05:31 -0400)]
gcc: Small fixes to compile with gcc 4.7
This patch makes two very minor changes to please gcc 4.7. The
CopyData function no longer exists and this has been replaced. For
some reason previous versions of gcc did not complain on the const
char casting not having an implementation, but this is now addressed.
Andreas Hansson [Wed, 30 May 2012 09:31:11 +0000 (05:31 -0400)]
Bus: Remove redundant packet parameter from isOccupied
This patch merely remove the Packet* from the isOccupied member
function. Historically this was used to check if the packet was an
express snoop, but this is now done outside this function (where
relevant).
Andreas Hansson [Wed, 30 May 2012 09:30:24 +0000 (05:30 -0400)]
Bus: Turn the PortId into a transport function parameter
The main aim of this patch is to arrive at a suitable port interface
for vector ports, including both the packet and the port id. This
patch changes the bus transport functions
(recvFunctional/Atomic/Timing) to require a PortId parameter
indicating the source port. Previously this information was passed by
setting the source field of the packet, and this is only required in
the case of a timing request.
With this patch, the use of the source and destination field is also
more restrictive, as they are only needed for timing accesses. The
modifications to these fields for atomic snoops is now removed
entirely, also making minor modifications to the cache.
Andreas Hansson [Wed, 30 May 2012 09:29:42 +0000 (05:29 -0400)]
Packet: Unify the use of PortID in packet and port
This patch removes the Packet::NodeID typedef and unifies it with the
Port::PortId. The src and dest fields in the packet are used to hold a
port id (e.g. in the bus), and thus the two should actually be the
same.
The typedef PortID is now global (in base/types.hh) and aligned with
the ThreadID in terms of capitalisation and naming of the
InvalidPortID constant.
Before this patch, two flags were used for valid destination and
source, rather than relying on a named value (InvalidPortID), and
this is now redundant, as the src and dest field themselves are
sufficient to tell whether the current value is a valid port
identifier or not. Consequently, the VALID_SRC and VALID_DST are
removed.
As part of the cleaning up, a number of int parameters and local
variables are updated to use PortID.
Note that Ruby still has its own NodeID typedef. Furthermore, the
MemObject getMaster/SlavePort still has an int idx parameter with a
default value of -1 which should eventually change to PortID idx =
InvalidPortID.
Andreas Hansson [Wed, 30 May 2012 09:29:07 +0000 (05:29 -0400)]
Packet: Updated comments for src and dest fields
This patch updates the comments for the src and dest fields to reflect
their actual use. Due to a number of patches (e.g. removing the
Broadcast flag), the old comments are no longer indicative of the
current usage.
Andreas Hansson [Wed, 30 May 2012 09:28:06 +0000 (05:28 -0400)]
Bridge: Split deferred request, response and sender state
This patch splits the PacketBuffer class into a RequestState and a
DeferredRequest and DeferredResponse. Only the requests need a
SenderState, and the deferred requests and responses only need an
associated point in time for the request and the response queue.
Besides the cleaning up, the goal is to simplify the transition to a
new port handshake, and with these changes, the two packet queues are
starting to look very similar to the generic packet queue, but
currently they do a few unique things relating to the NACK and
counting of requests/responses that the packet queue cannot be
conveniently used. This will be addressed in a later patch.
Gabe Black [Tue, 29 May 2012 04:56:23 +0000 (21:56 -0700)]
X86: Use the HandyM5Reg to avoid a register read and some logic in the TLB.
Gabe Black [Mon, 28 May 2012 02:01:09 +0000 (19:01 -0700)]
X86: Add a 32 bit hello world test binary.
Gabe Black [Mon, 28 May 2012 02:01:08 +0000 (19:01 -0700)]
X86: Move the GDT down to where it can be accessed in 32 bit mode.
The GDT can be accessed by user level software running in compatibility mode
by moving segment selectors into segment registers. The GDT needs to be set up
at an address accessible in this mode.
Gabe Black [Mon, 28 May 2012 02:01:04 +0000 (19:01 -0700)]
X86: Truncate addresses to 32 bits except in 64 bit mode, not long mode.
A small change was added a while ago to keep addresses from overflowing 32
bits when larger addresses shouldn't be accessible to software. That change
truncated when not in long mode, but really it should have truncated when not
in 64 bit mode. The difference is whether compatibility mode is included, a
mode that's supposed to act like a legacy 32 bit mode.
Gabe Black [Sat, 26 May 2012 20:45:12 +0000 (13:45 -0700)]
ISA,CPU: Generalize and split out the components of the decode cache.
This will allow it to be specialized by the ISAs. The existing caching scheme
is provided by the BasicDecodeCache in the GenericISA namespace and is built
from the generalized components.
--HG--
rename : src/cpu/decode_cache.cc => src/arch/generic/decode_cache.cc
Gabe Black [Sat, 26 May 2012 20:44:46 +0000 (13:44 -0700)]
CPU: Merge the predecoder and decoder.
These classes are always used together, and merging them will give the ISAs
more flexibility in how they cache things and manage the process.
--HG--
rename : src/arch/x86/predecoder_tables.cc => src/arch/x86/decoder_tables.cc
Gabe Black [Fri, 25 May 2012 07:55:24 +0000 (00:55 -0700)]
ISA: Make the decode function part of the ISA's decoder.
Gabe Black [Fri, 25 May 2012 07:54:39 +0000 (00:54 -0700)]
CPU: Simplify the implementation of the decode cache.
Also reorganize it to make it more amenable to being rearranged later.
Gabe Black [Fri, 25 May 2012 07:53:37 +0000 (00:53 -0700)]
Decode: Make the Decoder class defined per ISA.
--HG--
rename : src/cpu/decode.cc => src/arch/generic/decoder.cc
rename : src/cpu/decode.hh => src/arch/generic/decoder.hh
Andreas Hansson [Thu, 24 May 2012 08:09:19 +0000 (04:09 -0400)]
Cache: Remove dangling doWriteback declaration
This patch removes the declaration of doWriteback as there is no
implementation for this member function.
Andreas Hansson [Wed, 23 May 2012 13:18:04 +0000 (09:18 -0400)]
Packet: Cleaning up packet command and attribute
This patch removes unused commands and attributes from the packet to
avoid any confusion. It is part of an effort to clear up how and where
different commands and attributes are used.
Andreas Hansson [Wed, 23 May 2012 13:16:39 +0000 (09:16 -0400)]
Config: Use the attribute naming and include ports in JSON
This patch changes the organisation of the JSON output slightly to
make it easier to traverse and use the files. Most importantly, the
hierarchical dictionaries now use keys that correspond to the
attribute names also in the case of VectorParams (used to be
e.f. "cpu0 cpu1"). It also adds the name and the path to each
SimObject directory entry. Before this patch, to get cpu0, you would
have to query dict['system']['cpu0 cpu1'][0] and this could be a dict
with 'cpu0' : { cpu parameters }. Now you use dict['system']['cpu'][0]
and get { cpu parameters } (where one is "name" : "cpu0").
Additionally this patch includes more verbose information about the
ports, specifying their role, and using a JSON array rather than a
concatenated string for the peer.
Andreas Hansson [Wed, 23 May 2012 13:15:45 +0000 (09:15 -0400)]
DMA: Split the DMA device and IO device into seperate files
This patch moves the DMA device to its own set of files, splitting it
from the IO device. There are no behavioural changes associated with
this patch.
The patch also grabs the opportunity to do some very minor tidying up,
including some white space removal and pruning some redundant
parameters.
Besides the immediate benefits of the separation-of-concerns, this
patch also makes upcoming changes more streamlined as it split the
devices that are only slaves and the DMA device that also acts as a
master.
--HG--
rename : src/dev/io_device.cc => src/dev/dma_device.cc
rename : src/dev/io_device.hh => src/dev/dma_device.hh
Andreas Hansson [Wed, 23 May 2012 13:14:12 +0000 (09:14 -0400)]
MEM: Add a snooping DMA port subclass for table walker
This patch makes the (device) DmaPort non-snooping and removes the
recvSnoop constructor parameter and instead introduces a
SnoopingDmaPort subclass for the ARM table walker.
Functionality is unchanged, as are the stats, and the patch merely
clarifies that the normal DMA ports are not snooping (although they
may issue requests that are snooped by others, as done with PCI, PCIe,
AMBA4 ACE etc).
Currently this port is declared in the ARM table walker as it is not
used anywhere else. If other ports were to have similar behaviour it
could be moved in a future patch.
Andreas Hansson [Wed, 23 May 2012 13:01:56 +0000 (09:01 -0400)]
Config: Exit with fatal if a port is already connected
This patch turns the existing warning into a fatal, as there should
never be any cases where a (non-vector) port is assigned to and then
later connected to something else. If this behaviour is allowed, as it
used to be, there are cases where the wrong number of C++ ports are
created when instantiating objects with VectorPorts (obviously that
could be fixed, but the better approach is to simply not allow it).
Nilay Vaish [Tue, 22 May 2012 16:38:04 +0000 (11:38 -0500)]
X86 Regression: update stats due to cc register split
Nilay Vaish [Tue, 22 May 2012 16:35:58 +0000 (11:35 -0500)]
Ruby: Remove the unused src/mem/ruby/common/Driver.* files.
Nilay Vaish [Tue, 22 May 2012 16:32:57 +0000 (11:32 -0500)]
Ruby Sequencer: Schedule deadlock check event at correct time
The scheduling of the deadlock check event was being done incorrectly as the
clock was not being multiplied, so as to convert the time into ticks. This
patch removes that bug.
Nilay Vaish [Tue, 22 May 2012 16:29:53 +0000 (11:29 -0500)]
X86: Split Condition Code register
This patch moves the ECF and EZF bits to individual registers (ecfBit and
ezfBit) and the CF and OF bits to cfofFlag registers. This is being done
so as to lower the read after write dependencies on the the condition code
register. Ultimately we will have the following registers [ZAPS], [OF],
[CF], [ECF], [EZF] and [DF]. Note that this is only one part of the
solution for lowering the dependencies. The other part will check whether
or not the condition code register needs to be actually read. This would
be done through a separate patch.
Marc Orr [Sat, 19 May 2012 11:32:25 +0000 (04:32 -0700)]
x86 ISA: Implement the sse3 haddps instruction.
Shuffle the 32 bit values into position, and then add in parallel.
Gabe Black [Sat, 19 May 2012 11:13:47 +0000 (04:13 -0700)]
Syscalls: warn when the length argument to mmap is excessive.
If the length argument to mmap is larger than the arbitrary but reasonable
limit of 4GB, there's a good chance that the value is nonsense and not
intentional. Rather than attempting to satisfy the mmap anyway, this change
makes gem5 warn to make it more apparent what's going wrong.
Lena Olson [Tue, 15 May 2012 01:31:33 +0000 (20:31 -0500)]
Mem: Fix size check when allocating physical memory
Andreas Hansson [Wed, 16 May 2012 16:37:08 +0000 (12:37 -0400)]
Config: Fix a typo in the se.py script for setting fastmem
This patch changes a hardcoded index 0 to the appropriate CPU index so
that fastmem is set correctly for all the CPUs in the system.
Ali Saidi [Thu, 10 May 2012 23:04:29 +0000 (18:04 -0500)]
ARM: update stats for clock frequency fix.
Koan-Sin Tan [Thu, 10 May 2012 23:04:28 +0000 (18:04 -0500)]
ARM: fix the calculation of the values in the RV clocks
This clock is used by the linux scheduler.
Ali Saidi [Thu, 10 May 2012 23:04:28 +0000 (18:04 -0500)]
stats: fix compilation of unit test.
Ali Saidi [Thu, 10 May 2012 23:04:28 +0000 (18:04 -0500)]
stats: fix bug in assert for 2d vector
Chander Sudanthi [Thu, 10 May 2012 23:04:28 +0000 (18:04 -0500)]
ARM: pl011 raw interrupt fix
Raw interrupt was not being set when interrupt was disabled.
This patch sets the raw interrupt regardless of the mask.
Chander Sudanthi [Thu, 10 May 2012 23:04:28 +0000 (18:04 -0500)]
ARM: EMM board address range fix
0x40000000 is reservered for external AXI addresses. This address
range is not used currently. Removed the range from the bridge.
Uri Wiener [Thu, 10 May 2012 23:04:27 +0000 (18:04 -0500)]
DOT: improved dot-based system visualization
Revised system visualization to reflect structure and memory hierarchy.
Improved visualization: less congested and cluttered; more colorful.
Nodes reflect components; directed edges reflect dirctional relation, from
a master port to a slave port. Requires pydot.
Uri Wiener [Thu, 10 May 2012 23:04:27 +0000 (18:04 -0500)]
DOT: fixed broken code for visualizing configuration using dot
Fixed broken code which visualizes the system configuration by generating a
tree from each component's children, starting from root.
Requires DOT (hence pydot).
Dam Sunwoo [Thu, 10 May 2012 23:04:27 +0000 (18:04 -0500)]
ARM: guard masked symbol tables by default
Symbol tables masked with the loadAddrMask create redundant entries
that could conflict with kernel function events that rely on the
original addresses. This patch guards the creation of those masked
symbol tables by default, with an option to enable them when needed
(for early-stage kernel debugging, etc.)
Ali Saidi [Thu, 10 May 2012 23:04:27 +0000 (18:04 -0500)]
mem: fix bug with CopyStringOut and null string termination.
Ali Saidi [Thu, 10 May 2012 23:04:27 +0000 (18:04 -0500)]
Cache: restructure code that actually isn't a loop
Ali Saidi [Thu, 10 May 2012 23:04:27 +0000 (18:04 -0500)]
dev: use correct delete operation in SimpleDisk
Ali Saidi [Thu, 10 May 2012 23:04:27 +0000 (18:04 -0500)]
ARM: Fix incorrect use of not operators in arm devices
Ali Saidi [Thu, 10 May 2012 23:04:27 +0000 (18:04 -0500)]
gem5: assert before indexing intro arrays to verify bounds
Ali Saidi [Thu, 10 May 2012 23:04:27 +0000 (18:04 -0500)]
gem5: fix some iterator use and erase bugs
Ali Saidi [Thu, 10 May 2012 23:04:27 +0000 (18:04 -0500)]
gem5: fix a number of use after free issues
Ali Saidi [Thu, 10 May 2012 23:04:27 +0000 (18:04 -0500)]
base: fix a invalid ?: operator
Ali Saidi [Thu, 10 May 2012 23:04:26 +0000 (18:04 -0500)]
gem5: Fix a number of incorrect case statements
Ali Saidi [Thu, 10 May 2012 23:04:26 +0000 (18:04 -0500)]
ARM: Update m5op assembly for thumb compilation.
Ali Saidi [Thu, 10 May 2012 23:04:26 +0000 (18:04 -0500)]
stats: track if the stats have been enabled and prevent requesting master id
Track the point in the initialization where statistics have been registered.
After this point registering new masterIds can no longer work as some
SimObjects may have sized stats vectors based on the previous value. If someone
tries to register a masterId after this point the simulator executes fatal().
Ali Saidi [Thu, 10 May 2012 23:04:26 +0000 (18:04 -0500)]
Cache: Panic if you attempt to create a checkpoint with a cache in the system
Pritha Ghoshal [Thu, 10 May 2012 23:04:26 +0000 (18:04 -0500)]
IGbE: Fix writeback conditions for i8254x GbE in updated data sheet.
An older revision of the data sheet specified that txdctl.gran was 1 the granularity was
based on cache block and gran being 0 is based on descriptor count. The newer version of
the data sheet reverses this errata
Nathan Binkert [Wed, 9 May 2012 18:52:14 +0000 (11:52 -0700)]
stats: update stats for no_value -> nan
Lots of accumulated older changes too.
Nathan Binkert [Wed, 9 May 2012 18:51:42 +0000 (11:51 -0700)]
stats: use nan instead of no_value
Andreas Hansson [Wed, 9 May 2012 08:37:45 +0000 (04:37 -0400)]
MEM: Add the communication monitor
This patch adds a communication monitor MemObject that can be inserted
between a master and slave port to provide a range of statistics about
the communication passing through it. The communication monitor is
non-invasive and does not change any properties or timing of the
packets, with the exception of adding a sender state to be able to
track latency. The statistics are only collected in timing mode (not
atomic) to avoid slowing down any fast forwarding.
An example of the statistics captured by the monitor are: read/write
burst lengths, bandwidth, request-response latency, outstanding
transactions, inter transaction time, transaction count, and address
distribution. The monitor can be used in combination with periodic
resetting and dumping of stats (through schedStatEvent) to study the
behaviour over time.
In future patches, a selection of convenience scripts will be added to
aid in visualising the statistics collected by the monitor.
Steve Reinhardt [Tue, 8 May 2012 14:49:57 +0000 (07:49 -0700)]
scons: allow override of SWIG binary on command line
Andreas Hansson [Tue, 8 May 2012 09:15:52 +0000 (05:15 -0400)]
MEM: Do not forward uncacheable to bus snoopers
This patch adds a guarding if-statement to avoid forwarding
uncacheable requests (or rather their corresponding request packets)
to bus snoopers. These packets should never have any effect on the
caches, and thus there is no need to forward them to the snoopers.
Andreas Hansson [Fri, 4 May 2012 07:30:02 +0000 (03:30 -0400)]
Ruby: Ensure snoop requests are sent using sendTimingSnoopReq
This patch fixes a bug that caused snoop requests to be placed in a
packet queue. Instead, the packet is now sent immediately using
sendTimingSnoopReq, thus bypassing the packet queue and any normal
responses waiting to be sent.
Nilay Vaish [Fri, 4 May 2012 04:18:13 +0000 (23:18 -0500)]
Regression: Move x86 fs ruby simulation from quick to long
--HG--
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal
Jayneel Gandhi [Thu, 3 May 2012 10:17:29 +0000 (05:17 -0500)]
Config: Fix help msg for option --mem-size
Andreas Hansson [Tue, 1 May 2012 17:40:42 +0000 (13:40 -0400)]
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
Nilay Vaish [Mon, 30 Apr 2012 08:47:22 +0000 (03:47 -0500)]
Regression: Stats update for X86 Ruby FS test
The kernel originally used to generate the stats is different from the one
at use on zizzer. This patch updates the stats with the correct kernel in
use.
Gabe Black [Sun, 29 Apr 2012 09:26:34 +0000 (02:26 -0700)]
X86: Fix the IMUL_R_P_I macroop.
The disp displacement was left off the load microop so the wrong value was
used.
Vince Weaver [Sun, 29 Apr 2012 07:31:03 +0000 (00:31 -0700)]
X86: Fix up the open system call's flags.
Vince Weaver [Sun, 29 Apr 2012 07:30:56 +0000 (00:30 -0700)]
X86: Make gem5 ignore a bunch of syscalls.
Nilay Vaish [Sat, 28 Apr 2012 21:57:31 +0000 (16:57 -0500)]
Garnet: Correct computation of link utilization
The computation for link utilization was incorrect for the flexible network.
The utilization was being divided twice by the total time.
Nilay Vaish [Fri, 27 Apr 2012 01:28:45 +0000 (20:28 -0500)]
util/regress: Add the missing comma in the list of builds
Nilay Vaish [Thu, 26 Apr 2012 03:43:36 +0000 (22:43 -0500)]
Regression: Add a test for x86 timing full system ruby simulation
Nilay Vaish [Wed, 25 Apr 2012 22:52:03 +0000 (17:52 -0500)]
Ruby: Remove extra statements from Sequencer
Andreas Hansson [Wed, 25 Apr 2012 14:45:23 +0000 (10:45 -0400)]
MEM: Use base class Master/SlavePort pointers in the bus
This patch makes some rather trivial simplifications to the bus in
that it changes the use of BusMasterPort and BusSlavePort pointers to
simply use MasterPort and SlavePort (iterators are also updated
accordingly).
This change is a step towards a future patch that introduces a
separation of the interface and the structural port itself.
Andreas Hansson [Wed, 25 Apr 2012 14:41:23 +0000 (10:41 -0400)]
MEM: Add the PortId type and a corresponding id field to Port
This patch introduces the PortId type, moves the definition of
INVALID_PORT_ID to the Port class, and also gives every port an id to
reflect the fact that each element in a vector port has an
identifier/index.
Previously the bus and Ruby testers (and potentially other users of
the vector ports) added the id field in their port subclasses, and now
this functionality is always present as it is moved to the base class.
Andreas Hansson [Wed, 25 Apr 2012 12:57:18 +0000 (08:57 -0400)]
clang/gcc: Use STL hash function for int64_t and uint64_t
This patch changes the guards for the definition of hash functions to
also exclude the int64_t and uint64_t hash functions in the case we
are using the c++0x STL <unordered_map> (and <hash>) or the TR1
version of the same header. Previously the guard only covered the hash
function for strings, but it seems there is also no need to define a
hash for the 64-bit integer types, and this has caused problems with
builds on 32-bit Ubuntu.
Gabe Black [Tue, 24 Apr 2012 07:48:57 +0000 (00:48 -0700)]
X86: Update stats for the slightly changed TLB behavior.
Gabe Black [Tue, 24 Apr 2012 07:48:41 +0000 (00:48 -0700)]
X86: Clear out duplicate TLB entries when adding a new one.
It's possible for two page table walks to overlap which will go in the same
place in the TLB's trie. They would land on top of each other, so this change
adds some code which detects if an address already matches an entry and if so
throws away the new one.
Gabe Black [Mon, 23 Apr 2012 19:00:41 +0000 (12:00 -0700)]
ISA: Put parser generated files in a "generated" directory.
This is to avoid collision with non-generated files.
Steve Reinhardt [Mon, 23 Apr 2012 16:25:16 +0000 (09:25 -0700)]
scons: update minimum SWIG version to 1.3.34
We should try to keep this synced with the wiki
(which I also just updated, but which was
previously inconsistent).
Gabe Black [Sun, 22 Apr 2012 12:20:44 +0000 (05:20 -0700)]
base: Include cassert in trie.hh.
trie.hh uses assert, but it wasn't explicitly including cassert.
Gabe Black [Sat, 21 Apr 2012 22:00:23 +0000 (15:00 -0700)]
X86: Report an error if there's no kernel object, don't blindly use it.
This way the user gets a nice message instead of a less nice segfault.
Jayneel Gandhi [Tue, 17 Apr 2012 21:12:41 +0000 (16:12 -0500)]
SE Config: Changed se.py to support multithreaded mode
Multithreaded programs did not run by just specifying the binary once on the
command line of SE mode.The default mode is multi-programmed mode. Added
check in SE mode to run multi-threaded programs in case only one program is
specified with multiple CPUS. Default mode is still multi-programmed mode.