[AArch64] PR82964: Fix 128-bit immediate ICEs

This fixes PR82964 which reports ICEs for some CONST_WIDE_INT immediates.
It turns out decimal floating point CONST_DOUBLE get changed into
CONST_WIDE_INT without checking the constraint on the operand, which
results in failures.  Avoid this by only allowing SF/DF/TF mode floating
point constants in aarch64_legitimate_constant_p.  A similar issue can
occur with 128-bit immediates which may be emitted even when disallowed
in aarch64_legitimate_constant_p, and the constraints in movti_aarch64
don't match.  Fix this with a new constraint and allowing valid immediates
in aarch64_legitimate_constant_p.

Rather than allowing all 128-bit immediates and expanding in up to 8
MOV/MOVK instructions, limit them to 4 instructions and use a literal
load for other cases.  Improve a few TImode tests to use a literal and
ensure they are skipped with -fpic.

This fixes all reported failures.

    gcc/
PR target/82964
* config/aarch64/aarch64.md (movti_aarch64): Use Uti constraint.
* config/aarch64/aarch64.c (aarch64_mov128_immediate): New function.
(aarch64_legitimate_constant_p): Just support CONST_DOUBLE
SF/DF/TF mode to avoid creating illegal CONST_WIDE_INT immediates.
* config/aarch64/aarch64-protos.h (aarch64_mov128_immediate):
Add declaration.
* config/aarch64/constraints.md (aarch64_movti_operand):
Limit immediates.
* config/aarch64/predicates.md (Uti): Add new constraint.

    gcc/testsuite/
PR target/79041
PR target/82964
* gcc.target/aarch64/pr79041-2.c: Improve test, disable with fpic.
* gcc.target/aarch64/pr78733.c: Improve test, disable with fpic.

Co-Authored-By: Richard Sandiford <richard.sandiford@linaro.org>
From-SVN: r256800

[arm][testsuite] Fix -march tests in effective target checks auto-generation

There is a typo in the armv8.1-a and armv8.2-a effective target check generators.
They are not actually used anywhere in the testsuite as far as I can tell, but the fix is obvious.

     * lib/target-supports.exp: Fix -march arguments in arm arch effective
     target check autogenerator for armv8.1-a and armv8.2-a.

From-SVN: r256799

vsx.md (define_expand xl_len_r, [...]): Add match_dup argument.

gcc/ChangeLog:

2018-01-17 Carl Love  <cel@us.ibm.com>
* config/rs6000/vsx.md (define_expand xl_len_r,
define_expand stxvl, define_expand *stxvl): Add match_dup argument.
(define_insn): Add, match_dup 1 argument to define_insn stxvll and
lxvll.
(define_expand, define_insn): Move the shift left from the
define_insn to the define_expand for lxvl and stxvl instructions.
* config/rs6000/rs6000-builtin.def (BU_P9V_64BIT_VSX_2): Change LXVL
and XL_LEN_R definitions to PURE.

gcc/testsuite/ChangeLog:

2018-01-17  Carl Love  <cel@us.ibm.com>
* gcc.target/powerpc/builtins-6-p9-runnable.c: Add additional tests.
Add debug print statements.
* gcc.target/powerpc/builtins-5-p9-runnable.c: Add test to do
16 byte vector load followed by a partial vector load.

From-SVN: r256798

i386.c (indirect_thunk_name): Declare regno as unsigned int.

* config/i386/i386.c (indirect_thunk_name): Declare regno
as unsigned int.  Compare regno with INVALID_REGNUM.
(output_indirect_thunk): Ditto.
(output_indirect_thunk_function): Ditto.
(ix86_code_end): Declare regno as unsigned int.  Use INVALID_REGNUM
in the call to output_indirect_thunk_function.

From-SVN: r256797

Fix failure building LLVM with location wrapper nodes (PR c++/83799)

PR c++/83799 reports a failure building LLVM due to a bogus
"no matching function for call to" error at a callsite like this:
  TLI->getTypeLegalizationCost(DL);
where "DL" is from:
  using TargetTransformInfoImplBase::DL;

The root cause is that type_dependent_expression_p on a USING_DECL
should return true when processing a template, but after r256448 the
the argument at the callsite is a location wrapper around the USING_DECL,
and type_dependent_expression_p erroneously returns false for it, as
it is comparing tree codes, and failing a match, then looking at types.

This prevents cp_parser_postfix_expression from using the
"build_min_nt_call_vec" path for handling the call, instead erroneously
handling it via build_new_method_call (which fails for this case).

This patch fixes the problem by stripping any location wrappers before
the various tree code tests in type_dependent_expression_p.   It fixes
the reduced test case, and the full BasicTargetTransformInfo.ii; after
this patch, the assembly generated for that latter case is identical to
that generated before r256448.

gcc/cp/ChangeLog:
PR c++/83799
* pt.c (type_dependent_expression_p): Strip any location wrapper
before testing tree codes.
(selftest::test_type_dependent_expression_p): New function.
(selftest::cp_pt_c_tests): Call it.

gcc/testsuite/ChangeLog:
PR c++/83799
* g++.dg/wrappers/pr83799.C: New test case.

From-SVN: r256796

[C++/83739] bogus error tsubsting range for in generic lambda

https://gcc.gnu.org/ml/gcc-patches/2018-01/msg01554.html
PR c++/83739
* pt.c (tsubst_expr) <case RANGE_FOR_STMT>: Rebuild a range_for if
this not a final instantiation.

PR c++/83739
* g++.dg/cpp1y/pr83739.C: New.

From-SVN: r256795

libgo: update to Go1.10beta2 release

    Reviewed-on: https://go-review.googlesource.com/87897

From-SVN: r256794

overflow8.c: Pass -fno-if-conversion.

* gcc.target/visium/overflow8.c: Pass -fno-if-conversion.
* gcc.target/visium/overflow16.c: Likewise.
* gcc.target/visium/overflow32.c: Likewise.

From-SVN: r256793

* gcc.dg/ipa/inlinehint-4.c: Also pass --param inline-unit-growth=20.

From-SVN: r256787

[arm] Convert gcc.target/arm/stl-cond.c into an RTL test

This is an awkward testsuite failure. The original bug was that we were failing to put out
the conditional code in the conditional form of the STL instruction (oops!).
So we wanted to output STLNE, but instead output STL.
The testacase relies on if-conversion to conditionalise the insn for STL.
However, ever since r251643 the expansion of a non-relaxed atomic store
always includes a compiler barrier. That blocks if-conversion in all cases.

So there's no easy way to get to a conditional STL instruction from a C program.
But we do want to test for the original bug fix that if the RTL insn for STL is conditionalised
it should output the conditional code.

The solution in this patch is to convert the test into an RTL test with the COND_EXEC form
of the STL insn and scan the assembly output there.
This seems to work fine, and gives us an opportunity to create a gcc.dg/rtl/arm directory
in the RTL tests.

This now makes the gcc.target/arm/stl-cond.c disappear (as the test is deleted) and
the new test in gcc.dg/rtl/arm/stl-cond.c passes.

     * gcc.dg/rtl/arm/stl-cond.c: New test.
     * gcc.target/arm/stl-cond.c: Delete.

From-SVN: r256785

[arm] Fix gcc.target/arm/pr40887.c directives

This patch converts gcc.target/arm/pr40887.c to use the proper effective target check and dg-add-options for armv5te
so that we avoid situations where we end up trying to compile the test with a Thumb1 hard-float ABI, which makes the
compiler complain.

This allows the test to pass gracefully for me for my compiler configured with:
--with-cpu=cortex-a15 --with-fpu=neon-vfpv4 --with-float=hard --with-mode=thumb

     * gcc.target/arm/pr40887.c: Add armv5te effective target checks and
     directives.

From-SVN: r256784

re PR tree-optimization/83843 (wrong code at -O2)

PR tree-optimization/83843
* gcc.dg/store_merging_18.c: Don't expect "Merging successful" on arm.
* gcc.dg/store_merging_19.c: New test.

From-SVN: r256783

[arm] Fix gcc.target/arm/xor-and.c

This test is naughty because it doesn't use the proper effective target checks
and add-options mechanisms for setting a Thumb1 target, which leads to Thumb1 hard-float errors
when testing a toolchain configured with --with-cpu=cortex-a15 --with-fpu=neon-vfpv4 --with-float=hard --with-mode=thumb.

This patch fixes that in the obvious way.

* gcc.target/arm/xor-and.c: Fix armv6 effective target checks
and options.

From-SVN: r256782

re PR rtl-optimization/83771 (ICE: verify_flow_info failed (error: non-cold basic block 3 reachable only by paths crossing the cold partition))

PR rtl-optimization/83771
* gcc.dg/pr83771.c: New test.

From-SVN: r256781

re PR tree-optimization/81184 (gcc.dg/pr21643.c and gcc.dg/tree-ssa/phi-opt-11.c fail starting with r249450)

PR tree-optimization/81184
* gcc.dg/pr21643.c: Adjust dg-final line for logical_op_short_circuit
targets.
* gcc.dg/tree-ssa/phi-opt-11.c: Likewise.

From-SVN: r256780

VIEW_CONVERT_EXPR slots for strict-align targets (PR 83884)

This PR is about a case in which we VIEW_CONVERT a variable-sized
unaligned record:

 <record_type 0x7ffff6d92888 check_displace_generation__T245b sizes-gimplified type_7 BLK
    size <var_decl 0x7ffff6846510 D.3499 ...>
    unit-size <var_decl 0x7ffff68465a0 D.3500 ...>
    align:8 ...>

to an aligned 32-bit integer.  The strict-alignment handling of
this case creates an aligned temporary slot, moves the operand
into the slot in the operand's original mode, then accesses the
slot in the more-aligned result mode.

Previously the size of the temporary slot was calculated using:

                  HOST_WIDE_INT temp_size
                    = MAX (int_size_in_bytes (inner_type),
                           (HOST_WIDE_INT) GET_MODE_SIZE (mode));

int_size_in_bytes would return -1 for the variable-length type,
so we'd use the size of the result mode for the slot.  r256152 replaced
int_size_in_bytes with tree_to_poly_uint64, which triggered an ICE.

If op0 has BLKmode we do a block copy of GET_MODE_SIZE (mode) bytes
and then convert the slot to "mode":

                  poly_uint64 mode_size = GET_MODE_SIZE (mode);
                  ...
                  if (GET_MODE (op0) == BLKmode)
                    {
                      rtx size_rtx = gen_int_mode (mode_size, Pmode);
                      emit_block_move (new_with_op0_mode, op0, size_rtx,
                                       (modifier == EXPAND_STACK_PARM
                                        ? BLOCK_OP_CALL_PARM
                                        : BLOCK_OP_NORMAL));
                    }
                  else
                    ...

                  op0 = new_rtx;
                }
            }

          op0 = adjust_address (op0, mode, 0);

so I think in that case just the size of "mode" is enough, even if op0
is a fixed-size type.  For non-BLKmode op0 we first move in op0's mode
and then convert the slot to "mode":

                    emit_move_insn (new_with_op0_mode, op0);

                  op0 = new_rtx;
                }
            }

          op0 = adjust_address (op0, mode, 0);

so I think we want the maximum of the two mode sizes in that case.

2018-01-17  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
PR middle-end/83884
* expr.c (expand_expr_real_1): Use the size of GET_MODE (op0)
rather than the size of inner_type to determine the stack slot size
when handling VIEW_CONVERT_EXPRs on strict-alignment targets.

From-SVN: r256779

* c-c++-common/Wrestrict.c (test_strcpy_range): Revert latest change.

From-SVN: r256778

Re-enabling of RDRND for Silvermont.

2018-01-15  Sebastian Peryt  <sebastian.peryt@intel.com>

gcc/

PR target/83546
* config/i386/i386.c (ix86_option_override_internal): Add PTA_RDRND
to PTA_SILVERMONT.

2018-01-15  Sebastian Peryt  <sebastian.peryt@intel.com>

gcc/testsuite/

PR target/83546
* gcc.target/i386/pr83546.c: New test.

From-SVN: r256777

elf.c (codes): Fix size to be 288.

* elf.c (codes) [GENERATE_FIXED_HUFFMAN_TABLE]: Fix size to be
288.
(main) [GENERATE_FIXED_HUFFMAN_TABLE]: Pass 288 to
elf_zlib_inflate_table.  Generate elf_zlib_default_dist_table.
(elf_zlib_default_table): Update.
(elf_zlib_default_dist_table): New static array.
(elf_zlib_inflate): Use elf_zlib_default_dist_table for dist table
for block type 1.
* ztest.c (struct zlib_test): Add uncompressed_len.
(tests): Initialize uncompressed_len field.  Add new test case.
(test_samples): Use uncompressed_len field.

From-SVN: r256776

config.gcc (powerpc*-linux*-*): Add support for 64-bit little endian Linux systems to optionally enable...

2018-01-16  Michael Meissner  <meissner@linux.vnet.ibm.com>

* config.gcc (powerpc*-linux*-*): Add support for 64-bit little
endian Linux systems to optionally enable multilibs for selecting
the long double type if the user configured an explicit type.
* config/rs6000/rs6000.h (TARGET_IEEEQUAD_MULTILIB): Indicate we
have no long double multilibs if not defined.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Do not
warn if the user used -mabi={ieee,ibm}longdouble and we built
multilibs for long double.
* config/rs6000/linux64.h (MULTILIB_DEFAULTS_IEEE): Define as the
appropriate multilib option.
(MULTILIB_DEFAULTS): Add MULTILIB_DEFAULTS_IEEE to the default
multilib options.
* config/rs6000/t-ldouble-linux64le-ibm: New configuration files
for building long double multilibs.
* config/rs6000/t-ldouble-linux64le-ieee: Likewise.

From-SVN: r256775

config.gcc (hppa*-*-linux*): Change callee copies ABI to caller copies.

* config.gcc (hppa*-*-linux*): Change callee copies ABI to caller
copies.

From-SVN: r256774

pa.h (MALLOC_ABI_ALIGNMENT): Set 32-bit alignment default to 64 bits.

* config/pa.h (MALLOC_ABI_ALIGNMENT): Set 32-bit alignment default to
64 bits.
* config/pa/pa32-linux.h (MALLOC_ABI_ALIGNMENT): Set alignment to
128 bits.

From-SVN: r256773

Daily bump.

From-SVN: r256772

som.h (ASM_DECLARE_FUNCTION_NAME): Cleanup type and mode variables.

* config/pa/som.h (ASM_DECLARE_FUNCTION_NAME): Cleanup type and mode
variables.

From-SVN: r256769

pa.c (pa_function_arg_size): Apply CEIL to GET_MODE_SIZE return value.

* config/pa/pa.c (pa_function_arg_size): Apply CEIL to GET_MODE_SIZE
return value.

From-SVN: r256768

gimple-ssa-warn-restrict.c (builtin_memref::builtin_memref): For an ADDR_EXPR, do not count the offset of a COMPONENT_REF twice.

* gimple-ssa-warn-restrict.c (builtin_memref::builtin_memref): For an
ADDR_EXPR, do not count the offset of a COMPONENT_REF twice.

From-SVN: r256766

PR c++/83714 - ICE checking return in template.

* typeck.c (check_return_expr): Call build_non_dependent_expr.

From-SVN: r256765

Wrestrict.c (test_strcpy_range): Bump string size of one test and add dg-warning for the -Wstringop-overflow warning.

* c-c++-common/Wrestrict.c (test_strcpy_range): Bump string size of one
test and add dg-warning for the -Wstringop-overflow warning.

From-SVN: r256764

Warray-bounds-4.c (test_strcpy_bounds_memarray_range): XFAIL last test on SPARC and Visium.

* c-c++-common/Warray-bounds-4.c (test_strcpy_bounds_memarray_range):
XFAIL last test on SPARC and Visium.

From-SVN: r256763

rs6000-p8swap.c (rs6000_gen_stvx): Generate different rtl trees depending on TARGET_64BIT.

gcc/ChangeLog:

2018-01-16  Kelvin Nilsen  <kelvin@gcc.gnu.org>

* config/rs6000/rs6000-p8swap.c (rs6000_gen_stvx): Generate
different rtl trees depending on TARGET_64BIT.
(rs6000_gen_lvx): Likewise.

From-SVN: r256762

re PR rtl-optimization/80481 (Unoptimal additional copy instructions)

2018-01-16  Vladimir Makarov  <vmakarov@redhat.com>

PR rtl-optimization/80481
* g++.dg/pr80481.C: Exclude solaris.

From-SVN: r256761

patchable_function_entry-decl.c: Use 3 NOPs on Visium.

* c-c++-common/patchable_function_entry-decl.c: Use 3 NOPs on Visium.
* c-c++-common/patchable_function_entry-default.c: 4 NOPs on Visium.
* c-c++-common/patchable_function_entry-definition.c: 2 NOPs on Visium.

From-SVN: r256760

ldist-27.c: Skip on Visium.

* gcc.dg/tree-ssa/ldist-27.c: Skip on Visium.
* gcc.dg/tree-ssa/loop-interchange-1.c: Likewise.
* gcc.dg/tree-ssa/loop-interchange-1b.c: Likewise.
* gcc.dg/tree-ssa/loop-interchange-2.c: Likewise.
* gcc.dg/tree-ssa/loop-interchange-3.c: Likewise.
* gcc.dg/tree-ssa/loop-interchange-4.c: Likewise.
* gcc.dg/tree-ssa/loop-interchange-5.c: Likewise.
* gcc.dg/tree-ssa/loop-interchange-6.c: Likewise.
* gcc.dg/tree-ssa/loop-interchange-7.c: Likewise.
* gcc.dg/tree-ssa/loop-interchange-8.c: Likewise.
* gcc.dg/tree-ssa/loop-interchange-9.c: Likewise.
* gcc.dg/tree-ssa/loop-interchange-10.c: Likewise.
* gcc.dg/tree-ssa/loop-interchange-11.c: Likewise.
* gcc.dg/tree-ssa/loop-interchange-14.c: Likewise.
* gcc.dg/tree-ssa/loop-interchange-15.c: Likewise.

From-SVN: r256759

visium.md (nop): Tweak comment.

* config/visium/visium.md (nop): Tweak comment.
(hazard_nop): Likewise.

From-SVN: r256758

re PR testsuite/77734 (FAIL: gcc.dg/plugin/must-tail-call-1.c -fplugin=./must_tail_call_plugin.so (test  for excess errors))

PR testsuite/77734
* gcc.dg/plugin/must-tail-call-1.c: Pass -fdelayed-branch on SPARC.

From-SVN: r256756

* testsuite/17_intro/names.cc: Undefine 'y' on SPARC/Linux.

From-SVN: r256754

rs6000.c (rs6000_opt_vars): Add entry for -mspeculate-indirect-jumps.

[gcc]

2018-01-16  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

* config/rs6000/rs6000.c (rs6000_opt_vars): Add entry for
-mspeculate-indirect-jumps.
* config/rs6000/rs6000.md (*call_indirect_elfv2<mode>): Disable
for -mno-speculate-indirect-jumps.
(*call_indirect_elfv2<mode>_nospec): New define_insn.
(*call_value_indirect_elfv2<mode>): Disable for
-mno-speculate-indirect-jumps.
(*call_value_indirect_elfv2<mode>_nospec): New define_insn.
(indirect_jump): Emit different RTL for
-mno-speculate-indirect-jumps.
(*indirect_jump<mode>): Disable for
-mno-speculate-indirect-jumps.
(*indirect_jump<mode>_nospec): New define_insn.
(tablejump): Emit different RTL for
-mno-speculate-indirect-jumps.
(tablejumpsi): Disable for -mno-speculate-indirect-jumps.
(tablejumpsi_nospec): New define_expand.
(tablejumpdi): Disable for -mno-speculate-indirect-jumps.
(tablejumpdi_nospec): New define_expand.
(*tablejump<mode>_internal1): Disable for
-mno-speculate-indirect-jumps.
(*tablejump<mode>_internal1_nospec): New define_insn.
* config/rs6000/rs6000.opt (mspeculate-indirect-jumps): New
option.

[gcc/testsuite]

2018-01-16  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

* gcc.target/powerpc/safe-indirect-jump-1.c: New file.
* gcc.target/powerpc/safe-indirect-jump-2.c: New file.
* gcc.target/powerpc/safe-indirect-jump-3.c: New file.
* gcc.target/powerpc/safe-indirect-jump-4.c: New file.
* gcc.target/powerpc/safe-indirect-jump-5.c: New file.
* gcc.target/powerpc/safe-indirect-jump-6.c: New file.

From-SVN: r256753

caller-save.c (insert_save): Drop unnecessary parameter.

        * caller-save.c (insert_save): Drop unnecessary parameter.  All
callers updated.

From-SVN: r256751

re PR libgomp/83590 ([nvptx] openacc reduction C regressions)

PR libgomp/83590
* gimplify.c (gimplify_one_sizepos): For is_gimple_constant (expr)
return early, inline manually is_gimple_sizepos.  Make sure if we
call gimplify_expr we don't end up with a gimple constant.
* tree.c (variably_modified_type_p): Don't return true for
is_gimple_constant (_t).  Inline manually is_gimple_sizepos.
* gimplify.h (is_gimple_sizepos): Remove.

Co-Authored-By: Richard Biener <rguenther@suse.de>
From-SVN: r256748

Two fixes for live-out SLP inductions (PR 83857)

vect_analyze_loop_operations was calling vectorizable_live_operation
for all live-out phis, which led to a bogus ncopies calculation in
the pure SLP case.  I think v_a_l_o should only be passing phis
that are vectorised using normal loop vectorisation, since
vect_slp_analyze_node_operations handles the SLP side (and knows
the correct slp_index and slp_node arguments to pass in, via
vect_analyze_stmt).

With that fixed we hit an older bug that vectorizable_live_operation
didn't handle live-out SLP inductions.  Fixed by using gimple_phi_result
rather than gimple_get_lhs for phis.

2018-01-16  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
PR tree-optimization/83857
* tree-vect-loop.c (vect_analyze_loop_operations): Don't call
vectorizable_live_operation for pure SLP statements.
(vectorizable_live_operation): Handle PHIs.

gcc/testsuite/
PR tree-optimization/83857
* gcc.dg/vect/pr83857.c: New test.

From-SVN: r256747

re PR tree-optimization/83867 (ICE: Segmentation fault in nested_in_vect_loop_p)

2018-01-16  Richard Biener  <rguenther@suse.de>

PR tree-optimization/83867
* tree-vect-stmts.c (vect_transform_stmt): Precompute
nested_in_vect_loop_p since the scalar stmt may get invalidated.

* gcc.dg/vect/pr83867.c: New testcase.

From-SVN: r256746

re PR c/83844 (ICE with warn_if_not_aligned attribute)

PR c/83844
* stor-layout.c (handle_warn_if_not_align): Use byte_position and
multiple_of_p instead of unchecked tree_to_uhwi and UHWI check.
If off is not INTEGER_CST, issue a may not be aligned warning
rather than isn't aligned.  Use isn%'t rather than isn't.
* fold-const.c (multiple_of_p) <case BIT_AND_EXPR>: Don't fall through
into MULT_EXPR.
<case MULT_EXPR>: Improve the case when bottom and one of the
MULT_EXPR operands are INTEGER_CSTs and bottom is multiple of that
operand, in that case check if the other operand is multiple of
bottom divided by the INTEGER_CST operand.

* gcc.dg/pr83844.c: New test.

From-SVN: r256745

Move pa.h FUNCTION_ARG_SIZE to pa.c (PR83858)

The port-local FUNCTION_ARG_SIZE:

  ((((MODE) != BLKmode \
     ? (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
     : int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)

is used by code in pa.c and by ASM_DECLARE_FUNCTION_NAME in som.h.
Treating GET_MODE_SIZE as a constant is OK for the former but not
the latter, which is used in target-independent code.  This caused
a build failure on hppa2.0w-hp-hpux11.11.

2018-01-16  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
PR target/83858
* config/pa/pa.h (FUNCTION_ARG_SIZE): Delete.
* config/pa/pa-protos.h (pa_function_arg_size): Declare.
* config/pa/som.h (ASM_DECLARE_FUNCTION_NAME): Use
pa_function_arg_size instead of FUNCTION_ARG_SIZE.
* config/pa/pa.c (pa_function_arg_advance): Likewise.
(pa_function_arg, pa_arg_partial_bytes): Likewise.
(pa_function_arg_size): New function.

From-SVN: r256744

Fix whitespace in changelog

From-SVN: r256743

Fix changelog

From-SVN: r256741

Avoid GCC 4.1 build failure in fold-const.c

We had:

      tree t = fold_vec_perm (type, arg1, arg2,
      vec_perm_indices (sel, 2, nelts));

where fold_vec_perm takes a const vec_perm_indices &.  GCC 4.1 apparently
required a public copy constructor:

gcc/vec-perm-indices.h:85: error: 'vec_perm_indices::vec_perm_indices(const vec_perm_indices&)' is private
gcc/fold-const.c:11410: error: within this context

even though no copy should be made here.  This patch tries to work
around that by constructing the vec_perm_indices separately.

2018-01-16  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* fold-const.c (fold_ternary_loc): Construct the vec_perm_indices
in a separate statement.

From-SVN: r256740

PR libstdc++/83834 replace wildcard pattern in linker script

PR libstdc++/83834
* config/abi/pre/gnu.ver (GLIBCXX_3.4): Replace std::c[a-g]* wildcard
pattern with exact match for std::cerr.

From-SVN: r256739

* MAINTAINERS (write after approval): Add myself.

From-SVN: r256738

Don't group gather loads (PR83847)

In the testcase we were trying to group two gather loads, even though
that isn't supported.  Fixed by explicitly disallowing grouping of
gathers and scatters.

This problem didn't show up on SVE because there we convert to
IFN_GATHER_LOAD/IFN_SCATTER_STORE pattern statements, which fail
the can_group_stmts_p check.

2018-01-16  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* tree-vect-data-refs.c (vect_analyze_data_ref_accesses):

gcc/testsuite/
* gcc.dg/torture/pr83847.c: New test.

From-SVN: r256730

re PR rtl-optimization/83620 (ICE: in assign_by_spills, at lra-assigns.c:1470: unable to find a register to spill with -flive-range-shrinkage --param=max-sched-ready-insns=0)

PR rtl-optimization/86620
* params.def (max-sched-ready-insns): Bump minimum value to 1.

* gcc.dg/pr64935-2.c: Use --param=max-sched-ready-insns=1
instead of --param=max-sched-ready-insns=0.
* gcc.target/i386/pr83620.c: New test.
* gcc.dg/pr83620.c: New test.

From-SVN: r256729

re PR rtl-optimization/83213 (peephole bug with -O2)

PR rtl-optimization/83213
* recog.c (peep2_attempt): Copy over CROSSING_JUMP_P from peepinsn
to last if both are JUMP_INSNs.

From-SVN: r256728

re PR tree-optimization/83843 (wrong code at -O2)

PR tree-optimization/83843
* gimple-ssa-store-merging.c
(imm_store_chain_info::output_merged_store): Handle bit_not_p on
store_immediate_info for bswap/nop orig_stores.

* gcc.dg/store_merging_18.c: New test.

From-SVN: r256727

re PR c++/83817 (internal compiler error: tree check: expected call_expr, have aggr_init_expr in tsubst_copy_and_build, at cp/pt.c:17822)

PR c++/83817
* pt.c (tsubst_copy_and_build) <case CALL_EXPR>: If function
is AGGR_INIT_EXPR rather than CALL_EXPR, set AGGR_INIT_FROM_THUNK_P
instead of CALL_FROM_THUNK_P.

* g++.dg/cpp1y/pr83817.C: New test.

From-SVN: r256726

re PR c++/83825 (ICE on invalid C++ code with shadowed identifiers: in operator[], at vec.h:826)

PR c++/83825
* name-lookup.c (member_vec_dedup): Return early if len is 0.
(resort_type_member_vec, set_class_bindings,
insert_late_enum_def_bindings): Use vec qsort method instead of
calling qsort directly.

* g++.dg/template/pr83825.C: New test.

From-SVN: r256725

pr83435.c: Restrict to target pthread.

2018-01-16  Richard Biener  <rguenther@suse.de>

* gcc.dg/graphite/pr83435.c: Restrict to target pthread.

From-SVN: r256724

re PR testsuite/82132 (FAIL: gcc.dg/vect/vect-tail-nomask-1.c (test for excess errors) due to missing posix_memalign)

2018-01-16  Richard Biener  <rguenther@suse.de>

PR testsuite/82132
* gcc.dg/vect/vect-tail-nomask-1.c: Copy posix_memalign boiler-plate
from gcc.dg/torture/pr60092.c.

From-SVN: r256723

RISC-V: Increase mult/div cost if not implemented in hardware.

2018-01-15  Andrew Waterman  <andrew@sifive.com>
gcc/
* config/riscv/riscv.c (riscv_rtx_costs) <MULT>: Increase cost if
!TARGET_MUL.
<UDIV>: Increase cost if !TARGET_DIV.

From-SVN: r256722

PR c++/83588 - struct with two flexible arrays causes an internal compiler error

gcc/cp/ChangeLog:

PR c++/83588
* class.c (find_flexarrays): Make a record of multiple flexible array
members.

gcc/testsuite/ChangeLog:

PR c++/83588
* g++.dg/ext/flexary28.C: New test.

From-SVN: r256721

re PR fortran/82257 (f951: Internal compiler error segmentation fault)

2018-01-15  Louis Krupp  <louis.krupp@zoho.com>

PR fortran/82257
* interface.c (compare_rank): Don't try to retrieve CLASS_DATA
from symbol marked unlimited polymorphic.
* resolve.c (resolve_structure_cons): Likewise.
* misc.c (gfc_typename): Don't dereference derived->components
if it's NULL.

2018-01-15  Louis Krupp  <louis.krupp@zoho.com>

PR fortran/82257
* gfortran.dg/unlimited_polymorphic_28.f90: New test.

From-SVN: r256720

Daily bump.

From-SVN: r256719

rs6000: Delete "delayed_cr" insn type

"delayed_cr" is just "cr_logical" with the second source operand not
equal to the destination operand.  This patch changes it to be
expressed as type "cr_logical", with a new boolean attribute
"cr_logical_3op" added.  This simplifies code.

* config/rs6000/rs6000.md (define_attr "type"): Remove delayed_cr.
(define_attr "cr_logical_3op"): New.
(cceq_ior_compare): Adjust.
(cceq_ior_compare_complement): Adjust.
(*cceq_rev_compare): Adjust.
* config/rs6000/rs6000.c (rs6000_adjust_cost): Adjust.
(is_cracked_insn): Adjust.
(insn_must_be_first_in_group): Adjust.
* config/rs6000/40x.md: Adjust.
* config/rs6000/440.md: Adjust.
* config/rs6000/476.md: Adjust.
* config/rs6000/601.md: Adjust.
* config/rs6000/603.md: Adjust.
* config/rs6000/6xx.md: Adjust.
* config/rs6000/7450.md: Adjust.
* config/rs6000/7xx.md: Adjust.
* config/rs6000/8540.md: Adjust.
* config/rs6000/cell.md: Adjust.
* config/rs6000/e300c2c3.md: Adjust.
* config/rs6000/e500mc.md: Adjust.
* config/rs6000/e500mc64.md: Adjust.
* config/rs6000/e5500.md: Adjust.
* config/rs6000/e6500.md: Adjust.
* config/rs6000/mpc.md: Adjust.
* config/rs6000/power4.md: Adjust.
* config/rs6000/power5.md: Adjust.
* config/rs6000/power6.md: Adjust.
* config/rs6000/power7.md: Adjust.
* config/rs6000/power8.md: Adjust.
* config/rs6000/power9.md: Adjust.
* config/rs6000/rs64.md: Adjust.
* config/rs6000/titan.md: Adjust.

From-SVN: r256716

i386: Rewrite indirect_branch_operand logic

* config/i386/predicates.md (indirect_branch_operand): Rewrite
ix86_indirect_branch_register logic.

From-SVN: r256715

Don't check ix86_indirect_branch_register for GOT operand

Since GOT_memory_operand and GOT32_symbol_operand are simple pattern
matches, don't check ix86_indirect_branch_register here.  If needed,
-mindirect-branch= will convert indirect branch via GOT slot to a call
and return thunk.

* config/i386/constraints.md (Bs): Update
ix86_indirect_branch_register check.  Don't check
ix86_indirect_branch_register with GOT_memory_operand.
(Bw): Likewise.
* config/i386/predicates.md (GOT_memory_operand): Don't check
ix86_indirect_branch_register here.
(GOT32_symbol_operand): Likewise.

From-SVN: r256714

i386: Rewrite ix86_indirect_branch_register logic

Rewrite ix86_indirect_branch_register logic with

(and (not (match_test "ix86_indirect_branch_register"))
     (original condition before r256662))

* config/i386/predicates.md (constant_call_address_operand):
Rewrite ix86_indirect_branch_register logic.
(sibcall_insn_operand): Likewise.

From-SVN: r256713

i386: Rename to ix86_indirect_branch_register

Rename the variable for -mindirect-branch-register to
ix86_indirect_branch_register to match the command-line option name.

* config/i386/constraints.md (Bs): Replace
ix86_indirect_branch_thunk_register with
ix86_indirect_branch_register.
(Bw): Likewise.
* config/i386/i386.md (indirect_jump): Likewise.
(tablejump): Likewise.
(*sibcall_memory): Likewise.
(*sibcall_value_memory): Likewise.
Peepholes of indirect call and jump via memory: Likewise.
* config/i386/i386.opt: Likewise.
* config/i386/predicates.md (indirect_branch_operand): Likewise.
(GOT_memory_operand): Likewise.
(call_insn_operand): Likewise.
(sibcall_insn_operand): Likewise.
(GOT32_symbol_operand): Likewise.

From-SVN: r256712

re PR middle-end/83837 (libgomp.fortran/pointer[12].f90 FAIL)

PR middle-end/83837
* omp-expand.c (expand_omp_atomic_pipeline): Use loaded_val
type rather than type addr's type points to.
(expand_omp_atomic_mutex): Likewise.
(expand_omp_atomic): Likewise.

From-SVN: r256710

PR testsuite/83869 - c-c++-common/attr-nonstring-3.c fails starting with r256683

testsuite/CHangeLog:
* c-c++-common/attr-nonstring-3.c: Work around bug c++/74762.

From-SVN: r256709

PR libstdc++/83833 fix chi_squared_distribution::param(const param&)

PR libstdc++/83833
* include/bits/random.h (chi_squared_distribution::param): Update
gamma distribution parameter.
* testsuite/26_numerics/random/chi_squared_distribution/83833.cc: New
test.

From-SVN: r256708

compiler: reclaim memory of escape analysis Nodes

    Reclaim the memory of escape analysis Nodes before kicking off
    the backend, as they are not needed in get_backend.

    Reviewed-on: https://go-review.googlesource.com/86243

From-SVN: r256707

compiler: make sure variables captured by defer closure live

    Local variables captured by the deferred closure need to be live
    until the function finishes, especially when the deferred
    function runs. In Function::build, for function that has a defer,
    we wrap the function body in a try block. So the backend sees
    the local variables only live in the try block, without knowing
    that they are needed also in the finally block where we invoke
    the deferred function. Fix this by creating top-level
    declarations for non-escaping address-taken locals when there
    is a defer.

    An example of miscompilation without this CL:

    func F(fn func()) {
            didPanic := true
            defer func() {
                    println(didPanic)
            }()
            fn()
            didPanic = false
    }

    With escape analysis turned on, at optimization level -O1 or -O2,
    the store "didPanic = false" is elided by the backend's
    optimizer, presumably because it thinks "didPanic" is not live
    after the store, so the store is useless.

    Reviewed-on: https://go-review.googlesource.com/86241

From-SVN: r256706

re PR fortran/54613 ([F08] Add FINDLOC plus support MAXLOC/MINLOC with KIND=/BACK=)

2018-01-15  Thomas Koenig  <tkoenig@gcc.gnu.org>

PR fortran/54613
* gfortran.h (gfc_check_f): Rename f4ml to f5ml.
(gfc_logical_4_kind): New macro
* intrinsic.h (gfc_simplify_minloc): Add a gfc_expr *argument.
(gfc_simplify_maxloc): Likewise.
(gfc_resolve_maxloc): Likewise.
(gfc_resolve_minloc): Likewise.
* check.c (gfc_check_minloc_maxloc): Add checking for "back"
argument; also raise error if it is used (for now). Add it
if it isn't present.
* intrinsic.c (add_sym_4ml): Rename to
(add_sym_5ml), adjust for extra argument.
(add_functions): Add "back" constant. Adjust maxloc and minloc
for back argument.
* iresolve.c (gfc_resolve_maxloc): Add back argument. If back is
not of gfc_logical_4_kind, convert.
(gfc_resolve_minloc): Likewise.
* simplify.c (gfc_simplify_minloc): Add back argument.
(gfc_simplify_maxloc): Likewise.
* trans-intinsic.c (gfc_conv_intrinsic_minmaxloc): Rename last
argument to %VAL to ensure passing by value.
(gfc_conv_intrinsic_function): Call gfc_conv_intrinsic_minmaxloc
also for library calls.

2018-01-15  Thomas Koenig  <tkoenig@gcc.gnu.org>

PR fortran/54613
* m4/iparm.m4: Add back_arg macro if in minloc or maxloc.
* m4/iforeach-s.m4: Add optional argument back with back_arg
macro. Improve m4 quoting. If HAVE_BACK_ARG is defined, assert
that back is non-true.
* m4/iforeach.m4: Likewise.
* m4/ifunction-s.m4: Likewise.
* m4/ifunction.m4: Likewise.
* m4/maxloc0.m4: Include assert.h
* m4/minloc0.m4: Likewise.
* m4/maxloc0s.m4: #define HAVE_BACK_ARG.
* m4/minloc0s.m4: Likewise.
* m4/maxloc1s.m4: Likewise.
* m4/minloc1s.m4: Likewise.
* m4/maxloc1.m4: Include assert.h, #define HAVE_BACK_ARG.
* m4/minloc1.m4: Likewise.
* m4/maxloc2s.m4: Add assert.h, add back_arg, assert that
back is non-true.
* m4/minloc2s.m4: Likewise.
* generated/iall_i1.c: Regenerated.
* generated/iall_i16.c: Regenerated.
* generated/iall_i2.c: Regenerated.
* generated/iall_i4.c: Regenerated.
* generated/iall_i8.c: Regenerated.
* generated/iany_i1.c: Regenerated.
* generated/iany_i16.c: Regenerated.
* generated/iany_i2.c: Regenerated.
* generated/iany_i4.c: Regenerated.
* generated/iany_i8.c: Regenerated.
* generated/iparity_i1.c: Regenerated.
* generated/iparity_i16.c: Regenerated.
* generated/iparity_i2.c: Regenerated.
* generated/iparity_i4.c: Regenerated.
* generated/iparity_i8.c: Regenerated.
* generated/maxloc0_16_i1.c: Regenerated.
* generated/maxloc0_16_i16.c: Regenerated.
* generated/maxloc0_16_i2.c: Regenerated.
* generated/maxloc0_16_i4.c: Regenerated.
* generated/maxloc0_16_i8.c: Regenerated.
* generated/maxloc0_16_r10.c: Regenerated.
* generated/maxloc0_16_r16.c: Regenerated.
* generated/maxloc0_16_r4.c: Regenerated.
* generated/maxloc0_16_r8.c: Regenerated.
* generated/maxloc0_16_s1.c: Regenerated.
* generated/maxloc0_16_s4.c: Regenerated.
* generated/maxloc0_4_i1.c: Regenerated.
* generated/maxloc0_4_i16.c: Regenerated.
* generated/maxloc0_4_i2.c: Regenerated.
* generated/maxloc0_4_i4.c: Regenerated.
* generated/maxloc0_4_i8.c: Regenerated.
* generated/maxloc0_4_r10.c: Regenerated.
* generated/maxloc0_4_r16.c: Regenerated.
* generated/maxloc0_4_r4.c: Regenerated.
* generated/maxloc0_4_r8.c: Regenerated.
* generated/maxloc0_4_s1.c: Regenerated.
* generated/maxloc0_4_s4.c: Regenerated.
* generated/maxloc0_8_i1.c: Regenerated.
* generated/maxloc0_8_i16.c: Regenerated.
* generated/maxloc0_8_i2.c: Regenerated.
* generated/maxloc0_8_i4.c: Regenerated.
* generated/maxloc0_8_i8.c: Regenerated.
* generated/maxloc0_8_r10.c: Regenerated.
* generated/maxloc0_8_r16.c: Regenerated.
* generated/maxloc0_8_r4.c: Regenerated.
* generated/maxloc0_8_r8.c: Regenerated.
* generated/maxloc0_8_s1.c: Regenerated.
* generated/maxloc0_8_s4.c: Regenerated.
* generated/maxloc1_16_i1.c: Regenerated.
* generated/maxloc1_16_i16.c: Regenerated.
* generated/maxloc1_16_i2.c: Regenerated.
* generated/maxloc1_16_i4.c: Regenerated.
* generated/maxloc1_16_i8.c: Regenerated.
* generated/maxloc1_16_r10.c: Regenerated.
* generated/maxloc1_16_r16.c: Regenerated.
* generated/maxloc1_16_r4.c: Regenerated.
* generated/maxloc1_16_r8.c: Regenerated.
* generated/maxloc1_16_s1.c: Regenerated.
* generated/maxloc1_16_s4.c: Regenerated.
* generated/maxloc1_4_i1.c: Regenerated.
* generated/maxloc1_4_i16.c: Regenerated.
* generated/maxloc1_4_i2.c: Regenerated.
* generated/maxloc1_4_i4.c: Regenerated.
* generated/maxloc1_4_i8.c: Regenerated.
* generated/maxloc1_4_r10.c: Regenerated.
* generated/maxloc1_4_r16.c: Regenerated.
* generated/maxloc1_4_r4.c: Regenerated.
* generated/maxloc1_4_r8.c: Regenerated.
* generated/maxloc1_4_s1.c: Regenerated.
* generated/maxloc1_4_s4.c: Regenerated.
* generated/maxloc1_8_i1.c: Regenerated.
* generated/maxloc1_8_i16.c: Regenerated.
* generated/maxloc1_8_i2.c: Regenerated.
* generated/maxloc1_8_i4.c: Regenerated.
* generated/maxloc1_8_i8.c: Regenerated.
* generated/maxloc1_8_r10.c: Regenerated.
* generated/maxloc1_8_r16.c: Regenerated.
* generated/maxloc1_8_r4.c: Regenerated.
* generated/maxloc1_8_r8.c: Regenerated.
* generated/maxloc1_8_s1.c: Regenerated.
* generated/maxloc1_8_s4.c: Regenerated.
* generated/maxval_i1.c: Regenerated.
* generated/maxval_i16.c: Regenerated.
* generated/maxval_i2.c: Regenerated.
* generated/maxval_i4.c: Regenerated.
* generated/maxval_i8.c: Regenerated.
* generated/maxval_r10.c: Regenerated.
* generated/maxval_r16.c: Regenerated.
* generated/maxval_r4.c: Regenerated.
* generated/maxval_r8.c: Regenerated.
* generated/minloc0_16_i1.c: Regenerated.
* generated/minloc0_16_i16.c: Regenerated.
* generated/minloc0_16_i2.c: Regenerated.
* generated/minloc0_16_i4.c: Regenerated.
* generated/minloc0_16_i8.c: Regenerated.
* generated/minloc0_16_r10.c: Regenerated.
* generated/minloc0_16_r16.c: Regenerated.
* generated/minloc0_16_r4.c: Regenerated.
* generated/minloc0_16_r8.c: Regenerated.
* generated/minloc0_16_s1.c: Regenerated.
* generated/minloc0_16_s4.c: Regenerated.
* generated/minloc0_4_i1.c: Regenerated.
* generated/minloc0_4_i16.c: Regenerated.
* generated/minloc0_4_i2.c: Regenerated.
* generated/minloc0_4_i4.c: Regenerated.
* generated/minloc0_4_i8.c: Regenerated.
* generated/minloc0_4_r10.c: Regenerated.
* generated/minloc0_4_r16.c: Regenerated.
* generated/minloc0_4_r4.c: Regenerated.
* generated/minloc0_4_r8.c: Regenerated.
* generated/minloc0_4_s1.c: Regenerated.
* generated/minloc0_4_s4.c: Regenerated.
* generated/minloc0_8_i1.c: Regenerated.
* generated/minloc0_8_i16.c: Regenerated.
* generated/minloc0_8_i2.c: Regenerated.
* generated/minloc0_8_i4.c: Regenerated.
* generated/minloc0_8_i8.c: Regenerated.
* generated/minloc0_8_r10.c: Regenerated.
* generated/minloc0_8_r16.c: Regenerated.
* generated/minloc0_8_r4.c: Regenerated.
* generated/minloc0_8_r8.c: Regenerated.
* generated/minloc0_8_s1.c: Regenerated.
* generated/minloc0_8_s4.c: Regenerated.
* generated/minloc1_16_i1.c: Regenerated.
* generated/minloc1_16_i16.c: Regenerated.
* generated/minloc1_16_i2.c: Regenerated.
* generated/minloc1_16_i4.c: Regenerated.
* generated/minloc1_16_i8.c: Regenerated.
* generated/minloc1_16_r10.c: Regenerated.
* generated/minloc1_16_r16.c: Regenerated.
* generated/minloc1_16_r4.c: Regenerated.
* generated/minloc1_16_r8.c: Regenerated.
* generated/minloc1_16_s1.c: Regenerated.
* generated/minloc1_16_s4.c: Regenerated.
* generated/minloc1_4_i1.c: Regenerated.
* generated/minloc1_4_i16.c: Regenerated.
* generated/minloc1_4_i2.c: Regenerated.
* generated/minloc1_4_i4.c: Regenerated.
* generated/minloc1_4_i8.c: Regenerated.
* generated/minloc1_4_r10.c: Regenerated.
* generated/minloc1_4_r16.c: Regenerated.
* generated/minloc1_4_r4.c: Regenerated.
* generated/minloc1_4_r8.c: Regenerated.
* generated/minloc1_4_s1.c: Regenerated.
* generated/minloc1_4_s4.c: Regenerated.
* generated/minloc1_8_i1.c: Regenerated.
* generated/minloc1_8_i16.c: Regenerated.
* generated/minloc1_8_i2.c: Regenerated.
* generated/minloc1_8_i4.c: Regenerated.
* generated/minloc1_8_i8.c: Regenerated.
* generated/minloc1_8_r10.c: Regenerated.
* generated/minloc1_8_r16.c: Regenerated.
* generated/minloc1_8_r4.c: Regenerated.
* generated/minloc1_8_r8.c: Regenerated.
* generated/minloc1_8_s1.c: Regenerated.
* generated/minloc1_8_s4.c: Regenerated.
* generated/minval_i1.c: Regenerated.
* generated/minval_i16.c: Regenerated.
* generated/minval_i2.c: Regenerated.
* generated/minval_i4.c: Regenerated.
* generated/minval_i8.c: Regenerated.
* generated/minval_r10.c: Regenerated.
* generated/minval_r16.c: Regenerated.
* generated/minval_r4.c: Regenerated.
* generated/minval_r8.c: Regenerated.
* generated/norm2_r10.c: Regenerated.
* generated/norm2_r16.c: Regenerated.
* generated/norm2_r4.c: Regenerated.
* generated/norm2_r8.c: Regenerated.
* generated/parity_l1.c: Regenerated.
* generated/parity_l16.c: Regenerated.
* generated/parity_l2.c: Regenerated.
* generated/parity_l4.c: Regenerated.
* generated/parity_l8.c: Regenerated.
* generated/product_c10.c: Regenerated.
* generated/product_c16.c: Regenerated.
* generated/product_c4.c: Regenerated.
* generated/product_c8.c: Regenerated.
* generated/product_i1.c: Regenerated.
* generated/product_i16.c: Regenerated.
* generated/product_i2.c: Regenerated.
* generated/product_i4.c: Regenerated.
* generated/product_i8.c: Regenerated.
* generated/product_r10.c: Regenerated.
* generated/product_r16.c: Regenerated.
* generated/product_r4.c: Regenerated.
* generated/product_r8.c: Regenerated.
* generated/sum_c10.c: Regenerated.
* generated/sum_c16.c: Regenerated.
* generated/sum_c4.c: Regenerated.
* generated/sum_c8.c: Regenerated.
* generated/sum_i1.c: Regenerated.
* generated/sum_i16.c: Regenerated.
* generated/sum_i2.c: Regenerated.
* generated/sum_i4.c: Regenerated.
* generated/sum_i8.c: Regenerated.
* generated/sum_r10.c: Regenerated.
* generated/sum_r16.c: Regenerated.
* generated/sum_r4.c: Regenerated.
* generated/sum_r8.c: Regenerated.

2018-01-15  Thomas Koenig  <tkoenig@gcc.gnu.org>

PR fortran/54613
* gfortran.dg/minmaxloc_9.f90: New test.
* gfortran.dg/minmaxloc_10.f90: New test.
* gfortran.dg/minmaxloc_11.f90: New test.

From-SVN: r256705

i386: Don't use ASM_OUTPUT_DEF for TARGET_MACHO

ASM_OUTPUT_DEF isn't defined for TARGET_MACHO.  Use ASM_OUTPUT_LABEL to
generate the __x86_return_thunk label, instead of the set directive.
Update testcase to remove the __x86_return_thunk label check.  Since
-fno-pic is ignored on Darwin, update testcases to scan or "push" only
on Linux.

gcc/

PR target/83839
* config/i386/i386.c (output_indirect_thunk_function): Use
ASM_OUTPUT_LABEL, instead of ASM_OUTPUT_DEF, for TARGET_MACHO
for  __x86_return_thunk.

gcc/testsuite/

PR target/83839
* gcc.target/i386/indirect-thunk-1.c: Scan for "push" only on
Linux.
* gcc.target/i386/indirect-thunk-2.c: Likewise.
* gcc.target/i386/indirect-thunk-3.c: Likewise.
* gcc.target/i386/indirect-thunk-4.c: Likewise.
* gcc.target/i386/indirect-thunk-7.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-1.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-2.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-5.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-6.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-7.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-1.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-2.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-3.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-4.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-7.c: Likewise.
* gcc.target/i386/indirect-thunk-register-1.c: Likewise.
* gcc.target/i386/indirect-thunk-register-3.c: Likewise.
* gcc.target/i386/indirect-thunk-register-4.c: Likewise.
* gcc.target/i386/ret-thunk-10.c: Likewise.
* gcc.target/i386/ret-thunk-11.c: Likewise.
* gcc.target/i386/ret-thunk-12.c: Likewise.
* gcc.target/i386/ret-thunk-13.c: Likewise.
* gcc.target/i386/ret-thunk-14.c: Likewise.
* gcc.target/i386/ret-thunk-15.c: Likewise.
* gcc.target/i386/ret-thunk-9.c: Don't check the
__x86_return_thunk label.
Scan for "push" only for Linux.

From-SVN: r256704

PR libstdc++/83830 Define std::has_unique_object_representations_v

PR libstdc++/83830
* include/std/type_traits (has_unique_object_representations_v): Add
variable template.
* testsuite/20_util/has_unique_object_representations/value.cc: Check
variable template.

From-SVN: r256701

re PR target/83850 (Spills on vector extract, gcc.target/i386/pr80846-1.c FAILs)

2018-01-15  Richard Biener  <rguenther@suse.de>

PR middle-end/83850
* expmed.c (extract_bit_field_1): Fix typo.

From-SVN: r256700

Missing vect_double in gcc.dg/vect/pr79920.c (PR83836)

2018-01-15  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/testsuite/
PR testsuite/79920
* gcc.dg/vect/pr79920.c: Restrict reduction test to vect_double

From-SVN: r256698

[arm] PR target/83687: Fix invalid combination of VSUB + VABS into VABD

In this wrong-code bug we combine a VSUB.I8 and a VABS.S8
into a VABD.S8 instruction . This combination is not valid
for integer operands because in the VABD instruction the semantics
are that the difference is computed in notionally infinite precision
and the absolute difference is computed on that, whereas for a
VSUB.I8 + VABS.S8 sequence the VSUB operation will perform any
wrapping that's needed for the 8-bit signed type before the VABS
gets its hands on it.

This leads to the wrong-code in the PR where the expected
sequence from the intrinsics:
VSUB + VABS of two vectors {-100, -100, -100...}, {100, 100, 100...}
gives a result of {56, 56, 56...} (-100 - 100)

but GCC optimises it into a single
VABD of {-100, -100, -100...}, {100, 100, 100...}
which produces a result of {200, 200, 200...}

The transformation is still valid for floating-point operands,
which is why it was added in the first place I believe (r178817)
but this patch disables it for integer operands.
The HFmode variants though only exist for TARGET_NEON_FP16INST, so
this patch adds the appropriate guards to the new mode iterator

Bootstrapped and tested on arm-none-linux-gnueabihf.

PR target/83687
* config/arm/iterators.md (VF): New mode iterator.
* config/arm/neon.md (neon_vabd<mode>_2): Use the above.
Remove integer-related logic from pattern.
(neon_vabd<mode>_3): Likewise.

* gcc.target/arm/neon-combine-sub-abs-into-vabd.c: Delete integer
tests.
* gcc.target/arm/pr83687.c: New test.

From-SVN: r256696

Make optional conditionally trivially_{copy,move}_{constructible,assignable}

* include/std/optional (_Optional_payload): Fix the comment in
the class head and turn into a primary and one specialization.
(_Optional_payload::_M_engaged): Strike the NSDMI.
(_Optional_payload<_Tp, false>::operator=(const _Optional_payload&)):
New.
(_Optional_payload<_Tp, false>::operator=(_Optional_payload&&)):
Likewise.
(_Optional_payload<_Tp, false>::_M_get): Likewise.
(_Optional_payload<_Tp, false>::_M_reset): Likewise.
(_Optional_base_impl): Likewise.
(_Optional_base): Turn into a primary and three specializations.
(optional(nullopt)): Change the base init.
* testsuite/20_util/optional/assignment/8.cc: New.
* testsuite/20_util/optional/cons/trivial.cc: Likewise.
* testsuite/20_util/optional/cons/value_neg.cc: Adjust.

From-SVN: r256694

Adjust tests to AVR_TINY.

* gcc.target/avr/progmem.h (pgm_read_char): Handle AVR_TINY.
* gcc.target/avr/pr52472.c: Add "! avr_tiny" target filter.
* gcc.target/avr/pr71627.c: Same.
* gcc.target/avr/torture/addr-space-1-0.c: Same.
* gcc.target/avr/torture/addr-space-1-1.c: Same.
* gcc.target/avr/torture/addr-space-1-x.c: Same.
* gcc.target/avr/torture/addr-space-2-0.c: Same.
* gcc.target/avr/torture/addr-space-2-1.c: Same.
* gcc.target/avr/torture/addr-space-2-x.c: Same.
* gcc.target/avr/torture/sat-hr-plus-minus.c: Same.
* gcc.target/avr/torture/sat-k-plus-minus.c: Same.
* gcc.target/avr/torture/sat-llk-plus-minus.c: Same.
* gcc.target/avr/torture/sat-r-plus-minus.c: Same.
* gcc.target/avr/torture/sat-uhr-plus-minus.c: Same.
* gcc.target/avr/torture/sat-uk-plus-minus.c: Same.
* gcc.target/avr/torture/sat-ullk-plus-minus.c: Same.
* gcc.target/avr/torture/sat-ur-plus-minus.c: Same.
* gcc.target/avr/torture/pr61055.c: Same.
* gcc.target/avr/torture/builtins-3-absfx.c: Only use __flash if
available.
* gcc.target/avr/torture/int24-mul.c: Same.
* gcc.target/avr/torture/pr51782-1.c: Same.
* gcc.target/avr/torture/pr61443.c: Same.
* gcc.target/avr/torture/builtins-2.c: Factor out addr-space stuff...
* gcc.target/avr/torture/builtins-2-flash.c: ...to this new test.

From-SVN: r256690

PR libstdc++/80276 fix template argument handling in type printers

PR libstdc++/80276
* python/libstdcxx/v6/printers.py (strip_inline_namespaces): New.
(get_template_arg_list): New.
(StdVariantPrinter._template_args): Remove, use get_template_arg_list
instead.
(TemplateTypePrinter): Rewrite to work with gdb.Type objects instead
of strings and regular expressions.
(add_one_template_type_printer): Adapt to new TemplateTypePrinter.
(FilteringTypePrinter): Add docstring. Match using startswith. Use
strip_inline_namespaces instead of strip_versioned_namespace.
(add_one_type_printer): Prepend namespace to match argument.
(register_type_printers): Add type printers for char16_t and char32_t
string types and for types using cxx11 ABI. Update calls to
add_one_template_type_printer to provide default argument dicts.
* testsuite/libstdc++-prettyprinters/80276.cc: New test.
* testsuite/libstdc++-prettyprinters/whatis.cc: Remove tests for
basic_string<unsigned char> and basic_string<signed char>.
* testsuite/libstdc++-prettyprinters/whatis2.cc: Duplicate whatis.cc
to test local variables, without overriding _GLIBCXX_USE_CXX11_ABI.

From-SVN: r256689

Correct earlier ChangeLog entry

Add Juraj Oršulić as original patch author.

From-SVN: r256688

re PR c/83801 ([avr] String constant in __flash not put into .progmem)

PR c/83801
PR c/83729
* gcc.target/avr/torture/pr83729.c: New test.
* gcc.target/avr/torture/pr83801.c: New test.

From-SVN: r256687

re PR middle-end/82694 (Linux kernel miscompiled since r250765)

PR middle-end/82694
* common.opt (fstrict-overflow): No longer an alias.
(fwrapv-pointer): New option.
* tree.h (TYPE_OVERFLOW_WRAPS, TYPE_OVERFLOW_UNDEFINED): Define
also for pointer types based on flag_wrapv_pointer.
* opts.c (common_handle_option) <case OPT_fstrict_overflow>: Set
opts->x_flag_wrap[pv] to !value, clear opts->x_flag_trapv if
opts->x_flag_wrapv got set.
* fold-const.c (fold_comparison, fold_binary_loc): Revert 2017-08-01
changes, just use TYPE_OVERFLOW_UNDEFINED on pointer type instead of
POINTER_TYPE_OVERFLOW_UNDEFINED.
* match.pd: Likewise in address comparison pattern.
* doc/invoke.texi: Document -fwrapv and -fstrict-overflow.

* gcc.dg/no-strict-overflow-7.c: Revert 2017-08-01 changes.
* gcc.dg/tree-ssa/pr81388-1.c: Likewise.

From-SVN: r256686

re PR lto/83804 ([meta] LTO memory consumption)

2018-01-15  Richard Biener  <rguenther@suse.de>

PR lto/83804
* tree.c (free_lang_data_in_type): Always unlink TYPE_DECLs
from TYPE_FIELDS.  Free TYPE_BINFO if not used by devirtualization.
Reset type names to their identifier if their TYPE_DECL doesn't
have linkage (and thus is used for ODR and devirt).
(save_debug_info_for_decl): Remove.
(save_debug_info_for_type): Likewise.
(add_tree_to_fld_list): Adjust.
* tree-pretty-print.c (dump_generic_node): Make dumping of
type names more robust.

From-SVN: r256685

BASE-VER: Bump to 8.0.1.

2018-01-15  Richard Biener  <rguenther@suse.de>

* BASE-VER: Bump to 8.0.1.

From-SVN: r256684

re PR other/83508 ([arm] c-c++-common/Wrestrict.c fails since r255836)

PR other/83508
* builtins.c (check_access): Avoid warning when the no-warning bit
is set.

PR other/83508
* gcc.dg/Wstringop-overflow-2.c: New test.

From-SVN: r256683

tree-ssa-loop-im.c (sort_bbs_in_loop_postorder_cmp): Stabilize sort.

* tree-ssa-loop-im.c (sort_bbs_in_loop_postorder_cmp): Stabilize sort.
* ira-color (allocno_hard_regs_compare): Likewise.

From-SVN: r256682

re PR target/83013 (MicroBlaze - #ident - Error: operation combines symbols in different segments)

        PR target/83013
        * config/microblaze/microblaze.c (microblaze_asm_output_ident):
        Use .pushsection/.popsection.

From-SVN: r256681

Daily bump.

From-SVN: r256680

PR c++/81327 - cast to void* does not suppress -Wclass-memaccess

gcc/ChangeLog:
PR c++/81327
* doc/invoke.texi (-Wlass-memaccess): Document suppression by casting.

From-SVN: r256677

Fix date in log.

From-SVN: r256676

Fix date in Changelog

From-SVN: r256674

Correct ChangeLog of x86: Add -mfunction-return=

From-SVN: r256673

Correct ChangeLog of x86: Add -mindirect-branch=

From-SVN: r256672

re PR libfortran/83811 (fortran 'e' format broken for single digit exponents)

2018-01-18  Jerry DeLisle  <jvdelisle@gcc.gnu.org>

        PR libgfortran/83811
        * write.c (select_buffer): Adjust buffer size up by 1.

        * gfortran.dg/fmt_e.f90: New test.

From-SVN: r256669

re PR libstdc++/81092 (Missing symbols for new std::wstring constructors)

PR libstdc++/81092
* config/abi/post/ia64-linux-gnu/baseline_symbols.txt: Update.

From-SVN: r256668

config.gcc (i[34567]86-*-*): Remove one duplicate gfniintrin.h entry from extra_headers.

* config.gcc (i[34567]86-*-*): Remove one duplicate gfniintrin.h
entry from extra_headers.
(x86_64-*-*): Remove two duplicate gfniintrin.h entries from
extra_headers, make the list bitwise identical to the i?86-*-* one.

From-SVN: r256667

x86: Disallow -mindirect-branch=/-mfunction-return= with -mcmodel=large

Since the thunk function may not be reachable in large code model,
-mcmodel=large is incompatible with -mindirect-branch=thunk,
-mindirect-branch=thunk-extern, -mfunction-return=thunk and
-mfunction-return=thunk-extern.  Issue an error when they are used with
-mcmodel=large.

gcc/

* config/i386/i386.c (ix86_set_indirect_branch_type): Disallow
-mcmodel=large with -mindirect-branch=thunk,
-mindirect-branch=thunk-extern, -mfunction-return=thunk and
-mfunction-return=thunk-extern.
* doc/invoke.texi: Document -mcmodel=large is incompatible with
-mindirect-branch=thunk, -mindirect-branch=thunk-extern,
-mfunction-return=thunk and -mfunction-return=thunk-extern.

gcc/testsuite/

* gcc.target/i386/indirect-thunk-10.c: New test.
* gcc.target/i386/indirect-thunk-8.c: Likewise.
* gcc.target/i386/indirect-thunk-9.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-10.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-11.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-9.c: Likewise.
* gcc.target/i386/ret-thunk-17.c: Likewise.
* gcc.target/i386/ret-thunk-18.c: Likewise.
* gcc.target/i386/ret-thunk-19.c: Likewise.
* gcc.target/i386/ret-thunk-20.c: Likewise.
* gcc.target/i386/ret-thunk-21.c: Likewise.

From-SVN: r256664

x86: Add 'V' register operand modifier

Add 'V', a special modifier which prints the name of the full integer
register without '%'.  For

extern void (*func_p) (void);

void
foo (void)
{
  asm ("call __x86_indirect_thunk_%V0" : : "a" (func_p));
}

it generates:

foo:
movq func_p(%rip), %rax
call __x86_indirect_thunk_rax
ret

gcc/

* config/i386/i386.c (print_reg): Print the name of the full
integer register without '%'.
(ix86_print_operand): Handle 'V'.
 * doc/extend.texi: Document 'V' modifier.

gcc/testsuite/

* gcc.target/i386/indirect-thunk-register-4.c: New test.

From-SVN: r256663

x86: Add -mindirect-branch-register

Add -mindirect-branch-register to force indirect branch via register.
This is implemented by disabling patterns of indirect branch via memory,
similar to TARGET_X32.

-mindirect-branch= and -mfunction-return= tests are updated with
-mno-indirect-branch-register to avoid false test failures when
-mindirect-branch-register is added to RUNTESTFLAGS for "make check".

gcc/

* config/i386/constraints.md (Bs): Disallow memory operand for
-mindirect-branch-register.
(Bw): Likewise.
* config/i386/predicates.md (indirect_branch_operand): Likewise.
(GOT_memory_operand): Likewise.
(call_insn_operand): Likewise.
(sibcall_insn_operand): Likewise.
(GOT32_symbol_operand): Likewise.
* config/i386/i386.md (indirect_jump): Call convert_memory_address
for -mindirect-branch-register.
(tablejump): Likewise.
(*sibcall_memory): Likewise.
(*sibcall_value_memory): Likewise.
Disallow peepholes of indirect call and jump via memory for
-mindirect-branch-register.
(*call_pop): Replace m with Bw.
(*call_value_pop): Likewise.
(*sibcall_pop_memory): Replace m with Bs.
* config/i386/i386.opt (mindirect-branch-register): New option.
* doc/invoke.texi: Document -mindirect-branch-register option.

gcc/testsuite/

* gcc.target/i386/indirect-thunk-1.c (dg-options): Add
-mno-indirect-branch-register.
* gcc.target/i386/indirect-thunk-2.c: Likewise.
* gcc.target/i386/indirect-thunk-3.c: Likewise.
* gcc.target/i386/indirect-thunk-4.c: Likewise.
* gcc.target/i386/indirect-thunk-5.c: Likewise.
* gcc.target/i386/indirect-thunk-6.c: Likewise.
* gcc.target/i386/indirect-thunk-7.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-1.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-2.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-3.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-4.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-5.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-6.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-7.c: Likewise.
* gcc.target/i386/indirect-thunk-bnd-1.c: Likewise.
* gcc.target/i386/indirect-thunk-bnd-2.c: Likewise.
* gcc.target/i386/indirect-thunk-bnd-3.c: Likewise.
* gcc.target/i386/indirect-thunk-bnd-4.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-1.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-2.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-3.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-4.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-5.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-6.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-7.c: Likewise.
* gcc.target/i386/indirect-thunk-inline-1.c: Likewise.
* gcc.target/i386/indirect-thunk-inline-2.c: Likewise.
* gcc.target/i386/indirect-thunk-inline-3.c: Likewise.
* gcc.target/i386/indirect-thunk-inline-4.c: Likewise.
* gcc.target/i386/indirect-thunk-inline-5.c: Likewise.
* gcc.target/i386/indirect-thunk-inline-6.c: Likewise.
* gcc.target/i386/indirect-thunk-inline-7.c: Likewise.
* gcc.target/i386/ret-thunk-10.c: Likewise.
* gcc.target/i386/ret-thunk-11.c: Likewise.
* gcc.target/i386/ret-thunk-12.c: Likewise.
* gcc.target/i386/ret-thunk-13.c: Likewise.
* gcc.target/i386/ret-thunk-14.c: Likewise.
* gcc.target/i386/ret-thunk-15.c: Likewise.
* gcc.target/i386/ret-thunk-9.c: Likewise.
* gcc.target/i386/indirect-thunk-register-1.c: New test.
* gcc.target/i386/indirect-thunk-register-2.c: Likewise.
* gcc.target/i386/indirect-thunk-register-3.c: Likewise.

From-SVN: r256662

x86: Add -mfunction-return=

Add -mfunction-return= option to convert function return to call and
return thunks.  The default is 'keep', which keeps function return
unmodified.  'thunk' converts function return to call and return thunk.
'thunk-inline' converts function return to inlined call and return thunk.
'thunk-extern' converts function return to external call and return
thunk provided in a separate object file.  You can control this behavior
for a specific function by using the function attribute function_return.

Function return thunk is the same as memory thunk for -mindirect-branch=
where the return address is at the top of the stack:

__x86_return_thunk:
call L2
L1:
pause
lfence
jmp L1
L2:
lea 8(%rsp), %rsp|lea 4(%esp), %esp
ret

and function return becomes

jmp __x86_return_thunk

-mindirect-branch= tests are updated with -mfunction-return=keep to
avoid false test failures when -mfunction-return=thunk is added to
RUNTESTFLAGS for "make check".

gcc/

* config/i386/i386-protos.h (ix86_output_function_return): New.
* config/i386/i386.c (ix86_set_indirect_branch_type): Also
set function_return_type.
(indirect_thunk_name): Add ret_p to indicate thunk for function
return.
(output_indirect_thunk_function): Pass false to
indirect_thunk_name.
(ix86_output_indirect_branch): Likewise.
(output_indirect_thunk_function): Create alias for function
return thunk if regno < 0.
(ix86_output_function_return): New function.
(ix86_handle_fndecl_attribute): Handle function_return.
(ix86_attribute_table): Add function_return.
* config/i386/i386.h (machine_function): Add
function_return_type.
* config/i386/i386.md (simple_return_internal): Use
ix86_output_function_return.
(simple_return_internal_long): Likewise.
* config/i386/i386.opt (mfunction-return=): New option.
(indirect_branch): Mention -mfunction-return=.
* doc/extend.texi: Document function_return function attribute.
* doc/invoke.texi: Document -mfunction-return= option.

gcc/testsuite/

* gcc.target/i386/indirect-thunk-1.c (dg-options): Add
-mfunction-return=keep.
* gcc.target/i386/indirect-thunk-2.c: Likewise.
* gcc.target/i386/indirect-thunk-3.c: Likewise.
* gcc.target/i386/indirect-thunk-4.c: Likewise.
* gcc.target/i386/indirect-thunk-5.c: Likewise.
* gcc.target/i386/indirect-thunk-6.c: Likewise.
* gcc.target/i386/indirect-thunk-7.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-1.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-2.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-3.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-4.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-5.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-6.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-7.c: Likewise.
* gcc.target/i386/indirect-thunk-attr-8.c: Likewise.
* gcc.target/i386/indirect-thunk-bnd-1.c: Likewise.
* gcc.target/i386/indirect-thunk-bnd-2.c: Likewise.
* gcc.target/i386/indirect-thunk-bnd-3.c: Likewise.
* gcc.target/i386/indirect-thunk-bnd-4.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-1.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-2.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-3.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-4.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-5.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-6.c: Likewise.
* gcc.target/i386/indirect-thunk-extern-7.c: Likewise.
* gcc.target/i386/indirect-thunk-inline-1.c: Likewise.
* gcc.target/i386/indirect-thunk-inline-2.c: Likewise.
* gcc.target/i386/indirect-thunk-inline-3.c: Likewise.
* gcc.target/i386/indirect-thunk-inline-4.c: Likewise.
* gcc.target/i386/indirect-thunk-inline-5.c: Likewise.
* gcc.target/i386/indirect-thunk-inline-6.c: Likewise.
* gcc.target/i386/indirect-thunk-inline-7.c: Likewise.
* gcc.target/i386/ret-thunk-1.c: New test.
* gcc.target/i386/ret-thunk-10.c: Likewise.
* gcc.target/i386/ret-thunk-11.c: Likewise.
* gcc.target/i386/ret-thunk-12.c: Likewise.
* gcc.target/i386/ret-thunk-13.c: Likewise.
* gcc.target/i386/ret-thunk-14.c: Likewise.
* gcc.target/i386/ret-thunk-15.c: Likewise.
* gcc.target/i386/ret-thunk-16.c: Likewise.
* gcc.target/i386/ret-thunk-2.c: Likewise.
* gcc.target/i386/ret-thunk-3.c: Likewise.
* gcc.target/i386/ret-thunk-4.c: Likewise.
* gcc.target/i386/ret-thunk-5.c: Likewise.
* gcc.target/i386/ret-thunk-6.c: Likewise.
* gcc.target/i386/ret-thunk-7.c: Likewise.
* gcc.target/i386/ret-thunk-8.c: Likewise.
* gcc.target/i386/ret-thunk-9.c: Likewise.

From-SVN: r256661