Clifford Wolf [Tue, 20 Jun 2017 02:41:58 +0000 (04:41 +0200)]
Store command history when terminating with an error
Clifford Wolf [Tue, 20 Jun 2017 02:22:34 +0000 (04:22 +0200)]
Switched abc "clock domain not found" error to log_cmd_error()
Clifford Wolf [Wed, 7 Jun 2017 10:30:24 +0000 (12:30 +0200)]
Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"
Clifford Wolf [Thu, 1 Jun 2017 10:43:21 +0000 (12:43 +0200)]
Fix handling of Verilog ~& and ~| operators
Clifford Wolf [Wed, 31 May 2017 09:55:37 +0000 (11:55 +0200)]
Update ABC to hg rev
efbf7f13ea9e
Clifford Wolf [Wed, 31 May 2017 09:45:58 +0000 (11:45 +0200)]
Add dff2ff.v techmap file
Clifford Wolf [Tue, 30 May 2017 17:09:11 +0000 (19:09 +0200)]
Fix AIGER back-end for multiple symbols per input/latch/output/property
Clifford Wolf [Sun, 28 May 2017 09:59:05 +0000 (11:59 +0200)]
Add "setundef -anyseq"
Clifford Wolf [Sun, 28 May 2017 09:31:35 +0000 (11:31 +0200)]
Improve write_aiger handling of unconnected nets and constants
Clifford Wolf [Sat, 27 May 2017 09:56:01 +0000 (11:56 +0200)]
Change default smt2 solver to yices (Yices 2 has switched its license to GPL)
Clifford Wolf [Wed, 24 May 2017 09:39:05 +0000 (11:39 +0200)]
Add aliases for common sets of gate types to "abc -g"
Clifford Wolf [Tue, 23 May 2017 16:38:20 +0000 (18:38 +0200)]
Add examples/osu035
Clifford Wolf [Tue, 23 May 2017 16:24:27 +0000 (18:24 +0200)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Tue, 23 May 2017 12:07:30 +0000 (14:07 +0200)]
Merge pull request #346 from azonenberg/master
greenpak4_counters: Added support for parallel output from GP_COUNTx cells
Andrew Zonenberg [Tue, 23 May 2017 02:39:55 +0000 (19:39 -0700)]
greenpak4_counters: Added support for parallel output from GP_COUNTx cells
Clifford Wolf [Wed, 17 May 2017 19:07:54 +0000 (21:07 +0200)]
Add workaround for CBMC bug to SimpleC back-end
Clifford Wolf [Wed, 17 May 2017 18:46:22 +0000 (20:46 +0200)]
Enable readline and tcl in mxe builds
Clifford Wolf [Wed, 17 May 2017 17:10:57 +0000 (19:10 +0200)]
Add missing AndnotGate() and OrnotGate() declarations to rtlil.h
Clifford Wolf [Wed, 17 May 2017 07:08:29 +0000 (09:08 +0200)]
Add $_ANDNOT_ and $_ORNOT_ gates
Clifford Wolf [Tue, 16 May 2017 17:34:07 +0000 (19:34 +0200)]
Add <modname>_init() function generator to simpleC back-end
Clifford Wolf [Tue, 16 May 2017 06:50:23 +0000 (08:50 +0200)]
Improve simplec back-end
Clifford Wolf [Mon, 15 May 2017 11:21:59 +0000 (13:21 +0200)]
Improve simplec back-end
Clifford Wolf [Sun, 14 May 2017 11:14:49 +0000 (13:14 +0200)]
Improve simplec back-end
Clifford Wolf [Sat, 13 May 2017 16:47:31 +0000 (18:47 +0200)]
Improve simplec back-end
Clifford Wolf [Fri, 12 May 2017 20:36:53 +0000 (22:36 +0200)]
Improve simplec back-end
Clifford Wolf [Fri, 12 May 2017 15:42:31 +0000 (17:42 +0200)]
Added support for more gate types to simplec back-end
Clifford Wolf [Fri, 12 May 2017 12:13:33 +0000 (14:13 +0200)]
Add first draft of simple C back-end
Clifford Wolf [Thu, 11 May 2017 08:32:32 +0000 (10:32 +0200)]
Update ABC to hg rev
e79576e10d72
Clifford Wolf [Mon, 8 May 2017 12:33:22 +0000 (14:33 +0200)]
Fix boolector support in yosys-smtbmc
Clifford Wolf [Sun, 30 Apr 2017 15:20:30 +0000 (17:20 +0200)]
Add support for localparam in module header
Clifford Wolf [Fri, 28 Apr 2017 16:54:53 +0000 (18:54 +0200)]
Fix equiv_simple, old behavior now available with "equiv_simple -short"
Clifford Wolf [Wed, 26 Apr 2017 14:09:32 +0000 (16:09 +0200)]
Add support for `resetall compiler directive
Clifford Wolf [Wed, 12 Apr 2017 14:51:46 +0000 (16:51 +0200)]
Replace CRLF line endings with LF in de2i.qsf (quartus example)
Larry Doolittle [Sun, 9 Apr 2017 03:54:31 +0000 (20:54 -0700)]
Squelch trailing whitespace
Clifford Wolf [Fri, 7 Apr 2017 08:01:28 +0000 (10:01 +0200)]
Add MAX10 and Cyclone IV items to CHANGELOG
Clifford Wolf [Fri, 7 Apr 2017 07:58:54 +0000 (09:58 +0200)]
Merge pull request #337 from dh73/master
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
dh73 [Thu, 6 Apr 2017 04:01:29 +0000 (23:01 -0500)]
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
Clifford Wolf [Wed, 5 Apr 2017 09:25:22 +0000 (11:25 +0200)]
Add ConstEval defaultval feature
Clifford Wolf [Wed, 5 Apr 2017 09:21:06 +0000 (11:21 +0200)]
Fix gcc compiler warning
Clifford Wolf [Tue, 28 Mar 2017 10:13:58 +0000 (12:13 +0200)]
Add front-end detection for *.tcl files
Clifford Wolf [Mon, 27 Mar 2017 12:36:24 +0000 (14:36 +0200)]
Add minisat 00_PATCH_typofixes.patch
Clifford Wolf [Mon, 27 Mar 2017 12:32:43 +0000 (14:32 +0200)]
Remove use of <fpu_control.h> in minisat
Clifford Wolf [Mon, 20 Mar 2017 11:00:35 +0000 (12:00 +0100)]
Add "write_smt2 -stdt" mode
Clifford Wolf [Sun, 19 Mar 2017 13:57:40 +0000 (14:57 +0100)]
Add generation of logic cells to EDIF back-end runtest.py
Clifford Wolf [Sun, 19 Mar 2017 13:53:28 +0000 (14:53 +0100)]
Fix EDIF: portRef member 0 is always the MSB bit
Clifford Wolf [Sat, 18 Mar 2017 14:00:03 +0000 (15:00 +0100)]
Add simple EDIF test case generator and checker
Clifford Wolf [Tue, 14 Mar 2017 16:27:28 +0000 (17:27 +0100)]
Fix verilog pre-processor for multi-level relative includes
Clifford Wolf [Sat, 4 Mar 2017 22:41:54 +0000 (23:41 +0100)]
Improve smt2 encodings of assert/assume/cover, better wire_smt2 help msg
Clifford Wolf [Thu, 2 Mar 2017 15:39:48 +0000 (16:39 +0100)]
Add write_aiger $anyseq support
Clifford Wolf [Wed, 1 Mar 2017 09:47:05 +0000 (10:47 +0100)]
Allow $anyconst, etc. in non-formal SV mode
Clifford Wolf [Tue, 28 Feb 2017 21:17:00 +0000 (22:17 +0100)]
Disable opt_merge for $anyseq and $anyconst
Clifford Wolf [Tue, 28 Feb 2017 12:54:50 +0000 (13:54 +0100)]
Use hex addresses in smtbmc vcd mem traces
Clifford Wolf [Mon, 27 Feb 2017 22:59:59 +0000 (23:59 +0100)]
Add "chformal -assert2assume" and friends
Clifford Wolf [Mon, 27 Feb 2017 12:25:28 +0000 (13:25 +0100)]
Add "chformal" pass
Clifford Wolf [Sun, 26 Feb 2017 20:26:32 +0000 (21:26 +0100)]
Add smtbmc support for memory vcd dumping
Clifford Wolf [Sun, 26 Feb 2017 13:41:27 +0000 (14:41 +0100)]
Fix extra newline bug in write_smt2
Clifford Wolf [Sun, 26 Feb 2017 13:39:07 +0000 (14:39 +0100)]
Fix bug in smtio unroll code
Clifford Wolf [Sun, 26 Feb 2017 10:06:26 +0000 (11:06 +0100)]
Fix assert checking in "yosys-smtbmc -c --append"
Clifford Wolf [Sun, 26 Feb 2017 09:58:34 +0000 (10:58 +0100)]
Improve (and fix for stbv mode) SMT2 memory API
Clifford Wolf [Sat, 25 Feb 2017 22:41:40 +0000 (23:41 +0100)]
Add support for "yosys-smtbmc -c --append"
Clifford Wolf [Sat, 25 Feb 2017 21:59:34 +0000 (22:59 +0100)]
Update ABC to hg rev
3a95bfa55df7
Clifford Wolf [Sat, 25 Feb 2017 15:36:23 +0000 (16:36 +0100)]
Merge branch 'klammerj-master'
Clifford Wolf [Sat, 25 Feb 2017 15:35:53 +0000 (16:35 +0100)]
Improve "write_edif" help message
Clifford Wolf [Sat, 25 Feb 2017 15:29:27 +0000 (16:29 +0100)]
Move EdifNames out of double-private namespace
Clifford Wolf [Sat, 25 Feb 2017 15:28:34 +0000 (16:28 +0100)]
Clean up edif code, swap bit indexing of "upto" ports
Clifford Wolf [Sat, 25 Feb 2017 14:59:02 +0000 (15:59 +0100)]
Merge branch 'master' of https://github.com/klammerj/yosys into klammerj-master
Clifford Wolf [Sat, 25 Feb 2017 12:08:27 +0000 (13:08 +0100)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Sat, 25 Feb 2017 12:07:15 +0000 (13:07 +0100)]
Add $live and $fair support to AIGER back-end.
Clifford Wolf [Sat, 25 Feb 2017 09:36:39 +0000 (10:36 +0100)]
Add $live and $fair cell types, add support for s_eventually keyword
Clifford Wolf [Fri, 24 Feb 2017 18:23:29 +0000 (19:23 +0100)]
Merge pull request #322 from azonenberg/master
Add POUT to GP_COUNTx cells
Clifford Wolf [Fri, 24 Feb 2017 17:24:53 +0000 (18:24 +0100)]
Add "write_smt2 -stbv"
Andrew Zonenberg [Fri, 24 Feb 2017 16:12:45 +0000 (08:12 -0800)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Fri, 24 Feb 2017 13:04:52 +0000 (14:04 +0100)]
Add SMT2 statebv mode (inactive for now)
Johann Klammer [Fri, 24 Feb 2017 12:18:49 +0000 (13:18 +0100)]
Did as you requested, /but/...
Now the nets are wired in reverse again because the netlister still uses zero-based indices.
Clifford Wolf [Fri, 24 Feb 2017 11:48:12 +0000 (12:48 +0100)]
Merge pull request #320 from joshhead/uninstall-binpath-fix
Add missing slashes in paths for make uninstall
Josh Headapohl [Fri, 24 Feb 2017 01:21:03 +0000 (20:21 -0500)]
Add missing slashes in paths for make uninstall
Running make uninstall used to fail to remove binaries:
rm -vf /usr/local/binyosys /usr/local/binyosys-config #...etc
Fix Makefile so that it runs a command like this:
rm -vf /usr/local/bin/yosys /usr/local/bin/yosys-config #...etc
Johann Klammer [Thu, 23 Feb 2017 18:42:37 +0000 (19:42 +0100)]
add options for edif flavors
*to force renames on wide ports
*to choose array delimiters
*to choose up or downwards indices
Clifford Wolf [Thu, 23 Feb 2017 15:33:19 +0000 (16:33 +0100)]
Add support for SystemVerilog unique, unique0, and priority case
Clifford Wolf [Thu, 23 Feb 2017 14:39:13 +0000 (15:39 +0100)]
Preserve string parameters
Clifford Wolf [Thu, 23 Feb 2017 13:21:02 +0000 (14:21 +0100)]
Fix mingw compile issue (2nd attempt)
Clifford Wolf [Thu, 23 Feb 2017 12:59:02 +0000 (13:59 +0100)]
Fix mingw compile issue (maybe.. I can't test it)
Clifford Wolf [Thu, 23 Feb 2017 10:21:33 +0000 (11:21 +0100)]
Added SystemVerilog support for ++ and --
Clifford Wolf [Wed, 22 Feb 2017 18:20:47 +0000 (19:20 +0100)]
Update ABC to hg rev
8da4dc435b9f
Clifford Wolf [Sun, 19 Feb 2017 21:51:29 +0000 (22:51 +0100)]
Add "yosys-smtbmc -S <opt>"
Andrew Zonenberg [Thu, 16 Feb 2017 15:48:44 +0000 (07:48 -0800)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Thu, 16 Feb 2017 11:28:42 +0000 (12:28 +0100)]
Copy attributes to _TECHMAP_REPLACE_ cells
Clifford Wolf [Thu, 16 Feb 2017 11:17:03 +0000 (12:17 +0100)]
Fix eval implementation of $_NOR_
Andrew Zonenberg [Tue, 14 Feb 2017 16:29:37 +0000 (08:29 -0800)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Tue, 14 Feb 2017 14:10:59 +0000 (15:10 +0100)]
Fix incorrect "incompatible re-declaration of wire" error in tasks/functions
Clifford Wolf [Tue, 14 Feb 2017 11:49:35 +0000 (12:49 +0100)]
Add warning about x/z bits left unconnected in EDIF output
Clifford Wolf [Tue, 14 Feb 2017 10:57:54 +0000 (11:57 +0100)]
Fix double-call of log_pop() in synth_greenpak4
Clifford Wolf [Tue, 14 Feb 2017 10:49:14 +0000 (11:49 +0100)]
Merge pull request #313 from azidar/bugfix-assign-wmask
More progress on Firrtl backend.
Adam Izraelevitz [Tue, 22 Nov 2016 01:28:17 +0000 (17:28 -0800)]
More progress on Firrtl backend.
Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a
simple rocket-chip design.
Clifford Wolf [Mon, 13 Feb 2017 16:07:38 +0000 (17:07 +0100)]
Do not fix port widths on any blackbox instances
Clifford Wolf [Mon, 13 Feb 2017 15:55:25 +0000 (16:55 +0100)]
Fix techmap for inout ports connected to inout ports
Clifford Wolf [Sun, 12 Feb 2017 16:42:57 +0000 (17:42 +0100)]
Do not eagerly fix port widths on parameterized cells
Clifford Wolf [Sun, 12 Feb 2017 10:11:00 +0000 (11:11 +0100)]
Add "yosys -w" for suppressing warnings
Andrew Zonenberg [Sat, 11 Feb 2017 19:25:16 +0000 (11:25 -0800)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Sat, 11 Feb 2017 14:57:36 +0000 (15:57 +0100)]
Add support for verific mem initialization
Clifford Wolf [Sat, 11 Feb 2017 10:47:51 +0000 (11:47 +0100)]
Fix another stupid bug in the same line