litex.git
4 years agobios/sdram: update/simplify with new exported LiteDRAM parameters.
Florent Kermarrec [Thu, 16 Apr 2020 08:23:31 +0000 (10:23 +0200)]
bios/sdram: update/simplify with new exported LiteDRAM parameters.

4 years agolitex_sim: add phytype to PhySettings.
Florent Kermarrec [Thu, 16 Apr 2020 08:22:43 +0000 (10:22 +0200)]
litex_sim: add phytype to PhySettings.

4 years agobuild/generic_programmer: move requests import to do it only when needed.
Florent Kermarrec [Thu, 16 Apr 2020 06:44:36 +0000 (08:44 +0200)]
build/generic_programmer: move requests import to do it only when needed.

4 years agobios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4.
Florent Kermarrec [Wed, 15 Apr 2020 17:30:23 +0000 (19:30 +0200)]
bios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4.

Bitslip software control is now used on ECP5 to move dqs_read.

4 years agosetup.py/install_requires: add requests.
Florent Kermarrec [Wed, 15 Apr 2020 07:27:26 +0000 (09:27 +0200)]
setup.py/install_requires: add requests.

4 years agobuild/generic_programmer: add automatic search/download of flash_proxy in repositorie...
Florent Kermarrec [Wed, 15 Apr 2020 06:59:03 +0000 (08:59 +0200)]
build/generic_programmer: add automatic search/download of flash_proxy in repositories if not available locally.

4 years agoMerge pull request #467 from antmicro/region_type_fix
enjoy-digital [Wed, 15 Apr 2020 05:56:48 +0000 (07:56 +0200)]
Merge pull request #467 from antmicro/region_type_fix

soc_core: Fix region type generation

4 years agosoc_core: Fix region type generation
Mateusz Holenko [Tue, 14 Apr 2020 19:43:58 +0000 (21:43 +0200)]
soc_core: Fix region type generation

Include information about being a linker region.

4 years agostream/AsyncFIFO: add default depth (useful when used for CDC).
Florent Kermarrec [Tue, 14 Apr 2020 15:34:57 +0000 (17:34 +0200)]
stream/AsyncFIFO: add default depth (useful when used for CDC).

4 years agobuild/sim/core/Makefile: add -p to mkdir modules.
Florent Kermarrec [Tue, 14 Apr 2020 10:38:02 +0000 (12:38 +0200)]
build/sim/core/Makefile: add -p to mkdir modules.

4 years agoMerge pull request #464 from mithro/litex-sim-fixes
enjoy-digital [Tue, 14 Apr 2020 10:16:21 +0000 (12:16 +0200)]
Merge pull request #464 from mithro/litex-sim-fixes

Improve the litex_sim Makefiles

4 years agolitex_setup: raise exception on update if repository has been been initialized.
Florent Kermarrec [Sun, 12 Apr 2020 17:46:56 +0000 (19:46 +0200)]
litex_setup: raise exception on update if repository has been been initialized.

4 years agoRemove trailing whitespace.
Tim 'mithro' Ansell [Sun, 12 Apr 2020 17:29:13 +0000 (10:29 -0700)]
Remove trailing whitespace.

4 years agocores: add External Memory Interface (EMIF) Wishbone bridge.
Florent Kermarrec [Sun, 12 Apr 2020 14:34:33 +0000 (16:34 +0200)]
cores: add External Memory Interface (EMIF) Wishbone bridge.

Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.

4 years agoMerge pull request #462 from ironsteel/trellis-12k
enjoy-digital [Sun, 12 Apr 2020 13:49:49 +0000 (15:49 +0200)]
Merge pull request #462 from ironsteel/trellis-12k

Add support for ecp5 12k device in trellis.py

4 years agoboards/targets/ulx3s.py: Update --device option help message
Rangel Ivanov [Sun, 12 Apr 2020 08:51:08 +0000 (11:51 +0300)]
boards/targets/ulx3s.py: Update --device option help message

Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
4 years agobuild/lattice/trellis.py: Add 12k device
Rangel Ivanov [Sun, 12 Apr 2020 08:46:44 +0000 (11:46 +0300)]
build/lattice/trellis.py: Add 12k device

nextpnr adds the --12k option which is the same like
the --25k but with the correct idcode for the 12k devices

Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
4 years agolitex_sim: Rework Makefiles to put output files in gateware directory.
Tim 'mithro' Ansell [Sun, 12 Apr 2020 01:26:15 +0000 (18:26 -0700)]
litex_sim: Rework Makefiles to put output files in gateware directory.

4 years agolitex_sim: Better error messages on failure to load module.
Tim 'mithro' Ansell [Sun, 12 Apr 2020 01:23:40 +0000 (18:23 -0700)]
litex_sim: Better error messages on failure to load module.

4 years agoREADME: LiteDRAM moved to travis-ci.com as others repositories.
Florent Kermarrec [Fri, 10 Apr 2020 17:11:21 +0000 (19:11 +0200)]
README: LiteDRAM moved to travis-ci.com as others repositories.

4 years agoaltera/common: add DDROutput, DDRInput, SDROutput, SDRInput.
Florent Kermarrec [Fri, 10 Apr 2020 13:50:35 +0000 (15:50 +0200)]
altera/common: add DDROutput, DDRInput, SDROutput, SDRInput.

4 years agotargets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
Florent Kermarrec [Fri, 10 Apr 2020 12:41:01 +0000 (14:41 +0200)]
targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.

4 years agobuild/xilinx/common: add Spartan6 specialized DDRInput, SDROutput, SDRInput and SDRTr...
Florent Kermarrec [Fri, 10 Apr 2020 12:38:22 +0000 (14:38 +0200)]
build/xilinx/common: add Spartan6 specialized DDRInput, SDROutput, SDRInput and SDRTristate.

4 years agobuild/io: add SDR Tristate (with infered version) and remove multi-bits support on...
Florent Kermarrec [Fri, 10 Apr 2020 12:37:29 +0000 (14:37 +0200)]
build/io: add SDR Tristate (with infered version) and remove multi-bits support on SDRIO.

4 years agobuild/lattice/common: remove multi-bits support on SDRInput/Output.
Florent Kermarrec [Fri, 10 Apr 2020 12:36:13 +0000 (14:36 +0200)]
build/lattice/common: remove multi-bits support on SDRInput/Output.

4 years agolitex/build/io: also import CRG (since using DifferentialInput).
Florent Kermarrec [Fri, 10 Apr 2020 08:25:21 +0000 (10:25 +0200)]
litex/build/io: also import CRG (since using DifferentialInput).

4 years agolitex.build: update from migen.genlib.io litex.build.io.
Florent Kermarrec [Fri, 10 Apr 2020 07:18:39 +0000 (09:18 +0200)]
litex.build: update from migen.genlib.io litex.build.io.

4 years agolitex/build: move io.py from litex/gen and re-import DifferentialInput/Output, DDRInp...
Florent Kermarrec [Fri, 10 Apr 2020 06:47:07 +0000 (08:47 +0200)]
litex/build: move io.py from litex/gen and re-import DifferentialInput/Output, DDRInput/Output contributed to Migen.

This will make things easier and more consistent, all special IO primitives are now in LiteX.

4 years agoplatforms/versa_ecp5: remove Lattice Programmer (no longer used since we can now...
Florent Kermarrec [Thu, 9 Apr 2020 21:08:59 +0000 (23:08 +0200)]
platforms/versa_ecp5: remove Lattice Programmer (no longer used since we can now use OpenOCD).

4 years agoboards/platforms: cosmetic cleanups.
Florent Kermarrec [Thu, 9 Apr 2020 21:04:29 +0000 (23:04 +0200)]
boards/platforms: cosmetic cleanups.

4 years agoboards/plarforms/ulx3s: cleanup, fix user_leds, add spisdcard, add PULLMODE/DRIVE...
Florent Kermarrec [Thu, 9 Apr 2020 16:55:01 +0000 (18:55 +0200)]
boards/plarforms/ulx3s: cleanup, fix user_leds, add spisdcard, add PULLMODE/DRIVE on SDRAM pins.

4 years agobuild/lattice: add ECP5 implementation for SDRInput/SDROutput.
Florent Kermarrec [Thu, 9 Apr 2020 14:24:05 +0000 (16:24 +0200)]
build/lattice: add ECP5 implementation for SDRInput/SDROutput.

4 years agolitex/gen: add io with SDRInput/SDROutput (if not overrided, register is supposed...
Florent Kermarrec [Thu, 9 Apr 2020 14:23:27 +0000 (16:23 +0200)]
litex/gen: add io with SDRInput/SDROutput (if not overrided, register is supposed to be infered).

4 years agotools/litex_sim: remove LiteSPI support for now since breaking Travis-CI of others...
Florent Kermarrec [Thu, 9 Apr 2020 09:14:19 +0000 (11:14 +0200)]
tools/litex_sim: remove LiteSPI support for now since breaking Travis-CI of others sub-projects.

LiteSPI is not mature enough to be integrated in LiteX sim directly. (will case trouble is things are refactored).

This could be re-introduced later when more mature. For now simulation with LiteX Sim
could be tested directly in LiteSPI with a custom simulation.

4 years agotools/litex_term: increase workaround delay for usb_fifo. (validated on Minispartan6...
Florent Kermarrec [Thu, 9 Apr 2020 08:52:15 +0000 (10:52 +0200)]
tools/litex_term: increase workaround delay for usb_fifo. (validated on Minispartan6 and MimasA7).

Still needs to be fixed properly.

4 years agoMerge pull request #459 from mithro/travis-fix
enjoy-digital [Thu, 9 Apr 2020 07:01:59 +0000 (09:01 +0200)]
Merge pull request #459 from mithro/travis-fix

Two small Travis-CI related patches

4 years agotravis: Run Windows build but allow it to fail.
Tim 'mithro' Ansell [Thu, 9 Apr 2020 06:14:26 +0000 (23:14 -0700)]
travis: Run Windows build but allow it to fail.

4 years agotravis: Use litex_setup.py from the checked out code.
Tim 'mithro' Ansell [Thu, 9 Apr 2020 06:12:41 +0000 (23:12 -0700)]
travis: Use litex_setup.py from the checked out code.

4 years agoMerge pull request #458 from david-sawatzke/add_triple
Tim Ansell [Thu, 9 Apr 2020 04:39:29 +0000 (21:39 -0700)]
Merge pull request #458 from david-sawatzke/add_triple

Add riscv64-none-elf triple

4 years agoAdd riscv64-none-elf triple
David Sawatzke [Thu, 9 Apr 2020 03:36:10 +0000 (05:36 +0200)]
Add riscv64-none-elf triple

4 years agosoc/cores/clock: add Max10PLL.
Florent Kermarrec [Wed, 8 Apr 2020 06:54:12 +0000 (08:54 +0200)]
soc/cores/clock: add Max10PLL.

4 years agosoc/cores/clock: add Cyclone10LPPLL.
Florent Kermarrec [Wed, 8 Apr 2020 06:33:57 +0000 (08:33 +0200)]
soc/cores/clock: add Cyclone10LPPLL.

4 years agosoc/cores/clock/CycloneVPLL: fix typos.
Florent Kermarrec [Wed, 8 Apr 2020 06:25:46 +0000 (08:25 +0200)]
soc/cores/clock/CycloneVPLL: fix typos.

4 years agosoc/cores/clock: rename Altera to Intel.
Florent Kermarrec [Wed, 8 Apr 2020 06:16:37 +0000 (08:16 +0200)]
soc/cores/clock: rename Altera to Intel.

4 years agosoc/cores/clock: add CycloneVPLL.
Florent Kermarrec [Tue, 7 Apr 2020 15:24:12 +0000 (17:24 +0200)]
soc/cores/clock: add CycloneVPLL.

4 years agotargets/de0nano: use CycloneIVPLL, remove 50MHz limitation.
Florent Kermarrec [Tue, 7 Apr 2020 15:00:40 +0000 (17:00 +0200)]
targets/de0nano: use CycloneIVPLL, remove 50MHz limitation.

4 years agosoc/cores/clock: add initial AlteraClocking/CycloneIV support.
Florent Kermarrec [Tue, 7 Apr 2020 14:59:53 +0000 (16:59 +0200)]
soc/cores/clock: add initial AlteraClocking/CycloneIV support.

4 years ago.travis.yml: disable windows test (failing for now).
Florent Kermarrec [Tue, 7 Apr 2020 10:43:29 +0000 (12:43 +0200)]
.travis.yml: disable windows test (failing for now).

4 years agoREADME.md: update RISCV toolchain installation.
Florent Kermarrec [Tue, 7 Apr 2020 10:39:52 +0000 (12:39 +0200)]
README.md: update RISCV toolchain installation.

4 years ago.travis.yml: remove Python3.5 test.
Florent Kermarrec [Tue, 7 Apr 2020 10:33:56 +0000 (12:33 +0200)]
.travis.yml: remove Python3.5 test.

4 years agoMerge pull request #451 from mithro/multi-os
enjoy-digital [Tue, 7 Apr 2020 10:29:04 +0000 (12:29 +0200)]
Merge pull request #451 from mithro/multi-os

Add multiple Python versions, Windows and Mac to Travis CI testing

4 years agosetup.py: simplify, switch to Python3.6+ (using python_requires), remove version.
Florent Kermarrec [Tue, 7 Apr 2020 09:48:16 +0000 (11:48 +0200)]
setup.py: simplify, switch to Python3.6+ (using python_requires), remove version.

- Deprecate Python 3.5, switch to Python 3.6+.
- Remove which was not used or updated. We'll see to get this back when working on releases.

4 years agolitex_setup: reorganize a bit, add separators/comments.
Florent Kermarrec [Tue, 7 Apr 2020 09:05:14 +0000 (11:05 +0200)]
litex_setup: reorganize a bit, add separators/comments.

4 years ago.travis.yml: revert full url for litex_setup.py.
Florent Kermarrec [Tue, 7 Apr 2020 08:55:58 +0000 (10:55 +0200)]
.travis.yml: revert full url for litex_setup.py.

We want to have an almost identical .travis.yml between LiteX and the Cores.
Using $TRAVIS_BUILD_DIR works for LiteX but will not work for the cores.

4 years agoMerge pull request #452 from mithro/riscv-download
enjoy-digital [Tue, 7 Apr 2020 08:51:27 +0000 (10:51 +0200)]
Merge pull request #452 from mithro/riscv-download

Add GCC downloading via litex_setup.py

4 years agoEnable testing on multiple Python versions.
Tim 'mithro' Ansell [Tue, 7 Apr 2020 00:52:07 +0000 (17:52 -0700)]
Enable testing on multiple Python versions.

Makes sure LiteX tests pass on all supported Python versions.

4 years agoEnable CI for Windows and Mac.
Tim 'mithro' Ansell [Mon, 6 Apr 2020 18:47:12 +0000 (11:47 -0700)]
Enable CI for Windows and Mac.

4 years agoRemove symlinking step.
Tim 'mithro' Ansell [Tue, 7 Apr 2020 00:57:32 +0000 (17:57 -0700)]
Remove symlinking step.

4 years agoUse shutil.unpack_archive.
Tim 'mithro' Ansell [Tue, 7 Apr 2020 00:45:55 +0000 (17:45 -0700)]
Use shutil.unpack_archive.

4 years agoIgnore SSL errors on CI.
Tim 'mithro' Ansell [Tue, 7 Apr 2020 00:36:09 +0000 (17:36 -0700)]
Ignore SSL errors on CI.

4 years agoImprove the path messages a little.
Tim 'mithro' Ansell [Tue, 7 Apr 2020 00:27:24 +0000 (17:27 -0700)]
Improve the path messages a little.

4 years agoMake travis use litex_setup.py for GCC download.
Tim 'mithro' Ansell [Mon, 6 Apr 2020 23:54:25 +0000 (16:54 -0700)]
Make travis use litex_setup.py for GCC download.

4 years agoAdding SiFive RISC-V toolchain downloading to litex_setup.py
Tim 'mithro' Ansell [Mon, 6 Apr 2020 23:39:49 +0000 (16:39 -0700)]
Adding SiFive RISC-V toolchain downloading to litex_setup.py

4 years agoFix alignments.
Tim 'mithro' Ansell [Mon, 6 Apr 2020 23:49:52 +0000 (16:49 -0700)]
Fix alignments.

4 years agoMerge pull request #450 from mithro/litex-setup-fix
enjoy-digital [Mon, 6 Apr 2020 21:04:47 +0000 (23:04 +0200)]
Merge pull request #450 from mithro/litex-setup-fix

litex_setup: Use subprocess so failures are noticed.

4 years agoRun `litex_setup.py` outside the git clone directory.
Tim 'mithro' Ansell [Mon, 6 Apr 2020 18:38:23 +0000 (11:38 -0700)]
Run `litex_setup.py` outside the git clone directory.

Otherwise it tries to overwrite the litex directory by cloning LiteX
into it.

4 years agolitex_setup: Use subprocess so failures are noticed.
Tim 'mithro' Ansell [Mon, 6 Apr 2020 18:25:11 +0000 (11:25 -0700)]
litex_setup: Use subprocess so failures are noticed.

os.system doesn't report if any of the commands fail. This means that if
something goes wrong it happily reports success making it hard to debug
issues.

4 years agosoc/cores: use reset_less on datapath/configuration CSRStorages.
Florent Kermarrec [Mon, 6 Apr 2020 11:16:13 +0000 (13:16 +0200)]
soc/cores: use reset_less on datapath/configuration CSRStorages.

4 years agointerconnect/csr: add reset_less parameter.
Florent Kermarrec [Mon, 6 Apr 2020 11:14:21 +0000 (13:14 +0200)]
interconnect/csr: add reset_less parameter.

In cases CSRStorage can be considered as a datapath/configuration register and does not need to be reseted.

4 years agointerconnect/csr, wishbone: use reset_less on datapath signals.
Florent Kermarrec [Mon, 6 Apr 2020 11:11:50 +0000 (13:11 +0200)]
interconnect/csr, wishbone: use reset_less on datapath signals.

4 years agocores/code_8b10b: set reset_less to True on datapath signals.
Florent Kermarrec [Mon, 6 Apr 2020 09:35:18 +0000 (11:35 +0200)]
cores/code_8b10b: set reset_less to True on datapath signals.

Reset is only required on control signals.

4 years agostream: set reset_less to True on datapath signals.
Florent Kermarrec [Mon, 6 Apr 2020 09:33:49 +0000 (11:33 +0200)]
stream: set reset_less to True on datapath signals.

Reset is only required on control signals.

4 years agoMerge pull request #448 from kessam/patch-1
enjoy-digital [Mon, 6 Apr 2020 09:12:12 +0000 (11:12 +0200)]
Merge pull request #448 from kessam/patch-1

Fix timing constraints

4 years agoFix timing constraints
kessam [Sun, 5 Apr 2020 15:56:29 +0000 (17:56 +0200)]
Fix timing constraints

4 years agosoc/cores/clock/ECP5PLL: add CLKI_DIV support.
Florent Kermarrec [Fri, 3 Apr 2020 09:14:57 +0000 (11:14 +0200)]
soc/cores/clock/ECP5PLL: add CLKI_DIV support.

4 years agoMerge pull request #447 from antmicro/spi-xip
enjoy-digital [Wed, 1 Apr 2020 14:51:29 +0000 (16:51 +0200)]
Merge pull request #447 from antmicro/spi-xip

Add initial support for the new LiteSPI core

4 years agotargets: netv2: add LiteSPI
Piotr Binkowski [Mon, 30 Mar 2020 11:43:34 +0000 (13:43 +0200)]
targets: netv2: add LiteSPI

4 years agoplatform: netv2: update SPI flash pinout
Piotr Binkowski [Mon, 30 Mar 2020 10:42:15 +0000 (12:42 +0200)]
platform: netv2: update SPI flash pinout

4 years agolitex_sim: add LiteSPI
Piotr Binkowski [Mon, 30 Mar 2020 11:42:56 +0000 (13:42 +0200)]
litex_sim: add LiteSPI

4 years agosoc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce.
Florent Kermarrec [Tue, 31 Mar 2020 14:54:38 +0000 (16:54 +0200)]
soc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce.

This reduces logic a bit. It does not make large difference on usual design with
only 1 UART, but is interesting on designs with hundreds of UARTs used to "document"
FPGA boards :) (similar to https://github.com/enjoy-digital/camlink_4k/blob/master/ios_stream.py)

4 years agosoc/cores/spi_flash: add ECP5SPIFlash (non-memory-mapped).
Florent Kermarrec [Tue, 31 Mar 2020 14:17:12 +0000 (16:17 +0200)]
soc/cores/spi_flash: add ECP5SPIFlash (non-memory-mapped).

4 years agolitex_setup: add litespi core
Piotr Binkowski [Mon, 30 Mar 2020 11:37:34 +0000 (13:37 +0200)]
litex_setup: add litespi core

4 years agoMerge pull request #444 from ilya-epifanov/openocd-jtag-programmer
enjoy-digital [Sat, 28 Mar 2020 11:58:08 +0000 (12:58 +0100)]
Merge pull request #444 from ilya-epifanov/openocd-jtag-programmer

Added openocd jtagspi programmer, to be used with ECP5-EVN board

4 years agoMerge pull request #441 from gsomlo/gls-spisdcard-fixes
enjoy-digital [Sat, 28 Mar 2020 11:50:17 +0000 (12:50 +0100)]
Merge pull request #441 from gsomlo/gls-spisdcard-fixes

SPI SDCard fixes and features

4 years agoAdded openocd jtagspi programmer, to be used with ECP5-EVN board
Ilya Epifanov [Sat, 28 Mar 2020 10:20:30 +0000 (11:20 +0100)]
Added openocd jtagspi programmer, to be used with ECP5-EVN board

4 years agosoftware/bios: add spisdcardboot() to boot_sequence()
Gabriel Somlo [Fri, 27 Mar 2020 11:02:00 +0000 (07:02 -0400)]
software/bios: add spisdcardboot() to boot_sequence()

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
4 years agosoftware/libbase/spisdcard: add delay to goidle loop
Gabriel Somlo [Fri, 27 Mar 2020 11:01:02 +0000 (07:01 -0400)]
software/libbase/spisdcard: add delay to goidle loop

In `spi_sdcard_goidle()`, insert a `busy_wait()` into the CMD55+ACMD41
loop to avoid exhausting the retry counter before the card has a chance
to be ready (required on the trellisboard, also tested OK on nexys4ddr).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
4 years agosoftware/bios: factor out busy_wait() function
Gabriel Somlo [Fri, 27 Mar 2020 10:58:06 +0000 (06:58 -0400)]
software/bios: factor out busy_wait() function

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
4 years agosoftware/libbase/spisdcard: fix width of address parameter
Gabriel Somlo [Fri, 27 Mar 2020 11:07:30 +0000 (07:07 -0400)]
software/libbase/spisdcard: fix width of address parameter

Host address parameter types should match CPU word width, so
use `unsigned long` to be correct on both 32 and 64 bit CPUs.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
4 years agosoc/cores/spi: make dynamic clk divider optional (can be enabled with add_clk_divider...
Florent Kermarrec [Fri, 27 Mar 2020 17:44:48 +0000 (18:44 +0100)]
soc/cores/spi: make dynamic clk divider optional (can be enabled with add_clk_divider method) and only use it in add_spi_sdcard.

4 years agoMerge pull request #439 from antmicro/fix-compiler-rt
enjoy-digital [Thu, 26 Mar 2020 14:36:39 +0000 (15:36 +0100)]
Merge pull request #439 from antmicro/fix-compiler-rt

Update removed llvm compiler-rt repo

4 years agoUpdate removed llvm compiler-rt repo
Kamil Rakoczy [Thu, 26 Mar 2020 09:56:28 +0000 (10:56 +0100)]
Update removed llvm compiler-rt repo

4 years agotargets/add_constant: avoid specifying value when value is None (=default).
Florent Kermarrec [Thu, 26 Mar 2020 08:45:19 +0000 (09:45 +0100)]
targets/add_constant: avoid specifying value when value is None (=default).

4 years agosoftware/libbase/spisdcard: add USE_SPISDCARD_RECLOCKING define to easily disable...
Florent Kermarrec [Thu, 26 Mar 2020 06:46:32 +0000 (07:46 +0100)]
software/libbase/spisdcard: add USE_SPISDCARD_RECLOCKING define to easily disable reclocking.

4 years agointegration/soc/add_uart: add USB CDC support (with ValentyUSB core).
Florent Kermarrec [Wed, 25 Mar 2020 18:07:06 +0000 (19:07 +0100)]
integration/soc/add_uart: add USB CDC support (with ValentyUSB core).

4 years agotools/litex_sim: simplify using uart_name=sim.
Florent Kermarrec [Wed, 25 Mar 2020 17:57:26 +0000 (18:57 +0100)]
tools/litex_sim: simplify using uart_name=sim.

4 years agointegration/soc/add_uart: add Model/Sim.
Florent Kermarrec [Wed, 25 Mar 2020 17:56:58 +0000 (18:56 +0100)]
integration/soc/add_uart: add Model/Sim.

4 years agointegration/soc/add_uart: cleanup.
Florent Kermarrec [Wed, 25 Mar 2020 17:53:00 +0000 (18:53 +0100)]
integration/soc/add_uart: cleanup.

4 years agobuild/tools: add replace_in_file function.
Florent Kermarrec [Wed, 25 Mar 2020 15:36:53 +0000 (16:36 +0100)]
build/tools: add replace_in_file function.

4 years agotools/litex_term: use 64 bytes as default payload_lengh (work for all confniguration...
Florent Kermarrec [Wed, 25 Mar 2020 08:31:51 +0000 (09:31 +0100)]
tools/litex_term: use 64 bytes as default payload_lengh (work for all confniguration) and add small delay between frames for FT245 FIFO.

The delay still need to be investigated.