Clifford Wolf [Tue, 31 Jan 2017 15:21:23 +0000 (16:21 +0100)]
Merge branch 'C-Elegans-opt_compare_pr'
Clifford Wolf [Tue, 31 Jan 2017 15:20:56 +0000 (16:20 +0100)]
Fix indenting and log messages in code merged from opt_compare_pr
Clifford Wolf [Tue, 31 Jan 2017 14:54:41 +0000 (15:54 +0100)]
Merge branch 'opt_compare_pr' of https://github.com/C-Elegans/yosys into C-Elegans-opt_compare_pr
Clifford Wolf [Tue, 31 Jan 2017 09:15:04 +0000 (10:15 +0100)]
Improve opt_rmdff support for $dlatch cells
C-Elegans [Mon, 30 Jan 2017 22:52:16 +0000 (17:52 -0500)]
Refactor and generalize the comparision optimization
Generalizes the optimization to:
a < C,
a >= C,
C > a,
C <= a
Clifford Wolf [Mon, 30 Jan 2017 10:38:43 +0000 (11:38 +0100)]
Add "yosys-smtbmc --aig <aim_filename>:<aiw_filename>" support
Clifford Wolf [Mon, 30 Jan 2017 09:50:38 +0000 (10:50 +0100)]
Add $ff and $_FF_ support to equiv_simple
Clifford Wolf [Sat, 28 Jan 2017 14:14:56 +0000 (15:14 +0100)]
Add "yosys-smtbmc --aig-noheader" and AIGER mem init support
Clifford Wolf [Thu, 26 Jan 2017 08:19:28 +0000 (09:19 +0100)]
Be more conservative with merging large cells into FSMs
Clifford Wolf [Thu, 26 Jan 2017 08:01:26 +0000 (09:01 +0100)]
Add warnings for quickly growing FSM table size in fsm_expand
Clifford Wolf [Thu, 26 Jan 2017 07:59:26 +0000 (08:59 +0100)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Wed, 25 Jan 2017 16:00:59 +0000 (17:00 +0100)]
Fix RTLIL::Memory::start_offset initialization
C-Elegans [Sat, 21 Jan 2017 17:58:26 +0000 (12:58 -0500)]
Do not use b.as_int() in calculation of bit set
Clifford Wolf [Tue, 17 Jan 2017 16:33:52 +0000 (17:33 +0100)]
Add "enum" and "typedef" lexer support
C-Elegans [Mon, 16 Jan 2017 15:16:03 +0000 (10:16 -0500)]
Optimize compares to powers of 2
Remove opt_compare and put comparison pass in opt_expr
assuming a [7:0] is unsigned
a >= (1<<x) becomes |a[7:x]
a < (1<<x) becomes !a[7:x]
Additionally:
a >= 0 becomes constant true,
a < 0 becomes constant false
delete opt_compare.cc
revert opt.cc to commit
b7cfb7dbd (remove opt_compare step)
Clifford Wolf [Mon, 16 Jan 2017 09:25:25 +0000 (10:25 +0100)]
Merge pull request #293 from thoughtpolice/minor-cleanup
Delete some dead code in the Hierarchy pass
Austin Seipp [Sun, 15 Jan 2017 22:39:12 +0000 (16:39 -0600)]
passes/hierarchy: delete some dead code
Signed-off-by: Austin Seipp <aseipp@pobox.com>
C-Elegans [Sun, 15 Jan 2017 14:23:04 +0000 (09:23 -0500)]
Fix issue #269, optimize signed compare with 0
add opt_compare pass and add it to opt
for a < 0:
if a is signed, replace with a[max_bit-1]
for a >= 0:
if a is signed, replace with ~a[max_bit-1]
Clifford Wolf [Sun, 15 Jan 2017 12:52:50 +0000 (13:52 +0100)]
Fix bug in AstNode::mem2reg_as_needed_pass2()
Clifford Wolf [Wed, 11 Jan 2017 13:14:12 +0000 (14:14 +0100)]
Fix $initstate handling bug in yosys-smtbmc
Clifford Wolf [Wed, 11 Jan 2017 09:56:27 +0000 (10:56 +0100)]
Update ABC to hg id
f8cadfe3861f
Clifford Wolf [Sun, 8 Jan 2017 10:57:52 +0000 (11:57 +0100)]
Updated ABC to hg id
38b26a543f1d
Clifford Wolf [Thu, 5 Jan 2017 12:18:58 +0000 (13:18 +0100)]
Fixed handling of local memories in functions
Clifford Wolf [Wed, 4 Jan 2017 17:12:41 +0000 (18:12 +0100)]
Added "check -initdrv"
Clifford Wolf [Wed, 4 Jan 2017 15:03:04 +0000 (16:03 +0100)]
Added handling of local memories and error for local decls in unnamed blocks
Clifford Wolf [Wed, 4 Jan 2017 14:23:48 +0000 (15:23 +0100)]
Implicitly set "yosys-smtbmc --noprogress" on windows
Clifford Wolf [Wed, 4 Jan 2017 11:39:01 +0000 (12:39 +0100)]
Fixed typo in tests/simple/arraycells.v
Clifford Wolf [Wed, 4 Jan 2017 11:03:04 +0000 (12:03 +0100)]
Fixed "yosys-smtbmc --noprogress"
Clifford Wolf [Tue, 3 Jan 2017 16:40:58 +0000 (17:40 +0100)]
Added Verilog $rtoi and $itor support
Clifford Wolf [Mon, 2 Jan 2017 19:02:52 +0000 (20:02 +0100)]
Handle "always 1" like "always -1" in .smtc files
Clifford Wolf [Sun, 1 Jan 2017 21:52:52 +0000 (22:52 +0100)]
Added cell port resizing to hierarchy pass
Clifford Wolf [Sat, 31 Dec 2016 20:52:27 +0000 (21:52 +0100)]
Updated ABC to hg id
55cd83f432c0
Clifford Wolf [Sat, 31 Dec 2016 15:14:42 +0000 (16:14 +0100)]
Bugfix in RTLIL::SigSpec::remove2()
Clifford Wolf [Thu, 29 Dec 2016 11:20:35 +0000 (12:20 +0100)]
Updated ABC to hg id
8c6a635f7a20
Clifford Wolf [Thu, 29 Dec 2016 11:13:29 +0000 (12:13 +0100)]
Improved write_json help message
Clifford Wolf [Mon, 26 Dec 2016 16:52:38 +0000 (17:52 +0100)]
Updated ABC to hg id
f591c081d5e7
Clifford Wolf [Sat, 24 Dec 2016 13:28:39 +0000 (14:28 +0100)]
Merge pull request #284 from azonenberg/master
greenpak4: Support for many new cell types
Andrew Zonenberg [Fri, 23 Dec 2016 20:32:55 +0000 (12:32 -0800)]
Merge pull request #1 from azonenberg-hk/master
Pull changes from HK trip
Andrew Zonenberg [Fri, 23 Dec 2016 13:10:37 +0000 (05:10 -0800)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Fri, 23 Dec 2016 01:06:46 +0000 (02:06 +0100)]
Simplified log_spacer() code
Clifford Wolf [Thu, 22 Dec 2016 22:41:44 +0000 (23:41 +0100)]
Added "yosys -W regex"
Clifford Wolf [Wed, 21 Dec 2016 09:16:47 +0000 (10:16 +0100)]
Added AIGER back-end to automatic back-end detection
Clifford Wolf [Wed, 21 Dec 2016 09:16:10 +0000 (10:16 +0100)]
Updated ABC to hg rev
a4872e22c646
Clifford Wolf [Wed, 21 Dec 2016 08:13:20 +0000 (09:13 +0100)]
Updated ABC to hg rev
8bab2eedbba4
Andrew Zonenberg [Wed, 21 Dec 2016 03:35:29 +0000 (11:35 +0800)]
greenpak4: Added INT pin to GP_SPI
Andrew Zonenberg [Wed, 21 Dec 2016 03:33:32 +0000 (11:33 +0800)]
greenpak4: removed unused MISO pin from GP_SPI
Andrew Zonenberg [Tue, 20 Dec 2016 05:07:49 +0000 (13:07 +0800)]
greenpak4: Removed SPI_BUFFER parameter
Andrew Zonenberg [Tue, 20 Dec 2016 04:34:56 +0000 (12:34 +0800)]
greenpak4: replaced MOSI/MISO with single one-way SDAT pin
Andrew Zonenberg [Tue, 20 Dec 2016 02:30:38 +0000 (10:30 +0800)]
greenpak4: Changed port names on GP_SPI for clarity
Andrew Zonenberg [Tue, 20 Dec 2016 01:58:02 +0000 (09:58 +0800)]
greenpak4: Initial implementation of GP_SPI cell
Andrew Zonenberg [Sat, 17 Dec 2016 04:02:46 +0000 (12:02 +0800)]
Merge https://github.com/cliffordwolf/yosys
Andrew Zonenberg [Sat, 17 Dec 2016 04:01:22 +0000 (12:01 +0800)]
greenpak4: Updated GP_DCMP cell model
Andrew Zonenberg [Fri, 16 Dec 2016 07:14:20 +0000 (15:14 +0800)]
greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.
Clifford Wolf [Thu, 15 Dec 2016 16:49:11 +0000 (17:49 +0100)]
Added "verilog_defines" command
Andrew Zonenberg [Thu, 15 Dec 2016 07:19:35 +0000 (15:19 +0800)]
greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed interface to GP_DCMPMUX
Andrew Zonenberg [Wed, 14 Dec 2016 23:19:08 +0000 (07:19 +0800)]
greenpak4: More fixups of GP_DCMPx cells
Andrew Zonenberg [Wed, 14 Dec 2016 23:17:07 +0000 (07:17 +0800)]
greenpak4: And another typo :(
Andrew Zonenberg [Wed, 14 Dec 2016 23:16:26 +0000 (07:16 +0800)]
greenpak4: Fixed another typo
Andrew Zonenberg [Wed, 14 Dec 2016 23:15:38 +0000 (07:15 +0800)]
greenpak4: Fixed typo
Andrew Zonenberg [Wed, 14 Dec 2016 06:14:45 +0000 (14:14 +0800)]
greenpak4: Cleaned up trailing spaces in cells_sim
Andrew Zonenberg [Wed, 14 Dec 2016 06:14:26 +0000 (14:14 +0800)]
greenpak4: Added GP_DCMPREF / GP_DCMPMUX
Clifford Wolf [Tue, 13 Dec 2016 12:48:09 +0000 (13:48 +0100)]
Bugfix in comment handling
Andrew Zonenberg [Mon, 12 Dec 2016 09:05:06 +0000 (17:05 +0800)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Sun, 11 Dec 2016 12:48:18 +0000 (13:48 +0100)]
Added $anyconst support to AIGER back-end
Clifford Wolf [Sun, 11 Dec 2016 10:03:25 +0000 (11:03 +0100)]
Merge branch 'LSS-USP-unit-test-structure'
Clifford Wolf [Sun, 11 Dec 2016 10:02:56 +0000 (11:02 +0100)]
Some minor CodingReadme changes in unit test section
Clifford Wolf [Sun, 11 Dec 2016 09:58:49 +0000 (10:58 +0100)]
Build hotfix in tests/unit/Makefile
Andrew Zonenberg [Sun, 11 Dec 2016 02:04:00 +0000 (10:04 +0800)]
Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF
rodrigosiqueira [Sat, 10 Dec 2016 20:21:56 +0000 (18:21 -0200)]
Improved unit test structure
Signed-off-by: rodrigosiqueira <rodrigosiqueiramelo@gmail.com>
Signed-off-by: chaws <18oliveira.charles@gmail.com>
* Merged run-all-unitest inside unit-test target
* Fixed Makefile dependencies
* Updated documentation about unit test
Andrew Zonenberg [Sat, 10 Dec 2016 11:58:32 +0000 (19:58 +0800)]
greenpak4: Added support for inferred input/output inverters on latches
Andrew Zonenberg [Sat, 10 Dec 2016 10:46:36 +0000 (18:46 +0800)]
greenpak4: Can now techmap inferred D latches (without set/reset or output inverter)
Andrew Zonenberg [Sat, 10 Dec 2016 05:57:37 +0000 (13:57 +0800)]
greenpak4: Inverted D latch cells now have nQ instead of Q as output port name for consistency
Andrew Zonenberg [Tue, 6 Dec 2016 07:49:06 +0000 (23:49 -0800)]
Added GP_DLATCH and GP_DLATCHI
Andrew Zonenberg [Tue, 6 Dec 2016 05:22:41 +0000 (21:22 -0800)]
Initial implementation of techlib support for GreenPAK latches. Instantiation only, no behavioral inference yet.
Andrew Zonenberg [Tue, 6 Dec 2016 04:10:03 +0000 (20:10 -0800)]
Updated help text for synth_greenpak4
rodrigosiqueira [Sun, 4 Dec 2016 13:35:13 +0000 (11:35 -0200)]
Added explanation about configure and create test
Added explanation about configure unit test environment and how to add new unit tests
rodrigosiqueira [Sun, 4 Dec 2016 13:28:25 +0000 (11:28 -0200)]
Added required structure to implement unit tests
Added modifications inside the main Makefile to refers the unit test Makefile.
Added separated Makefile only for compiling unit tests.
Added simple example of unit test.
Signed-off-by: Charles Oliveira <18oliveira.charles@gmail.com>
Signed-off-by: Pablo Alejandro <pabloabur@usp.br>
Signed-off-by: Rodrigo Siqueira <siqueira@ime.usp.br>
Clifford Wolf [Sat, 3 Dec 2016 12:20:29 +0000 (13:20 +0100)]
Added $assert/$assume support to AIGER back-end
Clifford Wolf [Sat, 3 Dec 2016 11:37:20 +0000 (12:37 +0100)]
Improved yosys-smtbmc default -t/--assume-skipped for --cex and --aig
Clifford Wolf [Thu, 1 Dec 2016 16:45:40 +0000 (17:45 +0100)]
Updated ABV to hg rev
8b555d9e67cf
Clifford Wolf [Thu, 1 Dec 2016 12:42:17 +0000 (13:42 +0100)]
Added examples/aiger/
Clifford Wolf [Thu, 1 Dec 2016 11:57:26 +0000 (12:57 +0100)]
Added "yosys-smtbmc --aig"
Clifford Wolf [Thu, 1 Dec 2016 11:00:00 +0000 (12:00 +0100)]
Added support for partially initialized regs to smt2 back-end
Clifford Wolf [Thu, 1 Dec 2016 10:04:36 +0000 (11:04 +0100)]
Added "write_aiger -zinit -symbols -vmap"
Clifford Wolf [Wed, 30 Nov 2016 20:30:24 +0000 (21:30 +0100)]
Added "write_aiger" command
Clifford Wolf [Wed, 30 Nov 2016 10:25:55 +0000 (11:25 +0100)]
Added "design -reset-vlog"
Clifford Wolf [Tue, 29 Nov 2016 12:30:35 +0000 (13:30 +0100)]
Improved equiv_purge log output
Clifford Wolf [Mon, 28 Nov 2016 14:15:09 +0000 (15:15 +0100)]
Bugfix in smt2 back-end for pure checker modules
Clifford Wolf [Mon, 28 Nov 2016 13:50:17 +0000 (14:50 +0100)]
Added support for macros as include file names
Clifford Wolf [Mon, 28 Nov 2016 13:45:05 +0000 (14:45 +0100)]
Bugfix in "read_verilog -D NAME=VAL" handling
Clifford Wolf [Sun, 27 Nov 2016 11:11:04 +0000 (12:11 +0100)]
Removed shebang line from smtio.py, fixes #279
Clifford Wolf [Wed, 23 Nov 2016 12:49:25 +0000 (13:49 +0100)]
Added wire start_offset and upto handling BLIF back-end
Clifford Wolf [Wed, 23 Nov 2016 12:46:03 +0000 (13:46 +0100)]
Added wire start_offset and upto handling to splitnets cmd
Clifford Wolf [Tue, 22 Nov 2016 20:24:45 +0000 (21:24 +0100)]
Merge pull request #274 from oldtopman/lcurses
Added optional flag for linking curses with readline.
Clifford Wolf [Tue, 22 Nov 2016 20:21:13 +0000 (21:21 +0100)]
Added "yosys-smtbmc --append"
oldtopman [Tue, 22 Nov 2016 06:11:58 +0000 (23:11 -0700)]
Added optional flag for linking curses with readline.
Clifford Wolf [Sat, 19 Nov 2016 22:25:58 +0000 (23:25 +0100)]
Merge pull request #272 from AlexDaniel/master
Markdownify README (№2)
Aleks-Daniel Jakimenko-Aleksejev [Sat, 19 Nov 2016 18:51:50 +0000 (20:51 +0200)]
Keep lines under 80 characters
Recent README changes added some characters to existing lines, which
made them longer than 80 characters. This commit fixes that.
Clifford Wolf [Sat, 19 Nov 2016 17:20:54 +0000 (18:20 +0100)]
Improved ABC default scripts
Aleks-Daniel Jakimenko-Aleksejev [Sat, 19 Nov 2016 16:34:13 +0000 (18:34 +0200)]
Markdownify README even further