yosys.git
5 years agoxilinx_dsp to be sensitive to keep attribute
Eddie Hung [Thu, 15 Aug 2019 19:34:11 +0000 (12:34 -0700)]
xilinx_dsp to be sensitive to keep attribute

5 years agoSimplify
Eddie Hung [Thu, 15 Aug 2019 19:30:46 +0000 (12:30 -0700)]
Simplify

5 years agoMerge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung [Thu, 15 Aug 2019 19:19:51 +0000 (12:19 -0700)]
Merge remote-tracking branch 'origin/master' into xc7dsp

5 years agoMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Eddie Hung [Thu, 15 Aug 2019 19:19:47 +0000 (12:19 -0700)]
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp

5 years agoffH -> ffFJKG
Eddie Hung [Thu, 15 Aug 2019 19:19:34 +0000 (12:19 -0700)]
ffH -> ffFJKG

5 years agoMerge pull request #1297 from YosysHQ/eddie/fix_1284_again
Eddie Hung [Thu, 15 Aug 2019 14:49:02 +0000 (07:49 -0700)]
Merge pull request #1297 from YosysHQ/eddie/fix_1284_again

extract_fa: Un-inverting AND with an inverted input also inverts input to X{,N}OR

5 years agoMerge remote-tracking branch 'origin/master' into eddie/fix_1284_again
Eddie Hung [Thu, 15 Aug 2019 13:48:40 +0000 (06:48 -0700)]
Merge remote-tracking branch 'origin/master' into eddie/fix_1284_again

5 years agoMerge pull request #1275 from YosysHQ/clifford/ids
Clifford Wolf [Thu, 15 Aug 2019 10:03:16 +0000 (12:03 +0200)]
Merge pull request #1275 from YosysHQ/clifford/ids

New ID() macro and now also use it

5 years agoMerge branch 'master' into clifford/ids
Clifford Wolf [Thu, 15 Aug 2019 08:22:59 +0000 (10:22 +0200)]
Merge branch 'master' into clifford/ids

5 years agoMerge pull request #1295 from YosysHQ/eddie/fix_travis
Clifford Wolf [Thu, 15 Aug 2019 08:20:22 +0000 (10:20 +0200)]
Merge pull request #1295 from YosysHQ/eddie/fix_travis

Fix Travis CI

5 years agoAND with an inverted input, causes X{,N}OR output to be inverted too
Eddie Hung [Wed, 14 Aug 2019 23:26:24 +0000 (16:26 -0700)]
AND with an inverted input, causes X{,N}OR output to be inverted too

5 years agoRevert "Only sort leaves on non-ANDNOT/ORNOT cells"
Eddie Hung [Wed, 14 Aug 2019 22:23:25 +0000 (15:23 -0700)]
Revert "Only sort leaves on non-ANDNOT/ORNOT cells"

This reverts commit 5ec5f6dec7d4cdcfd9e1a2cda999886605778400.

5 years agoRevert earliest to gcc-4.8, compile iverilog with default compiler
Eddie Hung [Wed, 14 Aug 2019 19:28:17 +0000 (12:28 -0700)]
Revert earliest to gcc-4.8, compile iverilog with default compiler

5 years agoRevert "Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!"
Eddie Hung [Wed, 14 Aug 2019 19:26:45 +0000 (12:26 -0700)]
Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!"

This reverts commit c82b2fa31f8965be2680c87af6cd9ac5d26ead4d.

5 years agoRemove .0 from clang-8.0
Eddie Hung [Wed, 14 Aug 2019 19:23:15 +0000 (12:23 -0700)]
Remove .0 from clang-8.0

5 years agoBump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!
Eddie Hung [Wed, 14 Aug 2019 19:16:02 +0000 (12:16 -0700)]
Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!

5 years agobionic -> xenial as its on whitelist
Eddie Hung [Wed, 14 Aug 2019 18:52:08 +0000 (11:52 -0700)]
bionic -> xenial as its on whitelist

5 years agoBump gcc from 4.8 to 4.9 as undefined reference
Eddie Hung [Wed, 14 Aug 2019 18:26:32 +0000 (11:26 -0700)]
Bump gcc from 4.8 to 4.9 as undefined reference

... to `__warn_memset_zero_len'.
Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0

5 years agoOnly sort leaves on non-ANDNOT/ORNOT cells
Eddie Hung [Wed, 14 Aug 2019 18:25:56 +0000 (11:25 -0700)]
Only sort leaves on non-ANDNOT/ORNOT cells

5 years agoMerge pull request #1294 from YosysHQ/revert-1288-eddie/fix_1284
Eddie Hung [Wed, 14 Aug 2019 17:42:18 +0000 (10:42 -0700)]
Merge pull request #1294 from YosysHQ/revert-1288-eddie/fix_1284

Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves"

5 years agoRevert "Since $_ANDNOT_ is not symmetric, do not sort leaves"
Eddie Hung [Wed, 14 Aug 2019 17:40:53 +0000 (10:40 -0700)]
Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves"

5 years agoFixes for reverting SigSpec helper functions
Eddie Hung [Wed, 14 Aug 2019 17:22:33 +0000 (10:22 -0700)]
Fixes for reverting SigSpec helper functions

5 years agoPerform C -> PCIN optimisation after pattern matcher
Eddie Hung [Wed, 14 Aug 2019 00:11:35 +0000 (17:11 -0700)]
Perform C -> PCIN optimisation after pattern matcher

5 years agoRevert changes to RTLIL::SigSpec methods
Eddie Hung [Wed, 14 Aug 2019 00:09:28 +0000 (17:09 -0700)]
Revert changes to RTLIL::SigSpec methods

5 years agoOnly swap ports if $mul and not $__mul
Eddie Hung [Tue, 13 Aug 2019 23:52:15 +0000 (16:52 -0700)]
Only swap ports if $mul and not $__mul

5 years agoAdd assign PCOUT = P to DSP48E1
Eddie Hung [Tue, 13 Aug 2019 19:19:26 +0000 (12:19 -0700)]
Add assign PCOUT = P to DSP48E1

5 years agoRename to XilinxDspPass
Eddie Hung [Tue, 13 Aug 2019 17:23:07 +0000 (10:23 -0700)]
Rename to XilinxDspPass

5 years agoAdd DSP_A_MAXWIDTH_PARTIAL, refactor
Eddie Hung [Tue, 13 Aug 2019 17:21:24 +0000 (10:21 -0700)]
Add DSP_A_MAXWIDTH_PARTIAL, refactor

5 years agoMerge pull request #1288 from YosysHQ/eddie/fix_1284
Eddie Hung [Tue, 13 Aug 2019 16:06:11 +0000 (09:06 -0700)]
Merge pull request #1288 from YosysHQ/eddie/fix_1284

Since $_ANDNOT_ is not symmetric, do not sort leaves

5 years agoxilinx: Rework labels for faster Verilator testing
David Shah [Tue, 13 Aug 2019 09:29:42 +0000 (10:29 +0100)]
xilinx: Rework labels for faster Verilator testing

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung [Mon, 12 Aug 2019 18:32:10 +0000 (11:32 -0700)]
Merge remote-tracking branch 'origin/master' into xc7dsp

5 years agoSince $_ANDNOT_ is not symmetric, do not sort leaves
Eddie Hung [Mon, 12 Aug 2019 18:17:15 +0000 (11:17 -0700)]
Since $_ANDNOT_ is not symmetric, do not sort leaves

5 years agoMerge pull request #1152 from 1138-4EB/feat-docker
Serge Bazanski [Mon, 12 Aug 2019 13:09:25 +0000 (15:09 +0200)]
Merge pull request #1152 from 1138-4EB/feat-docker

Dockerfile

5 years agoMerge pull request #1277 from YosysHQ/eddie/fix_1262
Eddie Hung [Mon, 12 Aug 2019 05:10:17 +0000 (22:10 -0700)]
Merge pull request #1277 from YosysHQ/eddie/fix_1262

opt_expr -fine to now trim LSBs of $alu cells too

5 years agoMerge remote-tracking branch 'origin/master' into eddie/fix_1262
Eddie Hung [Mon, 12 Aug 2019 04:13:40 +0000 (21:13 -0700)]
Merge remote-tracking branch 'origin/master' into eddie/fix_1262

5 years agoAdd YOSYS_NO_IDS_REFCNT configuration macro
Clifford Wolf [Sun, 11 Aug 2019 10:23:16 +0000 (12:23 +0200)]
Add YOSYS_NO_IDS_REFCNT configuration macro

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoUse ID() in kernel/*, add simple ID:: hack (to be improved upon later)
Clifford Wolf [Sat, 10 Aug 2019 10:24:16 +0000 (12:24 +0200)]
Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMore improvements and cleanups in IdString subsystem
Clifford Wolf [Sat, 10 Aug 2019 09:41:09 +0000 (11:41 +0200)]
More improvements and cleanups in IdString subsystem

- better use of "inline" keyword
- deprecate "sticky" IDs feature
- improve handling of empty ID
- add move constructor

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoUse ID() macro in all of passes/opt/
Clifford Wolf [Fri, 9 Aug 2019 16:58:14 +0000 (18:58 +0200)]
Use ID() macro in all of passes/opt/

This was obtained by running the following SED command in passes/opt/
and then using "meld foo.cc foo.cc.orig" to manually fix all resulting
compiler errors.

sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' *.cc

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove API of ID() macro
Clifford Wolf [Fri, 9 Aug 2019 16:54:03 +0000 (18:54 +0200)]
Improve API of ID() macro

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder
Eddie Hung [Sat, 10 Aug 2019 21:18:16 +0000 (14:18 -0700)]
Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder

Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"

5 years agoWrong way around
Eddie Hung [Sat, 10 Aug 2019 18:55:00 +0000 (11:55 -0700)]
Wrong way around

5 years agoRevert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
David Shah [Sat, 10 Aug 2019 16:14:48 +0000 (17:14 +0100)]
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"

5 years agocover_list -> cover as per @cliffordwolf
Eddie Hung [Sat, 10 Aug 2019 15:26:41 +0000 (08:26 -0700)]
cover_list -> cover as per @cliffordwolf

5 years agoMerge pull request #1258 from YosysHQ/eddie/cleanup
Clifford Wolf [Sat, 10 Aug 2019 07:52:14 +0000 (09:52 +0200)]
Merge pull request #1258 from YosysHQ/eddie/cleanup

Cleanup a few barnacles across codebase

5 years agoMerge pull request #1261 from YosysHQ/clifford/verific_init
Clifford Wolf [Sat, 10 Aug 2019 07:47:25 +0000 (09:47 +0200)]
Merge pull request #1261 from YosysHQ/clifford/verific_init

Automatically prune init attributes in verific front-end

5 years agoMerge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cell
Clifford Wolf [Sat, 10 Aug 2019 07:47:10 +0000 (09:47 +0200)]
Merge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cell

FIRRTL error on unsupported cell

5 years agoMerge pull request #1270 from YosysHQ/eddie/alu_lcu_doc
Clifford Wolf [Sat, 10 Aug 2019 07:46:46 +0000 (09:46 +0200)]
Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc

Add a few comments to document $alu and $lcu

5 years agoMerge pull request #1272 from mmicko/travis_fix
Clifford Wolf [Sat, 10 Aug 2019 07:45:26 +0000 (09:45 +0200)]
Merge pull request #1272 from mmicko/travis_fix

Propagate parameters for Travis build

5 years agoMerge pull request #1274 from YosysHQ/eddie/fix_1271
Clifford Wolf [Sat, 10 Aug 2019 07:45:06 +0000 (09:45 +0200)]
Merge pull request #1274 from YosysHQ/eddie/fix_1271

Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro

5 years agoMerge pull request #1276 from YosysHQ/clifford/fix1273
Clifford Wolf [Sat, 10 Aug 2019 07:38:22 +0000 (09:38 +0200)]
Merge pull request #1276 from YosysHQ/clifford/fix1273

Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib

5 years agoCheck nusers of DSP output, not whole flop
Eddie Hung [Sat, 10 Aug 2019 00:35:13 +0000 (17:35 -0700)]
Check nusers of DSP output, not whole flop

5 years agoImprove ice40_dsp for non-fully-32-bit adders
Eddie Hung [Sat, 10 Aug 2019 00:23:12 +0000 (17:23 -0700)]
Improve ice40_dsp for non-fully-32-bit adders

5 years agoAdd wreduce to synth_ice40 -dsp as well
Eddie Hung [Sat, 10 Aug 2019 00:05:56 +0000 (17:05 -0700)]
Add wreduce to synth_ice40 -dsp as well

5 years agoAnother filter -> if
Eddie Hung [Fri, 9 Aug 2019 23:23:32 +0000 (16:23 -0700)]
Another filter -> if

5 years agoCleanup
Eddie Hung [Fri, 9 Aug 2019 22:47:40 +0000 (15:47 -0700)]
Cleanup

5 years agoPack partial-product adder DSP48E1 packing
Eddie Hung [Fri, 9 Aug 2019 22:19:33 +0000 (15:19 -0700)]
Pack partial-product adder DSP48E1 packing

5 years agoFix check
Eddie Hung [Fri, 9 Aug 2019 21:27:08 +0000 (14:27 -0700)]
Fix check

5 years agoRevert "Fix typo"
Eddie Hung [Fri, 9 Aug 2019 21:14:28 +0000 (14:14 -0700)]
Revert "Fix typo"

This reverts commit e3c39cc450a0317ad7e8234bb866d55465548c9c.

5 years agoGrammar
Eddie Hung [Fri, 9 Aug 2019 19:43:21 +0000 (12:43 -0700)]
Grammar

5 years agoReformat so it shows up/looks nice when "help $alu" and "help $alu+"
Eddie Hung [Fri, 9 Aug 2019 19:33:39 +0000 (12:33 -0700)]
Reformat so it shows up/looks nice when "help $alu" and "help $alu+"

5 years agoSeparate $alu handling
Eddie Hung [Fri, 9 Aug 2019 19:13:32 +0000 (12:13 -0700)]
Separate $alu handling

5 years agoAdd $alu tests
Eddie Hung [Fri, 9 Aug 2019 19:13:17 +0000 (12:13 -0700)]
Add $alu tests

5 years agoopt_expr -fine to trim LSBs of $alu too
Eddie Hung [Fri, 9 Aug 2019 17:32:12 +0000 (10:32 -0700)]
opt_expr -fine to trim LSBs of $alu too

5 years agoAdd alumacc versions of opt_expr tests
Eddie Hung [Fri, 9 Aug 2019 17:30:53 +0000 (10:30 -0700)]
Add alumacc versions of opt_expr tests

5 years agoAdd new $alu test, remove wreduce
Eddie Hung [Fri, 9 Aug 2019 17:22:06 +0000 (10:22 -0700)]
Add new $alu test, remove wreduce

5 years agoDisable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g all", fixes...
Clifford Wolf [Fri, 9 Aug 2019 17:17:23 +0000 (19:17 +0200)]
Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g all", fixes #1273

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoCleanup some more
Eddie Hung [Fri, 9 Aug 2019 17:13:49 +0000 (10:13 -0700)]
Cleanup some more

5 years agoMerge pull request #1267 from whitequark/proc_prune-fix-1243
whitequark [Fri, 9 Aug 2019 17:10:46 +0000 (17:10 +0000)]
Merge pull request #1267 from whitequark/proc_prune-fix-1243

proc_prune: fix handling of exactly identical assigns

5 years agoSimplify opt_expr tests using equiv_opt
Eddie Hung [Fri, 9 Aug 2019 17:08:17 +0000 (10:08 -0700)]
Simplify opt_expr tests using equiv_opt

5 years agoA bit more on where $lcu comes from
Eddie Hung [Fri, 9 Aug 2019 16:50:47 +0000 (09:50 -0700)]
A bit more on where $lcu comes from

5 years agoAdd more comments
Eddie Hung [Fri, 9 Aug 2019 16:48:17 +0000 (09:48 -0700)]
Add more comments

5 years agoAdd __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro
Eddie Hung [Fri, 9 Aug 2019 16:17:35 +0000 (09:17 -0700)]
Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro

5 years agoABC requires it like this
Miodrag Milanovic [Fri, 9 Aug 2019 06:54:17 +0000 (08:54 +0200)]
ABC requires it like this

5 years agoPropagate parameters for Travis build
Miodrag Milanovic [Fri, 9 Aug 2019 06:06:14 +0000 (08:06 +0200)]
Propagate parameters for Travis build

5 years agoRemove muxY and ffY for now
Eddie Hung [Thu, 8 Aug 2019 23:33:37 +0000 (16:33 -0700)]
Remove muxY and ffY for now

5 years agoRemove signed from ports in +/xilinx/dsp_map.v
Eddie Hung [Thu, 8 Aug 2019 23:33:20 +0000 (16:33 -0700)]
Remove signed from ports in +/xilinx/dsp_map.v

5 years agoRework ice40_dsp to map to SB_MAC16 earlier, and check before packing
Eddie Hung [Thu, 8 Aug 2019 19:56:05 +0000 (12:56 -0700)]
Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing

5 years agoCombine techmap calls
Eddie Hung [Thu, 8 Aug 2019 17:55:48 +0000 (10:55 -0700)]
Combine techmap calls

5 years agoOnly pack registers if {A,B,P}REG = 0, do not pack $dffe
Eddie Hung [Thu, 8 Aug 2019 17:51:19 +0000 (10:51 -0700)]
Only pack registers if {A,B,P}REG = 0, do not pack $dffe

5 years agoMove xilinx_dsp to before alumacc
Eddie Hung [Thu, 8 Aug 2019 17:45:56 +0000 (10:45 -0700)]
Move xilinx_dsp to before alumacc

5 years agoDisable $dffe
Eddie Hung [Thu, 8 Aug 2019 17:44:49 +0000 (10:44 -0700)]
Disable $dffe

5 years agoINMODE is 5 bits
Eddie Hung [Thu, 8 Aug 2019 17:44:35 +0000 (10:44 -0700)]
INMODE is 5 bits

5 years agoFix copy-pasta typo
Eddie Hung [Thu, 8 Aug 2019 17:44:26 +0000 (10:44 -0700)]
Fix copy-pasta typo

5 years agoAdd a few comments to document $alu and $lcu
Eddie Hung [Thu, 8 Aug 2019 17:05:28 +0000 (10:05 -0700)]
Add a few comments to document $alu and $lcu

5 years agoMerge pull request #1264 from YosysHQ/eddie/fix_1254
Eddie Hung [Thu, 8 Aug 2019 14:58:33 +0000 (07:58 -0700)]
Merge pull request #1264 from YosysHQ/eddie/fix_1254

opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)

5 years agoMerge pull request #1266 from YosysHQ/eddie/ice40_full_adder
Eddie Hung [Thu, 8 Aug 2019 14:58:11 +0000 (07:58 -0700)]
Merge pull request #1266 from YosysHQ/eddie/ice40_full_adder

Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER

5 years agoecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx
David Shah [Thu, 8 Aug 2019 14:18:59 +0000 (15:18 +0100)]
ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx

Signed-off-by: David Shah <dave@ds0.me>
5 years agoecp5: Bring up to date with mul2dsp changes
David Shah [Thu, 8 Aug 2019 14:14:09 +0000 (15:14 +0100)]
ecp5: Bring up to date with mul2dsp changes

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
David Shah [Thu, 8 Aug 2019 10:40:09 +0000 (11:40 +0100)]
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp

5 years agoDSP48E1 sim model: add SIMD tests
David Shah [Thu, 8 Aug 2019 10:39:35 +0000 (11:39 +0100)]
DSP48E1 sim model: add SIMD tests

Signed-off-by: David Shah <dave@ds0.me>
5 years agoDSP48E1 model: test CE inputs
David Shah [Thu, 8 Aug 2019 10:32:43 +0000 (11:32 +0100)]
DSP48E1 model: test CE inputs

Signed-off-by: David Shah <dave@ds0.me>
5 years agoDSP48E1 sim model: fix seq tests and add preadder tests
David Shah [Thu, 8 Aug 2019 10:18:37 +0000 (11:18 +0100)]
DSP48E1 sim model: fix seq tests and add preadder tests

Signed-off-by: David Shah <dave@ds0.me>
5 years agoDSP48E1 sim model: seq test working
David Shah [Thu, 8 Aug 2019 09:52:04 +0000 (10:52 +0100)]
DSP48E1 sim model: seq test working

Signed-off-by: David Shah <dave@ds0.me>
5 years agoDSP48E1 sim model: Comb, no pre-adder, mode working
David Shah [Thu, 8 Aug 2019 09:26:40 +0000 (10:26 +0100)]
DSP48E1 sim model: Comb, no pre-adder, mode working

Signed-off-by: David Shah <dave@ds0.me>
5 years ago[wip] sim model testing
David Shah [Thu, 8 Aug 2019 09:05:11 +0000 (10:05 +0100)]
[wip] sim model testing

Signed-off-by: David Shah <dave@ds0.me>
5 years ago[wip] sim model testing
David Shah [Thu, 8 Aug 2019 08:31:34 +0000 (09:31 +0100)]
[wip] sim model testing

Signed-off-by: David Shah <dave@ds0.me>
5 years agoproc_prune: fix handling of exactly identical assigns.
whitequark [Thu, 8 Aug 2019 05:28:01 +0000 (05:28 +0000)]
proc_prune: fix handling of exactly identical assigns.

Before this commit, in a process like:
   process $proc$bug.v:8$3
     assign $foo \bar
     switch \sel
       case 1'1
         assign $foo 1'1
         assign $foo 1'1
       case
         assign $foo 1'0
     end
   end
both of the "assign $foo 1'1" would incorrectly be removed.

Fixes #1243.

5 years agoRemove dump call
Eddie Hung [Thu, 8 Aug 2019 04:36:02 +0000 (21:36 -0700)]
Remove dump call

5 years agoMove tests/various/opt* into tests/opt/
Eddie Hung [Thu, 8 Aug 2019 04:35:48 +0000 (21:35 -0700)]
Move tests/various/opt* into tests/opt/