Clifford Wolf [Tue, 26 May 2015 15:04:37 +0000 (17:04 +0200)]
Added output args to synth_ice40
Clifford Wolf [Sun, 24 May 2015 06:03:21 +0000 (08:03 +0200)]
Improvements in BLIF front-end
Clifford Wolf [Sat, 23 May 2015 08:17:03 +0000 (10:17 +0200)]
improved ice40 SB_IO sim model
Clifford Wolf [Sat, 23 May 2015 08:14:53 +0000 (10:14 +0200)]
Improved "flatten" handlings of inout ports
Clifford Wolf [Sat, 23 May 2015 07:45:48 +0000 (09:45 +0200)]
Added simple $dlatch support to opt_rmdff
Clifford Wolf [Sat, 23 May 2015 07:30:24 +0000 (09:30 +0200)]
Added ice40 SB_IO sim model
Clifford Wolf [Fri, 22 May 2015 06:23:03 +0000 (08:23 +0200)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Fri, 22 May 2015 06:20:29 +0000 (08:20 +0200)]
preserve used $-wires with init attribute in opt_clean
Clifford Wolf [Wed, 20 May 2015 11:55:50 +0000 (13:55 +0200)]
Some fixes for $mem in verilog back-end
Clifford Wolf [Mon, 18 May 2015 09:15:49 +0000 (11:15 +0200)]
bugfix in blif front-end
Clifford Wolf [Sun, 17 May 2015 17:54:00 +0000 (19:54 +0200)]
added vloghtb test_febe.sh
Clifford Wolf [Sun, 17 May 2015 16:58:24 +0000 (18:58 +0200)]
Improved .latch support in BLIF front-end
Clifford Wolf [Sun, 17 May 2015 13:25:03 +0000 (15:25 +0200)]
Added read_blif command
Clifford Wolf [Sun, 17 May 2015 13:10:37 +0000 (15:10 +0200)]
Generalized blifparse API
Clifford Wolf [Sun, 17 May 2015 12:44:28 +0000 (14:44 +0200)]
abc/blifparse files reorganization
Clifford Wolf [Sun, 17 May 2015 06:19:52 +0000 (08:19 +0200)]
Verific build fixes
Clifford Wolf [Wed, 13 May 2015 04:45:12 +0000 (06:45 +0200)]
Added .barbuf support to abc BLIF parser
Clifford Wolf [Mon, 11 May 2015 19:46:35 +0000 (21:46 +0200)]
changed file() to open() in python scripts
Clifford Wolf [Mon, 11 May 2015 19:38:06 +0000 (21:38 +0200)]
Merge pull request #63 from wluker/verilog-backend-mem
Fixed bug in $mem cell verilog code generation.
luke whittlesey [Mon, 11 May 2015 18:05:18 +0000 (14:05 -0400)]
Fixed bug in $mem cell verilog code generation.
Clifford Wolf [Sun, 10 May 2015 19:38:41 +0000 (21:38 +0200)]
Disabled broken $mem support in verilog backend
Clifford Wolf [Sun, 10 May 2015 19:23:59 +0000 (21:23 +0200)]
Merge pull request #62 from wluker/verilog-backend-mem
Added support for $mem cells in the verilog backend.
luke whittlesey [Sun, 10 May 2015 15:33:24 +0000 (11:33 -0400)]
Made changes recommended by Clifford Wolf ...
Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used
dict<> instead of std::map, and used RTLIL::SigSpec instead of
std::vector.
luke whittlesey [Fri, 8 May 2015 19:29:51 +0000 (15:29 -0400)]
Verilog backend for $mem cells should now be able to handle different
write-enable bits and RD_TRANSPARENT parameter settings.
luke whittlesey [Thu, 7 May 2015 17:03:09 +0000 (13:03 -0400)]
Added support for $mem cells in the verilog backend.
Clifford Wolf [Wed, 29 Apr 2015 17:55:32 +0000 (19:55 +0200)]
Fixed memory_unpack for initialized memories
Clifford Wolf [Wed, 29 Apr 2015 05:44:57 +0000 (07:44 +0200)]
Preserve important attributes in splitnets
Clifford Wolf [Wed, 29 Apr 2015 05:28:15 +0000 (07:28 +0200)]
Added $eq/$neq -> $logic_not/$reduce_bool optimization
Clifford Wolf [Mon, 27 Apr 2015 09:36:13 +0000 (11:36 +0200)]
ice40_opt bugfix
Clifford Wolf [Mon, 27 Apr 2015 08:27:50 +0000 (10:27 +0200)]
iCE40: SB_CARRY const fold -> unmap SB_LUT
Clifford Wolf [Mon, 27 Apr 2015 08:16:07 +0000 (10:16 +0200)]
Added simplemap $lut support
Clifford Wolf [Mon, 27 Apr 2015 06:38:14 +0000 (08:38 +0200)]
Added iCE40 const folding support for SB_CARRY
Clifford Wolf [Sun, 26 Apr 2015 06:39:31 +0000 (08:39 +0200)]
Initialization support for all iCE40 bram modes
Clifford Wolf [Sat, 25 Apr 2015 18:44:51 +0000 (20:44 +0200)]
initialized iCE40 brams (mode 0)
Clifford Wolf [Sat, 25 Apr 2015 18:01:37 +0000 (20:01 +0200)]
improved iCE40 SB_RAM40_4K simulation model
Clifford Wolf [Sat, 25 Apr 2015 16:07:13 +0000 (18:07 +0200)]
Updated ABC to hg rev
779de2de1481
Clifford Wolf [Sat, 25 Apr 2015 16:04:57 +0000 (18:04 +0200)]
More iCE40 bram improvements
Clifford Wolf [Fri, 24 Apr 2015 20:04:05 +0000 (22:04 +0200)]
Improved attributes API and handling of "src" attributes
Clifford Wolf [Fri, 24 Apr 2015 13:38:11 +0000 (15:38 +0200)]
iCE40 bram progress
Clifford Wolf [Fri, 24 Apr 2015 06:32:07 +0000 (08:32 +0200)]
iCE40 bram tests and fixes
Clifford Wolf [Thu, 23 Apr 2015 22:06:50 +0000 (00:06 +0200)]
Added ice40 bram support
Clifford Wolf [Wed, 22 Apr 2015 04:40:23 +0000 (06:40 +0200)]
Fixed memory_share for unconditional write with part select to memory
Clifford Wolf [Sun, 19 Apr 2015 19:37:40 +0000 (21:37 +0200)]
iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models
Clifford Wolf [Sun, 19 Apr 2015 19:30:46 +0000 (21:30 +0200)]
Verilog front-end: define `BLACKBOX in -lib mode
Clifford Wolf [Sat, 18 Apr 2015 07:41:31 +0000 (09:41 +0200)]
added sync reset to ice40 test_ffs.sh
Clifford Wolf [Sat, 18 Apr 2015 07:33:34 +0000 (09:33 +0200)]
Added ice40 test_arith
Clifford Wolf [Sat, 18 Apr 2015 07:33:08 +0000 (09:33 +0200)]
Added ice40 SB_CARRY support
Clifford Wolf [Sat, 18 Apr 2015 07:29:03 +0000 (09:29 +0200)]
don't consider blackbox modules in "sat" command
Clifford Wolf [Sat, 18 Apr 2015 06:04:31 +0000 (08:04 +0200)]
Improved handling of init values in opt_rmdff
based on a patch by Mingyu Gao, user gaomy3832 on github
Clifford Wolf [Fri, 17 Apr 2015 19:35:59 +0000 (21:35 +0200)]
Bugfix for $_DFF_?_ in "
dff2dffe -direct-match"
Clifford Wolf [Fri, 17 Apr 2015 09:54:25 +0000 (11:54 +0200)]
Added mapping of synchronous set/reset to iCE40 flow
Clifford Wolf [Thu, 16 Apr 2015 16:23:43 +0000 (18:23 +0200)]
Improved "maccmap" help message
Clifford Wolf [Thu, 16 Apr 2015 16:13:41 +0000 (18:13 +0200)]
A "#" does start a comment, not a label.
Clifford Wolf [Thu, 16 Apr 2015 10:09:14 +0000 (12:09 +0200)]
Changed ice40 ICESTORM_CARRYCONST port name
Clifford Wolf [Thu, 16 Apr 2015 09:47:59 +0000 (11:47 +0200)]
Fixed "
dff2dffe -direct-match"
Clifford Wolf [Thu, 16 Apr 2015 09:31:15 +0000 (11:31 +0200)]
Added simple ice40 dff tests
Clifford Wolf [Thu, 16 Apr 2015 09:30:56 +0000 (11:30 +0200)]
improved ice40 dff cell mapping
Clifford Wolf [Thu, 16 Apr 2015 09:30:17 +0000 (11:30 +0200)]
Added "
dff2dffe -direct-match"
Clifford Wolf [Tue, 14 Apr 2015 11:45:15 +0000 (13:45 +0200)]
use "hierarchy -auto-top" in synth_ice40
Clifford Wolf [Tue, 14 Apr 2015 11:44:43 +0000 (13:44 +0200)]
more cells in ice40 cell library
Clifford Wolf [Mon, 13 Apr 2015 17:28:12 +0000 (19:28 +0200)]
Added "splice -wires"
Clifford Wolf [Mon, 13 Apr 2015 17:27:49 +0000 (19:27 +0200)]
Added handling of bool-output cells to "wreduce"
Clifford Wolf [Thu, 9 Apr 2015 15:12:12 +0000 (17:12 +0200)]
Improved xilinx "bram1" test
Clifford Wolf [Thu, 9 Apr 2015 14:08:54 +0000 (16:08 +0200)]
Added memory_bram "make_outreg" feature
Clifford Wolf [Thu, 9 Apr 2015 13:37:54 +0000 (15:37 +0200)]
Added back-end auto-detect for .edif and .json
Clifford Wolf [Thu, 9 Apr 2015 13:12:26 +0000 (15:12 +0200)]
Minor fixes in handling of "init" attribute
Clifford Wolf [Thu, 9 Apr 2015 11:37:07 +0000 (13:37 +0200)]
Xilinx DRAMS: RAM64X1D, RAM128X1D
Clifford Wolf [Thu, 9 Apr 2015 11:20:19 +0000 (13:20 +0200)]
Fixed const2big performance bug
Clifford Wolf [Thu, 9 Apr 2015 10:02:26 +0000 (12:02 +0200)]
techmap code cleanup
Clifford Wolf [Thu, 9 Apr 2015 06:17:14 +0000 (08:17 +0200)]
Towards DRAM support in Xilinx flow
Clifford Wolf [Wed, 8 Apr 2015 10:14:34 +0000 (12:14 +0200)]
Added support for "file names with blanks"
Clifford Wolf [Wed, 8 Apr 2015 10:13:53 +0000 (12:13 +0200)]
Removed "techmap -share_map" (use "-map +/filename" instead)
Clifford Wolf [Tue, 7 Apr 2015 20:22:09 +0000 (22:22 +0200)]
Added %M and %C select operators
Clifford Wolf [Tue, 7 Apr 2015 18:27:10 +0000 (20:27 +0200)]
Added "pmuxtree" command
Clifford Wolf [Tue, 7 Apr 2015 17:21:30 +0000 (19:21 +0200)]
Added "chparam -list"
Clifford Wolf [Tue, 7 Apr 2015 16:03:27 +0000 (18:03 +0200)]
Added decoder generation to "muxcover"
Clifford Wolf [Tue, 7 Apr 2015 15:23:30 +0000 (17:23 +0200)]
Added hashlib support for std::tuple<>
Clifford Wolf [Tue, 7 Apr 2015 13:42:25 +0000 (15:42 +0200)]
Added "muxcover" command
Clifford Wolf [Tue, 7 Apr 2015 13:07:01 +0000 (15:07 +0200)]
Added pool<K>::pop()
Clifford Wolf [Tue, 7 Apr 2015 05:43:01 +0000 (07:43 +0200)]
typo fix
Clifford Wolf [Tue, 7 Apr 2015 05:30:14 +0000 (07:30 +0200)]
Added "chparam" command
Clifford Wolf [Mon, 6 Apr 2015 15:07:10 +0000 (17:07 +0200)]
Added support for initialized xilinx brams
Clifford Wolf [Mon, 6 Apr 2015 15:06:15 +0000 (17:06 +0200)]
Added support for initialized brams
Clifford Wolf [Mon, 6 Apr 2015 11:03:37 +0000 (13:03 +0200)]
Added Xilinx test case for initialized brams
Clifford Wolf [Mon, 6 Apr 2015 06:44:30 +0000 (08:44 +0200)]
Added Xilinx bram black-box modules
Clifford Wolf [Sun, 5 Apr 2015 23:49:58 +0000 (01:49 +0200)]
Added "port_directions" to write_json output
Clifford Wolf [Sun, 5 Apr 2015 16:04:19 +0000 (18:04 +0200)]
Avoid parameter values with size 0 ($mem cells)
Clifford Wolf [Sun, 5 Apr 2015 15:26:53 +0000 (17:26 +0200)]
make all vector-size related integer params in $mem sim model signed
this fixes iverilog crashes such as the following:
warning: verinum::as_long() truncated 32 bits to 31, returns
2147483647
draw_net_input.c:711: Error: malloc() ran out of memory.
Clifford Wolf [Sun, 5 Apr 2015 07:45:14 +0000 (09:45 +0200)]
Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types
Clifford Wolf [Sat, 4 Apr 2015 17:00:15 +0000 (19:00 +0200)]
Added "dffinit", Support for initialized Xilinx DFF
Clifford Wolf [Sat, 4 Apr 2015 16:06:52 +0000 (18:06 +0200)]
Added "init" attribute support to verilog backend
Clifford Wolf [Sat, 4 Apr 2015 13:13:35 +0000 (15:13 +0200)]
appnote 012 fix
Clifford Wolf [Sat, 4 Apr 2015 11:48:13 +0000 (13:48 +0200)]
Appnote 012
Clifford Wolf [Sat, 4 Apr 2015 09:47:59 +0000 (11:47 +0200)]
Updated ABC to
51705b168d7a
Clifford Wolf [Sat, 4 Apr 2015 07:35:21 +0000 (09:35 +0200)]
Merge pull request #55 from ahmedirfan1983/master
added appnote and impr in btor
Ahmed Irfan [Fri, 3 Apr 2015 15:11:45 +0000 (17:11 +0200)]
Update README
corrected url
Ahmed Irfan [Fri, 3 Apr 2015 14:45:54 +0000 (16:45 +0200)]
Delete btor.ys
.ys script not needed
Ahmed Irfan [Fri, 3 Apr 2015 14:45:14 +0000 (16:45 +0200)]
Update README
pmux cell is implemented
Ahmed Irfan [Fri, 3 Apr 2015 14:41:50 +0000 (16:41 +0200)]
separated memory next from write cell
Ahmed Irfan [Fri, 3 Apr 2015 14:38:07 +0000 (16:38 +0200)]
Merge branch 'master' of https://github.com/cliffordwolf/yosys