Yehowshua [Tue, 9 Jun 2020 23:18:49 +0000 (19:18 -0400)]
Re: [libre-riscv-dev] AMD ISAs
bugzilla-daemon [Tue, 9 Jun 2020 23:17:05 +0000 (23:17 +0000)]
[libre-riscv-dev] [Bug 372] create cycle-accurate JIT-compiler-based processor simulator
Yehowshua [Tue, 9 Jun 2020 23:16:44 +0000 (19:16 -0400)]
Re: [libre-riscv-dev] AMD ISAs
Yehowshua [Tue, 9 Jun 2020 23:15:36 +0000 (19:15 -0400)]
[libre-riscv-dev] AMD ISAs
bugzilla-daemon [Tue, 9 Jun 2020 22:53:28 +0000 (22:53 +0000)]
[libre-riscv-dev] [Bug 372] create cycle-accurate JIT-compiler-based processor simulator
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 22:48:24 +0000 (23:48 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 09jun2020
bugzilla-daemon [Tue, 9 Jun 2020 22:46:54 +0000 (22:46 +0000)]
[libre-riscv-dev] [Bug 372] create cycle-accurate JIT-compiler-based processor simulator
bugzilla-daemon [Tue, 9 Jun 2020 22:44:18 +0000 (22:44 +0000)]
[libre-riscv-dev] [Bug 372] create cycle-accurate JIT-compiler-based processor simulator
bugzilla-daemon [Tue, 9 Jun 2020 22:43:36 +0000 (22:43 +0000)]
[libre-riscv-dev] [Bug 372] New: create cycle-accurate JIT-compiler-based processor simulator
bugzilla-daemon [Tue, 9 Jun 2020 22:08:49 +0000 (22:08 +0000)]
[libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 22:07:01 +0000 (23:07 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 09jun2020
Hendrik Boom [Tue, 9 Jun 2020 22:01:34 +0000 (18:01 -0400)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
Alain D D Williams [Tue, 9 Jun 2020 21:49:36 +0000 (22:49 +0100)]
[libre-riscv-dev] daily kan-ban update 09jun2020
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 21:48:20 +0000 (22:48 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 09jun2020
Cole Poirier [Tue, 9 Jun 2020 21:01:14 +0000 (14:01 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 09jun2020
bugzilla-daemon [Tue, 9 Jun 2020 20:59:35 +0000 (20:59 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 20:17:12 +0000 (21:17 +0100)]
Re: [libre-riscv-dev] wishbone does not have byte-enable (but it does have user-tags)
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 20:15:39 +0000 (21:15 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 09jun2020
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 20:13:01 +0000 (21:13 +0100)]
Re: [libre-riscv-dev] mortbopet/Ripes: A graphical processor simulator and assembly editor for the RISC-V ISA
Cole Poirier [Tue, 9 Jun 2020 19:35:35 +0000 (12:35 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 09jun2020
bugzilla-daemon [Tue, 9 Jun 2020 19:32:32 +0000 (19:32 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Cole Poirier [Tue, 9 Jun 2020 19:25:37 +0000 (12:25 -0700)]
[libre-riscv-dev] mortbopet/Ripes: A graphical processor simulator and assembly editor for the RISC-V ISA
Cole Poirier [Tue, 9 Jun 2020 19:18:15 +0000 (12:18 -0700)]
Re: [libre-riscv-dev] wishbone does not have byte-enable (but it does have user-tags)
Cole Poirier [Tue, 9 Jun 2020 19:01:35 +0000 (12:01 -0700)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 17:44:23 +0000 (18:44 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 09jun2020
Jacob Lifshay [Tue, 9 Jun 2020 17:21:37 +0000 (10:21 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 09jun2020
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 17:10:30 +0000 (18:10 +0100)]
[libre-riscv-dev] wishbone does not have byte-enable (but it does have user-tags)
bugzilla-daemon [Tue, 9 Jun 2020 17:04:18 +0000 (17:04 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 16:20:56 +0000 (17:20 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 09jun2020
Tobias Platen [Tue, 9 Jun 2020 13:23:07 +0000 (15:23 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 09jun2020
bugzilla-daemon [Tue, 9 Jun 2020 13:17:17 +0000 (13:17 +0000)]
[libre-riscv-dev] [Bug 371] code removed by commit
12297566322355ce5fed2e2a5460bea54f69e79e
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 13:11:48 +0000 (14:11 +0100)]
[libre-riscv-dev] daily kan-ban update 09jun2020
bugzilla-daemon [Tue, 9 Jun 2020 13:08:22 +0000 (13:08 +0000)]
[libre-riscv-dev] [Bug 371] code removed by commit
12297566322355ce5fed2e2a5460bea54f69e79e
bugzilla-daemon [Tue, 9 Jun 2020 13:07:27 +0000 (13:07 +0000)]
[libre-riscv-dev] [Bug 371] code removed by commit
12297566322355ce5fed2e2a5460bea54f69e79e
bugzilla-daemon [Tue, 9 Jun 2020 13:06:13 +0000 (13:06 +0000)]
[libre-riscv-dev] [Bug 371] code removed by commit
12297566322355ce5fed2e2a5460bea54f69e79e
bugzilla-daemon [Tue, 9 Jun 2020 12:49:10 +0000 (12:49 +0000)]
[libre-riscv-dev] [Bug 371] code removed by commit
12297566322355ce5fed2e2a5460bea54f69e79e
bugzilla-daemon [Tue, 9 Jun 2020 12:48:25 +0000 (12:48 +0000)]
[libre-riscv-dev] [Bug 371] New: code removed by commit
12297566322355ce5fed2e2a5460bea54f69e79e
bugzilla-daemon [Tue, 9 Jun 2020 12:43:36 +0000 (12:43 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Tue, 9 Jun 2020 12:36:44 +0000 (12:36 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 10:34:20 +0000 (11:34 +0100)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
Cole Poirier [Tue, 9 Jun 2020 01:17:17 +0000 (18:17 -0700)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
bugzilla-daemon [Mon, 8 Jun 2020 22:51:25 +0000 (22:51 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Cole Poirier [Mon, 8 Jun 2020 22:29:17 +0000 (15:29 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 08jun2020
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 22:18:26 +0000 (23:18 +0100)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 22:17:04 +0000 (23:17 +0100)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 22:13:07 +0000 (23:13 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08jun2020
bugzilla-daemon [Mon, 8 Jun 2020 22:03:38 +0000 (22:03 +0000)]
[libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side
Michael Nolan [Mon, 8 Jun 2020 21:19:29 +0000 (17:19 -0400)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Cole Poirier [Mon, 8 Jun 2020 21:17:28 +0000 (14:17 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 08jun2020
bugzilla-daemon [Mon, 8 Jun 2020 21:03:36 +0000 (21:03 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 20:46:26 +0000 (21:46 +0100)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 20:38:10 +0000 (21:38 +0100)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 20:31:28 +0000 (21:31 +0100)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Yehowshua [Mon, 8 Jun 2020 20:12:13 +0000 (16:12 -0400)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Michael Nolan [Mon, 8 Jun 2020 20:11:01 +0000 (16:11 -0400)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 20:08:54 +0000 (21:08 +0100)]
[libre-riscv-dev] daily kan-ban update 08jun2020
Yehowshua [Mon, 8 Jun 2020 19:14:05 +0000 (15:14 -0400)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Yehowshua [Mon, 8 Jun 2020 19:09:23 +0000 (15:09 -0400)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Yehowshua [Mon, 8 Jun 2020 19:05:17 +0000 (15:05 -0400)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 19:02:37 +0000 (20:02 +0100)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Sanjay Menon [Mon, 8 Jun 2020 19:01:07 +0000 (00:31 +0530)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Yehowshua [Mon, 8 Jun 2020 18:58:02 +0000 (14:58 -0400)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 18:55:41 +0000 (19:55 +0100)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
bugzilla-daemon [Mon, 8 Jun 2020 18:52:51 +0000 (18:52 +0000)]
[libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side
bugzilla-daemon [Mon, 8 Jun 2020 18:37:44 +0000 (18:37 +0000)]
[libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline
Yehowshua [Mon, 8 Jun 2020 18:46:36 +0000 (14:46 -0400)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
bugzilla-daemon [Mon, 8 Jun 2020 18:37:44 +0000 (18:37 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 8 Jun 2020 18:37:44 +0000 (18:37 +0000)]
[libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py
bugzilla-daemon [Mon, 8 Jun 2020 18:34:03 +0000 (18:34 +0000)]
[libre-riscv-dev] [Bug 370] New: need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side
bugzilla-daemon [Mon, 8 Jun 2020 18:31:31 +0000 (18:31 +0000)]
[libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 18:24:12 +0000 (19:24 +0100)]
Re: [libre-riscv-dev] Understanding the LibreSOC core
Sanjay Menon [Mon, 8 Jun 2020 18:03:22 +0000 (23:33 +0530)]
[libre-riscv-dev] Understanding the LibreSOC core
bugzilla-daemon [Mon, 8 Jun 2020 18:00:05 +0000 (18:00 +0000)]
[libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
bugzilla-daemon [Mon, 8 Jun 2020 17:57:53 +0000 (17:57 +0000)]
[libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py
bugzilla-daemon [Mon, 8 Jun 2020 17:48:46 +0000 (17:48 +0000)]
[libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 15:27:46 +0000 (16:27 +0100)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
bugzilla-daemon [Mon, 8 Jun 2020 14:28:11 +0000 (14:28 +0000)]
[libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py
Lauri Kasanen [Mon, 8 Jun 2020 14:15:07 +0000 (17:15 +0300)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
bugzilla-daemon [Mon, 8 Jun 2020 14:10:44 +0000 (14:10 +0000)]
[libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py
Hendrik Boom [Mon, 8 Jun 2020 13:55:54 +0000 (09:55 -0400)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
bugzilla-daemon [Mon, 8 Jun 2020 13:50:54 +0000 (13:50 +0000)]
[libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py
bugzilla-daemon [Mon, 8 Jun 2020 13:42:15 +0000 (13:42 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Mon, 8 Jun 2020 12:59:34 +0000 (12:59 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Staf Verhaegen [Mon, 8 Jun 2020 12:37:29 +0000 (14:37 +0200)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 11:13:48 +0000 (12:13 +0100)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
Staf Verhaegen [Mon, 8 Jun 2020 10:17:05 +0000 (12:17 +0200)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 09:40:27 +0000 (10:40 +0100)]
Re: [libre-riscv-dev] Using formal to expose bugs in scoreboard
bugzilla-daemon [Mon, 8 Jun 2020 09:13:22 +0000 (09:13 +0000)]
[libre-riscv-dev] [Bug 81] implement 6600-style "precise" out-of-order scoreboard
bugzilla-daemon [Mon, 8 Jun 2020 09:13:22 +0000 (09:13 +0000)]
[libre-riscv-dev] [Bug 197] Formal correctness proof needed of the 6600-style Out-of-Order execution engine
Yehowshua [Mon, 8 Jun 2020 03:18:58 +0000 (23:18 -0400)]
Re: [libre-riscv-dev] Using formal to expose bugs in scoreboard
Yehowshua [Mon, 8 Jun 2020 03:11:36 +0000 (23:11 -0400)]
[libre-riscv-dev] Using formal to expose bugs in scoreboard
bugzilla-daemon [Mon, 8 Jun 2020 01:28:51 +0000 (01:28 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 8 Jun 2020 01:20:16 +0000 (01:20 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 8 Jun 2020 01:09:26 +0000 (01:09 +0000)]
[libre-riscv-dev] [Bug 369] New: missing XER SO/OV/32 check in test_pipe_caller.py
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 00:35:43 +0000 (01:35 +0100)]
Re: [libre-riscv-dev] "simple" core
Jacob Lifshay [Mon, 8 Jun 2020 00:29:21 +0000 (17:29 -0700)]
Re: [libre-riscv-dev] Request for input and technical expertise for Systèmes Libres Amazon Alexa IOT Pitch 10-JUN-2020
Yehowshua [Mon, 8 Jun 2020 00:27:22 +0000 (20:27 -0400)]
Re: [libre-riscv-dev] "simple" core
Cole Poirier [Mon, 8 Jun 2020 00:10:30 +0000 (17:10 -0700)]
Re: [libre-riscv-dev] "simple" core
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 00:06:19 +0000 (01:06 +0100)]
Re: [libre-riscv-dev] "simple" core
Cole Poirier [Mon, 8 Jun 2020 00:01:33 +0000 (17:01 -0700)]
Re: [libre-riscv-dev] "simple" core
projects / libre-riscv-dev.git / log