Eliminate several cases of multiplication in arguments to calloc

In commit 32f2fd1c5d6088692551c80352b7d6fa35b0cd09, several calls to
_mesa_calloc(x) were replaced with calls to calloc(1, x). This is strictly
equivalent to what the code was doing previously.

But for cases where "x" involves multiplication, now that we are explicitly
using the two-argument calloc, we can do one step better and replace:

calloc(1, A * B);

with:

calloc(A, B);

The advantage of the latter is that calloc will detect any overflow that would
have resulted from the multiplication and will fail the allocation, (whereas
the former would return a small allocation). So this fix can change
potentially exploitable buffer overruns into segmentation faults.

Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Report progress from opt_copy_propagation_elements().

It's been altering the tree and reporting "false" since January 2011.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Skip rewriting instructions in opt_cpe when unnecessary.

Previously, opt_copy_propagation_elements would always rewrite the
instruction stream, even if was the same thing as before.  In order to
report progress correctly, we'll need to bail if the suggested
replacement is identical (or equivalent) to the original code.

This also introduced unnecessary noop swizzles, as far as I can tell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Initialize source_chan in opt_copy_propagation_elements.

Previously, if chans < 4, we passed uninitialized stack garbage to the
ir_swizzle constructor for the excess components.  Thankfully, it
ignores that data, as it's unnecessary, so no harm actually comes of it.

However, it's obviously better to initialize it.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Handle ir_triop_csel in emit_bool_to_cond_code().

ir_triop_csel can return a boolean expression, so we need to handle it
here; we simply forgot when we added it.

Fixes Piglit's EXT_shader_integer_mix/{vs,fs}-mix-if-bool.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org

i965: Move curb_read_length/total_scratch to brw_stage_prog_data.

All shader stages have these fields, so it makes sense to store them in
the common base structure, rather than duplicating them in each.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

build: Rename md5 to checksums as part of .PHONY target

In commit 46d03d37bf3a75e86f9f8ab56c6a939d04f23383 I renamed a Makefile target
from md5 to checksums, (as we switched from MD5 checksums to SHA-256
checksums, so the more general name is more future proof).

But that commit missed one mention of "md5" as a dependency of the .PHONY
target. Rename that here as well.

glsl: fix assertion which fails for unsigned array indices.

According to the GLSL 1.40 spec, section 5.7 Structure and Array Operations:

"Array elements are accessed using an expression whose type is int or uint."

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

i965/copy_image: Divide the x offsets by block width when using the blitter

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82804
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/copy_image: Use the correct block dimension

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82804
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

meta/copy_image: Use the correct texture level when creating views

Previously, we were accidentally assuming that the level of both textures
was 0.  Now we actually use the correct level in our hacked texture view.
This doesn't 100% fix the meta path because the texture type is getting
lost somewhere in the pipeline.  However, it actually copies to/from the
correct layer now.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82804
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/copy_image: Use the correct texture level

Previously, we were using the source images level for both source and
destination.  Also, we weren't taking the MinLevel from a potential texture
view into account.  This commit fixes both problems.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82804
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

gallivm: Fix build against LLVM SVN >= r216982

Only MCJIT is available anymore.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>

r600g: fix alpha-test with HyperZ enabled, fixing L4D2 tree corruption

*_update_db_shader_control depends on the alpha test state. The problem was
it was in a block which is only entered if the pixel shader is changed.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74863

Cc: mesa-stable@lists.freedesktop.org
Tested-by: Benjamin Bellec <b.bellec@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

r600g,radeonsi: Preserve existing buffer flags

The default case was accidentally clearing RADEON_FLAG_CPU_ACCESS from the
previous fall-through cases.

Reported-by: Mathias Fröhlich <Mathias.Froehlich@gmx.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

main: Don't leak temporary texture rows

Reviewed-by: Dave Airlie <airlied@gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

r300g: pointless assignment of info.indexed

Did this code mean to do something else, you tell me!

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

omx/h264: remove stray semicolon after if

Coverity reported this, looks wrong to me.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

vdpau: unlock the mutex on error paths in attribute setting.

Coverity pointed out we never dropped the lock here, so fix
it by using a common exit path.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

u_primconvert: Use u_upload_mgr for our little IB allocations.

tex-miplevel-selection was hammering my memory manager with primconverts
on individual quads.  This gets all those converted IBs packed into larger
IBs.

Reviewed-by: Rob Clark <robclark@freedesktop.org>

u_primconvert: Shut up compiler warning.

gcc isn't detecting that src is set before used, since both are under if
(info->indexed).

Reviewed-by: Rob Clark <robclark@freedesktop.org>

gbm: Fix gallium build when X11 is in a non-system directory

pipe-loader.h will include Xlib.h when HAVE_PIPE_LOADER_XLIB is set in the
build.

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

vc4: Handle a couple of the transfer map flags.

This is part of fixing extremely long runtimes on some piglit tests that
involve streaming vertex reuploads due to format conversions, and will
similarly be important for X performance, which relies on these flags.

meta: Make MESA_META_DRAW_BUFFERS restore properly

A meta begin/end pair with MESA_META_DRAW_BUFFERS will change visible GL
state.  We recreate the draw buffer enums from the buffer bitfield, which
changes GL_BACK to GL_BACK_LEFT (and GL_FRONT to GL_FRONT_LEFT).

This commit modifes the save/restore logic to instead copy the buffer enums
from the gl_framebuffer and then set them on restore using
_mesa_drawbuffers().

It's not clear how this breaks the benchmark in 82796, but fixing meta to not
leak the state change fixes the regression.

No piglit regressions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=82796
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Cc: mesa-stable@lists.freedesktop.org

Revert "mesa: fix make tarballs"

This reverts commit 0fbb9a599df898d4e1166d6d6f00cb34a0524bea.

Rather than adding hacks around the issue drop the sources from the
final tarball, and re-add them back with 'make dist'. This fixes a
problem when running parallel 'make install' fails as it recreates
sources and triggers partial recompilation.

Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83355
Reported-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Tested-by: Kai Wasserbäch <kai@dev.carbon-project.org>

mesa/program_cache: calloc the correct size for the cache.

Coverity reported this, and I think this is the right solution,
since cache->items is struct cache_item ** not struct cache_item *,
we also realloc it using struct cache_item * at some point.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radeonsi: Compile dummy pixel shader on demand

It's never used under normal circumstances.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

u_blitter: Create all shaders on demand

Not all of these are used in every context, so this can make a
significant difference for short-lived contexts such as in piglit tests.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

r600g,radeonsi: Inform the kernel if a BO will likely be accessed by the CPU

This allows the kernel to prevent such BOs from ever being stored in the
CPU inaccessible part of VRAM.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl: free uniform_map on failure path.

If we fails in reserve_explicit_locations, we leak uniform_map.

Reported-by: coverity scanner.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

main/cs: Add gl_context::ComputeProgram

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

mesa: Convert NewDriverState to 64-bits

i965 will have more than 32 bits when BRW_STATE_COMPUTE_PROGRAM is added.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965: Modify state upload to allow 2 different sets of state atoms.

The set of state atoms for compute shaders is currently empty; it will
be filled in by future patches.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Modify dirty bit handling to support 2 pipelines.

The hardware state for compute shaders is almost entirely orthogonal
to the hardware state for 3D rendering.  To avoid sending unnecessary
state to the hardware, we'll need to have a separate set of state
atoms for the compute pipeline and the 3D pipeline.  That means we
need to maintain two separate sets of dirty bits to determine which
state atoms need to be run.

But the dirty bits are not completely independent; for example, if
BRW_NEW_SURFACES is flagged while doing 3D rendering, then not only do
we need to re-run 3D state atoms that depend on BRW_NEW_SURFACES, but
we also need to re-run compute state atoms that depend on
BRW_NEW_SURFACES.  But we'll also need to re-run those state atoms the
next time the compute pipeline is run.

To accomplish this, we record two sets of dirty bits, one for each
pipeline.  When bits are dirtied (via SET_DIRTY_BIT() or
SET_DIRTY_ALL()) we set them to the dirty state in both pipelines.
When brw_state_upload() is run, we clear the dirty bits just for the
pipeline that was run.

Note that since the number of pipelines is known at compile time to be
2, the compiler should unroll the loops in SET_DIRTY_BIT() and
SET_DIRTY_ALL().

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Create a macro for checking a dirty bit.

This will make it easier to extend dirty bit handling to support
compute shaders.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Create a macro for setting all dirty bits.

This will make it easier to extend dirty bit handling to support
compute shaders.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Create a macro for setting a dirty bit.

This will make it easier to extend dirty bit handling to support
compute shaders.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: add missing parens in vec4 visitor

coverity reported this, Matt said it look like missing parens,
not bad identing, so lets try that.

Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Dave Airlie <airlied@redhat.com>

nouveau: don't leak dec struct on error

This one path doesn't goto fail, so it seems to leak dec.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>

xvmc/tests: %C isn't a valid printf specifier.

Reported-by: Coverity scanner.
Signed-off-by: Dave Airlie <airlied@redhat.com>

nouveau/nv40: quiten coverity warning in unused vertex texture code.

This fixes the code, but we never run it anyways, so silence coverity.

Signed-off-by: Dave Airlie <airlied@redhat.com>

nv50: remove unused variables

Recent code changes have caused these to no longer be used. Remove them.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa: force height of 1D textures to be 1 in texture views

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

nv50: attach the buffer bo to the miptree structures

The current code... makes no sense. Use nouveau_bo_ref to attach the bo
to the exposed resource so as to have the proper lifetime guarantees.

Tested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>

nv50: mt address may not be the underlying bo's start address

With VP2, nv50_miptree is faked because the underlying bo's have to be
laid out in a certain way. This is done by adjusting the address. Make
sure that blits (and everything else for consistency) use the mt address
rather than the bo address as a base.

This fixes retrieving chroma plane with VDPAU.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82255
Tested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>

nv50: set the miptree address when clearing bo's in vp2 init

The mt address is about to be used more, make sure it's set
appropriately.

Reported-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>

nv50/ir: avoid creating instructions that can't be emitted

When constant folding a MAD operation, we first fold the multiply and
generate an ADD. However we do so without making sure that the immediate
can be handled in the saturate case. If it can't, load the immediate in
a separate instruction.

Reported-by: Tiziano Bacocco <tizbac2@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>

nvc0: don't make 1d staging textures linear

Experimentally, the sampler doesn't appear to like these, neither as
buffer nor as rect textures. So remove 1D from the list of texture types
to make linear when used for staging.

This fixes the OSD in mplayer for VDPAU.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>

nv50: zero out unbound samplers

Samplers are only defined up to num_samplers, so set all samplers above
nr to NULL so that we don't try to read them again later.

Tested-by: Christian Ruppert <idl0r@qasl.de>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>

nvc0/ir: avoid infinite recursion when finding first uses of tex

In certain circumstances, findFirstUses could end up doubling back on
instructions it had already processed, resulting in an infinite
recursion. Avoid this by keeping track of already-visited instructions.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83079
Tested-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>

freedreno/ir3: add DDX/DDY

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: don't keep IR around

Once we've assembled the shader, no need to keep the intermediate
around.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

i965/fs: Don't segfault when debug-logging a null program

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Don't segfault when debug-logging a null program

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeonsi: implement EXPCLEAR optimization for depth

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

r600g,radeonsi: initialize HTILE to fully-expanded state

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: implement fast depth clear

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: move DB_RENDER_CONTROL into draw_vbo

So that I can add fast depth clear.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: disable occlusion queries if they are not needed

We always left them enabled, which turned off HiZ in some cases.
This should improve performace with Hyper-Z.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

r600g,radeonsi: force fast stencil and HTILE stencil off, fixing a Hyper-Z hang

This should be as fast as no HTILE for stencil. I think we can still get full
performance with depth-only rendering even if stencil is present in the buffer
but not used, but I'm not 100% sure. This may be revisited when HiS and fast
stencil clear are implemented.

This fixes a hang in Brutal Legend.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64471

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

r600g: set VGT_ENHANCE=4 on R7xx

This is a golden setting on RV740, but there is a hw bug which recommends
setting it on all R7xx chipsets.

Acked-by: Michel Dänzer <michel.daenzer@amd.com>

r600g: expose AMD_vertex_shader_layer and *_viewport_index on R600-R700

already implemented

Acked-by: Michel Dänzer <michel.daenzer@amd.com>

r600g: fix layered clear

Cc: mesa-stable@lists.freedesktop.org
Acked-by: Michel Dänzer <michel.daenzer@amd.com>

r600g: some DB bug workarounds for R6xx DB flushing

Acked-by: Michel Dänzer <michel.daenzer@amd.com>

r600g: enable fast depth clear for array textures and cubemaps

I have a piglit test that hits this.

Acked-by: Michel Dänzer <michel.daenzer@amd.com>

r600g: use HTILE allocator from SI

It's almost the same.

This enables tiling for HTILE. It also enables Hyper-Z for other texture
targets (1D, 1D_ARRAY, 2D_ARRAY, CUBE, CUBE_ARRAY, 3D, RECT).

2D array depth textures are tested by Unigine Sanctuary and my new piglit
test.

Acked-by: Michel Dänzer <michel.daenzer@amd.com>

r600g: set DB_DEPTH_SIZE.HEIGHT_TILE_MAX for EG/CM, inline other fields

This fixes rendering to non-zero layer/face/slice with HTILE.

v2: added the assertion

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: set DB_DEPTH_SIZE.HEIGHT_TILE_MAX, inline other fields

This fixes rendering to a non-zero layer/face/slice with HTILE.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72685

v2: added the assertion

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

r600g: Implement sm5 geometry shader instancing

Requires Evergreen or later hardware.

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>

glsl_to_tgsi: allocate and enlarge arrays for temporaries on demand

This fixes crashes if the number of temporaries is greater than 4096.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66184

v2: added fail paths for realloc failures

Cc: 10.2 10.3 mesa-stable@lists.freedesktop.org
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

gallium/pb_bufmgr_cache: limit the size of cache

This should make a machine which is running piglit more responsive at times.
e.g. streaming-texture-leak can easily eat 600 MB because of how fast it
creates new textures.

pipe-loader: use the correct screen index

egl/dri2: use the correct screen index

Required for multi-GPU configuration where each GPU has its own X screen.

docs: Mark ARB_compute_shader as work in progress

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>

i965/fs: don't use ir->shadow_comparitor in emit_texture_*

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: don't pass ir_variable * to emit_samplepos_setup()

We were only using it to get at its type, which we already know because
it's a builtin variable.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: don't pass ir_variable * to emit_frontfacing_interpolation()

We were only using it to get at its type, which we already know because
it's a builtin variable.

v2 (Ken): Rebase on Matt's optimized gl_FrontFacing calculations.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Fix GPU hangs when INTEL_DEBUG=no16 is set.

The replicated data clear shader needs to be SIMD16, or else the GPU
will hang.  So, compile it even if INTEL_DEBUG=no16 is set.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: fix make tarballs

Current method of generating distribution tar-balls involves manually
invoking make + target name in the appropriate places. This temporary
solution is used until we get 'make dist' working.

Currently it does not work, as in order to have the target (which is
also a filename) available in the final Makefile we need to add a PHONY
target + use the correct target name.

Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

i965/vec4: Remove try_emit_saturate

Now that saturate is implemented natively as an instruction,
we can cut down on unneeded functionality.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

i965/fs: Refactor try_emit_saturate

v3: Since the fs backend can emit saturate as a separate instruction, there is
    no need to detect for min/max instructions and to rewrite the instruction tree
    accordingly. On the other hand, we don't need to emit a separate saturated
    mov either when the expression generating src can do saturate directly.
v4: Add can_do_saturate() check before enabling saturate modifer (Ken)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

ir_to_mesa, glsl_to_tgsi: Remove try_emit_saturate

Now that saturate is implemented natively as instruction,
we can cut down on unneeded functionality.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

i965/vec4: Allow propagation of instructions with saturate flag to sel

When sel conditon is bounded within 0 and 1.0. This allows code as:
        mov.sat a b
        sel.ge  dst a 0.25F

To be propagated as:
        sel.ge.sat dst b 0.25F

v3: - Syntax clarifications in inst->saturate assignment
    - Remove extra parenthesis when assigning src_reg value
      from copy_entry (Matt Turner)
v4: - Take channels into consideration when propagating saturated instructions.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

i965/fs: Allow propagation of instructions with saturate flag to sel

When sel conditon is bounded within 0 and 1.0. This allows code as:
mov.sat a b
sel.ge  dst a 0.25F

To be propagated as:
sel.ge.sat dst b 0.25F

v3: Syntax clarifications in inst->saturate assignment (Matt Turner)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

glsl: Optimize clamp(x, b, 1.0), where b > 0.0 as max(saturate(x),b)

v2: - Output max(saturate(x),b) instead of saturate(max(x,b))
    - Make sure we do component-wise comparison for vectors (Ian Romanick)
v3: - Add missing condition where the outer constant value is > 0.0 and
      inner constant is 1.0.
    - Fix comments to show that the optimization is a commutative operation
      (Matt Turner)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

glsl: Optimize clamp(x, 0.0, b), where b < 1.0 as min(saturate(x),b)

v2: - Output min(saturate(x),b) instead of saturate(min(x,b)) suggested by Ilia Mirkin
    - Make sure we do component-wise comparison for vectors (Ian Romanick)
v3: - Add missing condition where the outer constant value is zero and
      inner constant is < 1
    - Fix comments to reflect we are doing a commutative operation (Matt Turner)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

glsl: Optimize clamp(x, 0, 1) as saturate(x)

v2: - Check that the base type is float (Ian Romanick)
v3: - Make sure comments reflect that we are doing a commutative operation
    - Add missing condition where the inner constant is 1.0 and outer constant is 0.0
    - Make indexing of operands easier to read (Matt Turner)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

glsl: Implement saturate as ir_unop_saturate

Now that we have the ir_unop_saturate implemented as a single
instruction, generate the correct simplified expression.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

yi965/vec4: Add support for ir_unop_saturate

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

i965/fs: Add support for ir_unop_saturate

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

ir_to_mesa, glsl_to_tgsi: Add support for ir_unop_saturate

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

ir_to_mesa, glsl_to_tgsi: lower ir_unop_saturate

Needed when vertex programs doesn't allow saturate

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

glsl: Add a pass to lower ir_unop_saturate to clamp(x, 0, 1)

Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Add constant evaluation of ir_unop_saturate

v2: Use CLAMP macro (Ian Romanick)

Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Add ir_unop_saturate

Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/vec4/fs: Count loops in shader debug

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

i965/vec4: inline generate_vec4_instruction() within generate_code()

Suggested by Matt. This patch combines and moves back the code-generation
functions from generate_vec4_instruction() into generate_code(). Makes
generate_code() a bit larger, but helps us to count loops in a
straightforward manner.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

i965: Add 2x MSAA support to Broadwell fast clear code.

According to the cited documentation section (but in the newer docs),
x_scaledown is the same for 2x and 4x MSAA.

+47 piglits.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83081
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>

i965/vec4: Update register coalescing test.

In commit 04895f5c I added support for reswizzling writemasks. This test
was checking that we didn't support this.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82881

i965: Use unreachable() to silence warning.

brw_meta_fast_clear.c:211:17: warning: 'x_scaledown' may be used
uninitialized in this function [-Wmaybe-uninitialized]
    unsigned int x_scaledown, y_scaledown;

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>