Eddie Hung [Thu, 1 Aug 2019 22:13:18 +0000 (15:13 -0700)]
Add comment about supporting $dffe in ice40_dsp
Eddie Hung [Thu, 1 Aug 2019 22:10:43 +0000 (15:10 -0700)]
Pack P register properly
Eddie Hung [Thu, 1 Aug 2019 21:33:16 +0000 (14:33 -0700)]
Trim Y_WIDTH
Eddie Hung [Thu, 1 Aug 2019 21:29:00 +0000 (14:29 -0700)]
Add DSP_SIGNEDONLY back
Eddie Hung [Thu, 1 Aug 2019 20:20:34 +0000 (13:20 -0700)]
DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH
Eddie Hung [Thu, 1 Aug 2019 19:45:14 +0000 (12:45 -0700)]
Change $__softmul back to $mul
Eddie Hung [Thu, 1 Aug 2019 19:44:56 +0000 (12:44 -0700)]
Cope with sign extension in mul2dsp
Eddie Hung [Thu, 1 Aug 2019 19:17:14 +0000 (12:17 -0700)]
Revert "Do not do sign extension in techmap; let packer do it"
This reverts commit
595a8f032f1e9db385959f92a4a414a40de291fd.
Eddie Hung [Thu, 1 Aug 2019 19:02:16 +0000 (12:02 -0700)]
Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung [Thu, 1 Aug 2019 17:01:43 +0000 (10:01 -0700)]
Fix B_WIDTH > DSP_B_MAXWIDTH case
Eddie Hung [Thu, 1 Aug 2019 17:00:49 +0000 (10:00 -0700)]
CO is sign extension only if signed multiplier
Eddie Hung [Thu, 1 Aug 2019 17:00:01 +0000 (10:00 -0700)]
Fix typo
Eddie Hung [Thu, 1 Aug 2019 16:38:55 +0000 (09:38 -0700)]
Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map
xc6s_brams_map.v: RST -> RSTBRST for RAMB8BWER
Eddie Hung [Wed, 31 Jul 2019 23:04:19 +0000 (16:04 -0700)]
Do not compute sign bit if result is zero
Eddie Hung [Wed, 31 Jul 2019 22:45:41 +0000 (15:45 -0700)]
For signed multipliers, compute sign bit separately...
Eddie Hung [Wed, 31 Jul 2019 22:45:15 +0000 (15:45 -0700)]
Restore old CO behaviour
Eddie Hung [Wed, 31 Jul 2019 19:18:03 +0000 (12:18 -0700)]
Helper: SigSpec::operator[] to accept negative indices
Clifford Wolf [Wed, 31 Jul 2019 11:30:52 +0000 (13:30 +0200)]
Merge pull request #1233 from YosysHQ/clifford/defer
Call "read_verilog" with -defer from "read"
Eddie Hung [Mon, 29 Jul 2019 23:05:44 +0000 (16:05 -0700)]
RST -> RSTBRST for RAMB8BWER
Eddie Hung [Mon, 29 Jul 2019 16:16:09 +0000 (09:16 -0700)]
Merge pull request #1228 from YosysHQ/dave/yy_buf_size
verilog_lexer: Increase YY_BUF_SIZE to 65536
David Shah [Mon, 29 Jul 2019 14:50:20 +0000 (15:50 +0100)]
Merge pull request #1234 from mmicko/fix_gzip_no_exist
Fix case when file does not exist
Miodrag Milanovic [Mon, 29 Jul 2019 10:29:13 +0000 (12:29 +0200)]
Fix case when file does not exist
Clifford Wolf [Mon, 29 Jul 2019 08:40:30 +0000 (10:40 +0200)]
Update README to use "read" instead of "read_verilog"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 29 Jul 2019 08:29:36 +0000 (10:29 +0200)]
Call "read_verilog" with -defer from "read"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
David Shah [Sat, 27 Jul 2019 06:40:38 +0000 (07:40 +0100)]
Merge pull request #1226 from YosysHQ/dave/gzip
Add support for gzip'd input files
Eddie Hung [Fri, 26 Jul 2019 22:30:51 +0000 (15:30 -0700)]
Fix spacing
Eddie Hung [Fri, 26 Jul 2019 19:37:30 +0000 (12:37 -0700)]
Update test_autotb doc to reflect default value of zero
Eddie Hung [Fri, 26 Jul 2019 19:26:54 +0000 (12:26 -0700)]
Add doc for "test_autotb -seed" option
Eddie Hung [Fri, 26 Jul 2019 17:27:30 +0000 (10:27 -0700)]
Pop the CO bit from O
Eddie Hung [Fri, 26 Jul 2019 17:15:36 +0000 (10:15 -0700)]
Allow adders/accumulators with 33 bits using CO output
David Shah [Fri, 26 Jul 2019 14:53:21 +0000 (15:53 +0100)]
Update CHANGELOG
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 26 Jul 2019 12:35:39 +0000 (13:35 +0100)]
verilog_lexer: Increase YY_BUF_SIZE to 65536
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 26 Jul 2019 09:29:05 +0000 (10:29 +0100)]
Fix frontend auto-detection for gzipped input
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 26 Jul 2019 09:23:58 +0000 (10:23 +0100)]
Add support for reading gzip'd input files
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Thu, 25 Jul 2019 17:49:26 +0000 (10:49 -0700)]
Merge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung [Thu, 25 Jul 2019 17:44:20 +0000 (10:44 -0700)]
Bump abc to fix &mfs bug
Clifford Wolf [Thu, 25 Jul 2019 15:23:48 +0000 (17:23 +0200)]
Merge branch 'ZirconiumX-synth_intel_m9k'
Clifford Wolf [Thu, 25 Jul 2019 15:19:54 +0000 (17:19 +0200)]
Merge pull request #1218 from ZirconiumX/synth_intel_iopads
intel: Make -noiopads the default
Clifford Wolf [Thu, 25 Jul 2019 15:19:11 +0000 (17:19 +0200)]
Merge pull request #1219 from jakobwenzel/objIterator
made ObjectIterator comply with Iterator Interface
Eddie Hung [Thu, 25 Jul 2019 13:44:17 +0000 (06:44 -0700)]
Merge pull request #1224 from YosysHQ/xilinx_fix_ff
xilinx: Fix missing cell name underscore in cells_map.v
Jakob Wenzel [Thu, 25 Jul 2019 07:51:09 +0000 (09:51 +0200)]
replaced std::iterator with using statements
David Shah [Thu, 25 Jul 2019 07:19:07 +0000 (08:19 +0100)]
xilinx: Fix missing cell name underscore in cells_map.v
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Wed, 24 Jul 2019 17:51:03 +0000 (10:51 -0700)]
Merge pull request #1222 from koriakin/s6-example
Add a simple example for Spartan 6
Eddie Hung [Wed, 24 Jul 2019 17:49:09 +0000 (10:49 -0700)]
Add copyright header, comment on cascade
Marcin KoĆcielnicki [Wed, 24 Jul 2019 16:41:39 +0000 (18:41 +0200)]
Add a simple example for Spartan 6
Jakob Wenzel [Wed, 24 Jul 2019 11:33:07 +0000 (13:33 +0200)]
made ObjectIterator extend std::iterator
this makes it possible to use std algorithms on them
Dan Ravensloft [Wed, 24 Jul 2019 09:38:15 +0000 (10:38 +0100)]
intel: Make -noiopads the default
Eddie Hung [Tue, 23 Jul 2019 22:13:30 +0000 (15:13 -0700)]
Eliminate warnings by sizing O correctly
Eddie Hung [Tue, 23 Jul 2019 22:05:20 +0000 (15:05 -0700)]
Typo for Y_WIDTH
Eddie Hung [Tue, 23 Jul 2019 21:52:14 +0000 (14:52 -0700)]
Fix muxAB logic
Eddie Hung [Tue, 23 Jul 2019 21:21:45 +0000 (14:21 -0700)]
Remove debug print
Eddie Hung [Tue, 23 Jul 2019 21:20:34 +0000 (14:20 -0700)]
Simplify and fix for MACs
Eddie Hung [Tue, 23 Jul 2019 20:58:56 +0000 (13:58 -0700)]
Fix typo
Dan Ravensloft [Mon, 22 Jul 2019 11:15:22 +0000 (12:15 +0100)]
intel: Map M9K BRAM only on families that have it
This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.
Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
Eddie Hung [Tue, 23 Jul 2019 16:56:58 +0000 (09:56 -0700)]
Merge pull request #1212 from YosysHQ/eddie/signed_ice40_dsp
ice40: Fix SB_MAC16 sim model for signed modes
Eddie Hung [Mon, 22 Jul 2019 23:37:13 +0000 (16:37 -0700)]
Fix spacing
Eddie Hung [Mon, 22 Jul 2019 23:14:15 +0000 (16:14 -0700)]
Remove debug
Eddie Hung [Mon, 22 Jul 2019 23:12:57 +0000 (16:12 -0700)]
Pack hi and lo registers separately
Eddie Hung [Mon, 22 Jul 2019 23:10:21 +0000 (16:10 -0700)]
SigSpec::extract() to return as many bits as poss if out of bounds
Eddie Hung [Mon, 22 Jul 2019 22:08:26 +0000 (15:08 -0700)]
Rename according to vendor doc TN1295
Eddie Hung [Mon, 22 Jul 2019 22:05:16 +0000 (15:05 -0700)]
Pack Y register
Eddie Hung [Mon, 22 Jul 2019 20:48:33 +0000 (13:48 -0700)]
opt and wreduce necessary for -dsp
Eddie Hung [Mon, 22 Jul 2019 20:01:49 +0000 (13:01 -0700)]
Pack adders not just accumulators
Eddie Hung [Mon, 22 Jul 2019 20:01:26 +0000 (13:01 -0700)]
Use minimum sized width wires
Eddie Hung [Mon, 22 Jul 2019 14:42:53 +0000 (07:42 -0700)]
Merge pull request #1214 from jakobwenzel/astmod_clone
initialize noblackbox and nowb in AstModule::clone
Jakob Wenzel [Mon, 22 Jul 2019 08:37:40 +0000 (10:37 +0200)]
initialize noblackbox and nowb in AstModule::clone
Clifford Wolf [Sat, 20 Jul 2019 13:06:28 +0000 (15:06 +0200)]
Add "stat -tech cmos"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Sat, 20 Jul 2019 05:47:08 +0000 (22:47 -0700)]
Restore old ffY behaviour
Eddie Hung [Sat, 20 Jul 2019 03:25:28 +0000 (20:25 -0700)]
Cleanup
Eddie Hung [Sat, 20 Jul 2019 03:20:33 +0000 (20:20 -0700)]
Indirection via $__soft_mul
Eddie Hung [Fri, 19 Jul 2019 22:50:13 +0000 (15:50 -0700)]
Do not do sign extension in techmap; let packer do it
Eddie Hung [Fri, 19 Jul 2019 21:03:34 +0000 (14:03 -0700)]
Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp
Eddie Hung [Fri, 19 Jul 2019 21:02:46 +0000 (14:02 -0700)]
Add another test
Eddie Hung [Fri, 19 Jul 2019 20:58:50 +0000 (13:58 -0700)]
Do not access beyond bounds
Eddie Hung [Fri, 19 Jul 2019 20:54:57 +0000 (13:54 -0700)]
Add an SigSpec::at(offset, defval) convenience method
Eddie Hung [Fri, 19 Jul 2019 20:23:07 +0000 (13:23 -0700)]
Wrap A and B in sigmap
Eddie Hung [Fri, 19 Jul 2019 20:20:45 +0000 (13:20 -0700)]
Remove "top" from message
Eddie Hung [Fri, 19 Jul 2019 20:18:20 +0000 (13:18 -0700)]
Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp
Eddie Hung [Fri, 19 Jul 2019 20:11:48 +0000 (13:11 -0700)]
Also optimise MSB of $sub
Eddie Hung [Fri, 19 Jul 2019 20:11:30 +0000 (13:11 -0700)]
Add one more test with trimming Y_WIDTH of $sub
Eddie Hung [Fri, 19 Jul 2019 19:53:18 +0000 (12:53 -0700)]
Be more explicit
Eddie Hung [Fri, 19 Jul 2019 19:50:21 +0000 (12:50 -0700)]
wreduce for $sub
Eddie Hung [Fri, 19 Jul 2019 19:50:11 +0000 (12:50 -0700)]
Add tests for sub too
Eddie Hung [Fri, 19 Jul 2019 19:43:02 +0000 (12:43 -0700)]
Add test
Eddie Hung [Fri, 19 Jul 2019 19:34:04 +0000 (12:34 -0700)]
SigSpec::extract to take negative lengths
Eddie Hung [Fri, 19 Jul 2019 18:54:26 +0000 (11:54 -0700)]
Do not $mul -> $__mul if A and B are less than maxwidth
Eddie Hung [Fri, 19 Jul 2019 18:41:00 +0000 (11:41 -0700)]
Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold
Eddie Hung [Fri, 19 Jul 2019 18:39:24 +0000 (11:39 -0700)]
Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too
Eddie Hung [Fri, 19 Jul 2019 17:57:32 +0000 (10:57 -0700)]
Fine tune ice40_dsp.pmg, add support for packing subsets of registers
Eddie Hung [Fri, 19 Jul 2019 17:38:13 +0000 (10:38 -0700)]
Add support for ice40 signed multipliers
Eddie Hung [Fri, 19 Jul 2019 17:28:38 +0000 (10:28 -0700)]
Merge branch 'xc7dsp' into ice40dsp
Eddie Hung [Fri, 19 Jul 2019 17:27:44 +0000 (10:27 -0700)]
Fix typo in B
Eddie Hung [Fri, 19 Jul 2019 16:40:47 +0000 (09:40 -0700)]
Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp
David Shah [Fri, 19 Jul 2019 16:33:57 +0000 (17:33 +0100)]
ice40: Fix test_dsp_model.sh
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 19 Jul 2019 16:33:41 +0000 (17:33 +0100)]
ice40/cells_sim.v: Fix sign of J and K partial products
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Fri, 19 Jul 2019 16:16:13 +0000 (09:16 -0700)]
Use sign_headroom instead
David Shah [Fri, 19 Jul 2019 16:13:34 +0000 (17:13 +0100)]
ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Fri, 19 Jul 2019 15:52:49 +0000 (08:52 -0700)]
Add tests for all combinations of A and B signedness for comb mul
Eddie Hung [Fri, 19 Jul 2019 15:45:35 +0000 (08:45 -0700)]
Don't copy ref if exists already
Eddie Hung [Fri, 19 Jul 2019 04:03:54 +0000 (21:03 -0700)]
Fix SB_MAC sim model -- do not sign extend internal products?