openpower-isa.git
14 months agopower_enums: deprecate CRType enum
Dmitry Selyutin [Wed, 16 Nov 2022 19:47:40 +0000 (22:47 +0300)]
power_enums: deprecate CRType enum

14 months agopower_enums: clean code
Dmitry Selyutin [Wed, 16 Nov 2022 19:47:40 +0000 (22:47 +0300)]
power_enums: clean code

14 months agopower_enums: support 8/16/32 in SVP64Width
Dmitry Selyutin [Wed, 16 Nov 2022 19:47:40 +0000 (22:47 +0300)]
power_enums: support 8/16/32 in SVP64Width

14 months agopower_insn: switch to SVP64SubVL enum
Dmitry Selyutin [Tue, 15 Nov 2022 20:56:13 +0000 (23:56 +0300)]
power_insn: switch to SVP64SubVL enum

14 months agopower_enums: support subvl conversions
Dmitry Selyutin [Tue, 15 Nov 2022 20:04:53 +0000 (23:04 +0300)]
power_enums: support subvl conversions

14 months agopower_insn: validate predicates masks
Dmitry Selyutin [Tue, 15 Nov 2022 19:57:36 +0000 (22:57 +0300)]
power_insn: validate predicates masks

14 months agopower_enums: support predicate type property
Dmitry Selyutin [Tue, 15 Nov 2022 19:41:13 +0000 (22:41 +0300)]
power_enums: support predicate type property

14 months agopower_insn: introduce validation stubs
Dmitry Selyutin [Tue, 15 Nov 2022 19:25:10 +0000 (22:25 +0300)]
power_insn: introduce validation stubs

14 months agopower_insn: support predicates masks
Dmitry Selyutin [Tue, 15 Nov 2022 15:49:23 +0000 (18:49 +0300)]
power_insn: support predicates masks

14 months agopower_insn: support failfirst/predresult
Dmitry Selyutin [Sun, 13 Nov 2022 21:04:09 +0000 (00:04 +0300)]
power_insn: support failfirst/predresult

14 months agopower_enums: support predicates
Dmitry Selyutin [Mon, 14 Nov 2022 19:17:43 +0000 (22:17 +0300)]
power_enums: support predicates

14 months agopower_insn: support subvector length specifiers
Dmitry Selyutin [Fri, 11 Nov 2022 19:24:00 +0000 (22:24 +0300)]
power_insn: support subvector length specifiers

14 months agopower_insn: support width specifier
Dmitry Selyutin [Fri, 11 Nov 2022 17:20:23 +0000 (20:20 +0300)]
power_insn: support width specifier

14 months agopower_insn: fix Rc record property
Dmitry Selyutin [Sun, 13 Nov 2022 21:10:47 +0000 (00:10 +0300)]
power_insn: fix Rc record property

14 months agopysvp64asm: allow insndb-based assembly
Dmitry Selyutin [Sun, 13 Nov 2022 21:07:01 +0000 (00:07 +0300)]
pysvp64asm: allow insndb-based assembly

14 months agopower_enums: clean CR definitions
Dmitry Selyutin [Sun, 13 Nov 2022 18:52:23 +0000 (21:52 +0300)]
power_enums: clean CR definitions

14 months agopower_fields: support field bits assignment
Dmitry Selyutin [Sun, 13 Nov 2022 14:26:06 +0000 (17:26 +0300)]
power_fields: support field bits assignment

14 months agopower_insn: support empty arguments
Dmitry Selyutin [Fri, 11 Nov 2022 17:05:08 +0000 (20:05 +0300)]
power_insn: support empty arguments

14 months agopower_insn: support CR operands disassembly
Dmitry Selyutin [Tue, 8 Nov 2022 20:26:12 +0000 (23:26 +0300)]
power_insn: support CR operands disassembly

14 months agopower_insn: fix opcodes generation (again)
Dmitry Selyutin [Tue, 8 Nov 2022 18:56:38 +0000 (21:56 +0300)]
power_insn: fix opcodes generation (again)

14 months agopower_insn: simplify spans and bytes conversion
Dmitry Selyutin [Mon, 7 Nov 2022 21:50:07 +0000 (00:50 +0300)]
power_insn: simplify spans and bytes conversion

14 months agopower_insn: fix operands iteration
Dmitry Selyutin [Mon, 7 Nov 2022 19:29:34 +0000 (22:29 +0300)]
power_insn: fix operands iteration

14 months agopower_insn: support CR operands assembly
Dmitry Selyutin [Mon, 7 Nov 2022 18:54:35 +0000 (21:54 +0300)]
power_insn: support CR operands assembly

14 months agopower_insn: refactor extandable operands assembly
Dmitry Selyutin [Mon, 7 Nov 2022 18:22:05 +0000 (21:22 +0300)]
power_insn: refactor extandable operands assembly

14 months agopower_insn: remap GPR and FPR operands
Dmitry Selyutin [Mon, 7 Nov 2022 18:16:23 +0000 (21:16 +0300)]
power_insn: remap GPR and FPR operands

14 months agopower_insn: unify GPR and FPR assembly
Dmitry Selyutin [Sun, 6 Nov 2022 17:06:41 +0000 (20:06 +0300)]
power_insn: unify GPR and FPR assembly

14 months agopower_insn: provide SVP64 assembly stub
Dmitry Selyutin [Sun, 6 Nov 2022 16:50:14 +0000 (19:50 +0300)]
power_insn: provide SVP64 assembly stub

14 months agopysvp64asm: deprecate custom_insn helper
Dmitry Selyutin [Sun, 6 Nov 2022 09:30:40 +0000 (12:30 +0300)]
pysvp64asm: deprecate custom_insn helper

14 months agopower_insn: discard overlaps for dynamic operands
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: discard overlaps for dynamic operands

14 months agopower_insn: fix DOperandDX span
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: fix DOperandDX span

14 months agopower_insn: fix XO static operand
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: fix XO static operand

14 months agopower_insn: hide records repr from operands
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: hide records repr from operands

14 months agopower_insn: sort opcodes by sections
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: sort opcodes by sections

14 months agopower_insn: fix repr for opcode mask and value
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: fix repr for opcode mask and value

14 months agopower_insn: support tables priorities
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: support tables priorities

14 months agopower_insn: provide operands helpers
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: provide operands helpers

14 months agopower_insn: cache operands
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: cache operands

14 months agopower_insn: deprecate operand record argument
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: deprecate operand record argument

14 months agopower_insn: simplify word instruction assembly
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: simplify word instruction assembly

14 months agopower_insn: introduce PO and XO static operands
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: introduce PO and XO static operands

14 months agopower_insn: introduce record operands helpers
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: introduce record operands helpers

14 months agopower_insn: convert spans into properties
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: convert spans into properties

14 months agopower_insn: bind records to operands
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: bind records to operands

14 months agopower_insn: postpone operands initialization
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: postpone operands initialization

14 months agopower_insn: ensure operands are always dataclasses
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: ensure operands are always dataclasses

14 months agopower_insn: provide basics for insndb assembly
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: provide basics for insndb assembly

14 months agopower_insn: return None for unknown insn names
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: return None for unknown insn names

14 months agopower_insn: introduce signed immediate operand class
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: introduce signed immediate operand class

14 months agopower_insn: rename register operand class
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: rename register operand class

14 months agopower_insn: clean and simplify EXTS operands
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: clean and simplify EXTS operands

14 months agopower_insn: support FPR operands assembly
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: support FPR operands assembly

14 months agopower_insn: support GPR operands
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: support GPR operands

14 months agopower_insn: support non-zero operands
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: support non-zero operands

14 months agopower_insn: allow sign only for SignedOperand
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: allow sign only for SignedOperand

14 months agopower_insn: add support for a trivial assembly
Dmitry Selyutin [Sun, 6 Nov 2022 09:29:55 +0000 (12:29 +0300)]
power_insn: add support for a trivial assembly

14 months agoadd INSNDB=true test pass to .gitlab-ci.yml
Jacob Lifshay [Mon, 12 Dec 2022 21:01:46 +0000 (13:01 -0800)]
add INSNDB=true test pass to .gitlab-ci.yml

14 months agocorrect name for Mem test function
Luke Kenneth Casson Leighton [Sun, 1 Jan 2023 23:37:15 +0000 (23:37 +0000)]
correct name for Mem test function

14 months agogaah a mess (but working)
Luke Kenneth Casson Leighton [Sun, 1 Jan 2023 23:32:29 +0000 (23:32 +0000)]
gaah a mess (but working)
as there is no elf-loading in pypowersim, .data .rodata .eh_frame and other
information is missing and/or in the wrong place.

had to get things working exactly as in media/mp3_0.sh, which is to call
just the one function with the input data pre-loaded into specific memory
locations

14 months agouse qemu user-mode to run cross-compiled xchacha20
Luke Kenneth Casson Leighton [Sun, 1 Jan 2023 15:51:52 +0000 (15:51 +0000)]
use qemu user-mode to run cross-compiled xchacha20

14 months agoascii dump on xchacha20 to compare against x86 version
Luke Kenneth Casson Leighton [Sun, 1 Jan 2023 15:37:33 +0000 (15:37 +0000)]
ascii dump on xchacha20 to compare against x86 version

14 months agoadd -mno-altivec option to xchacha20 test
Luke Kenneth Casson Leighton [Sun, 1 Jan 2023 15:12:19 +0000 (15:12 +0000)]
add -mno-altivec option to xchacha20 test

14 months agoenable misaligned Mem in ISACaller by default
Luke Kenneth Casson Leighton [Sun, 1 Jan 2023 15:09:21 +0000 (15:09 +0000)]
enable misaligned Mem in ISACaller by default

14 months agoHandle newer nMigen adding a "bench" top-level root in VCD files
Cesar Strauss [Sun, 1 Jan 2023 12:32:54 +0000 (09:32 -0300)]
Handle newer nMigen adding a "bench" top-level root in VCD files

14 months agocorrections to boundary-wrapped store, and add misaligned store that is
Luke Kenneth Casson Leighton [Fri, 30 Dec 2022 13:59:47 +0000 (13:59 +0000)]
corrections to boundary-wrapped store, and add misaligned store that is
storing to a single line (not wrapping)

14 months agoadd rollover mem test, store "rolls over" a 64-bit boundary
Luke Kenneth Casson Leighton [Fri, 30 Dec 2022 13:41:49 +0000 (13:41 +0000)]
add rollover mem test, store "rolls over" a 64-bit boundary

14 months agoadd misaligned mem test
Luke Kenneth Casson Leighton [Fri, 30 Dec 2022 13:26:45 +0000 (13:26 +0000)]
add misaligned mem test

14 months agoadd misaligned mem test
Luke Kenneth Casson Leighton [Fri, 30 Dec 2022 13:20:56 +0000 (13:20 +0000)]
add misaligned mem test

14 months agorelocate main() to a single section
Luke Kenneth Casson Leighton [Fri, 30 Dec 2022 13:18:41 +0000 (13:18 +0000)]
relocate main() to a single section
so that it can be put at a fixed address

14 months agoadd unit test for Mem class, need to add misaligned ld/st
Luke Kenneth Casson Leighton [Fri, 30 Dec 2022 13:18:21 +0000 (13:18 +0000)]
add unit test for Mem class, need to add misaligned ld/st

14 months agoprint out memory exception details, on unaligned
Luke Kenneth Casson Leighton [Thu, 29 Dec 2022 21:28:06 +0000 (21:28 +0000)]
print out memory exception details, on unaligned

14 months agoadd .gitignore
Luke Kenneth Casson Leighton [Thu, 29 Dec 2022 16:56:23 +0000 (16:56 +0000)]
add .gitignore

14 months agoadd cross-compiled test of xchacha20 suitable for running under pypowersim
Luke Kenneth Casson Leighton [Thu, 29 Dec 2022 16:48:01 +0000 (16:48 +0000)]
add cross-compiled test of xchacha20 suitable for running under pypowersim

14 months agosimplify by running smallest test
Luke Kenneth Casson Leighton [Thu, 29 Dec 2022 13:10:09 +0000 (13:10 +0000)]
simplify by running smallest test

14 months agoget video pypowersim_wrapper running
Luke Kenneth Casson Leighton [Thu, 29 Dec 2022 13:04:09 +0000 (13:04 +0000)]
get video pypowersim_wrapper running

14 months agoadd bryan hawkins chacha20 source from
Luke Kenneth Casson Leighton [Thu, 29 Dec 2022 12:53:45 +0000 (12:53 +0000)]
add bryan hawkins chacha20 source from
https://github.com/spcnvdr/xchacha20

14 months agoadd maddedus
Jacob Lifshay [Fri, 11 Nov 2022 08:52:36 +0000 (00:52 -0800)]
add maddedus

14 months agofix case_sv_bigint_shift_left_then_back
Jacob Lifshay [Fri, 11 Nov 2022 08:51:07 +0000 (00:51 -0800)]
fix case_sv_bigint_shift_left_then_back

14 months agoXLEN-ify maddedu
Jacob Lifshay [Fri, 11 Nov 2022 08:49:52 +0000 (00:49 -0800)]
XLEN-ify maddedu

14 months agofix maddedu title line
Jacob Lifshay [Fri, 11 Nov 2022 08:48:52 +0000 (00:48 -0800)]
fix maddedu title line

14 months agofix bug in parser when concatenating stuff that isn't variables
Jacob Lifshay [Fri, 11 Nov 2022 08:41:18 +0000 (00:41 -0800)]
fix bug in parser when concatenating stuff that isn't variables

14 months agotests/bigint: provide shadd/shadduw tests
Dmitry Selyutin [Tue, 1 Nov 2022 17:37:06 +0000 (20:37 +0300)]
tests/bigint: provide shadd/shadduw tests

14 months agoselectable_int: support variable concatenation
Dmitry Selyutin [Tue, 1 Nov 2022 17:35:11 +0000 (20:35 +0300)]
selectable_int: support variable concatenation

14 months agobitmanip.mdwn: avoid overflow for m variable
Dmitry Selyutin [Tue, 1 Nov 2022 19:16:52 +0000 (22:16 +0300)]
bitmanip.mdwn: avoid overflow for m variable

14 months agoRevert "Revert "https://bugs.libre-soc.org/show_bug.cgi?id=966#c4""
Dmitry Selyutin [Tue, 1 Nov 2022 17:37:42 +0000 (20:37 +0300)]
Revert "Revert "https://bugs.libre-soc.org/show_bug.cgi?id=966#c4""

This reverts commit 975f1b62b0430ca93377ee1a18d8d9138d5b5254.

14 months agoRevert "corrections to shadd/uw after reverting to switch"
Dmitry Selyutin [Tue, 1 Nov 2022 17:37:32 +0000 (20:37 +0300)]
Revert "corrections to shadd/uw after reverting to switch"

This reverts commit 6484c99953ceeff206a5888c148b9412be1b5656.

14 months agocorrections to shadd/uw after reverting to switch
Luke Kenneth Casson Leighton [Tue, 1 Nov 2022 13:53:27 +0000 (13:53 +0000)]
corrections to shadd/uw after reverting to switch

14 months agoRevert "https://bugs.libre-soc.org/show_bug.cgi?id=966#c4"
Luke Kenneth Casson Leighton [Tue, 1 Nov 2022 13:49:16 +0000 (13:49 +0000)]
Revert "https://bugs.libre-soc.org/show_bug.cgi?id=966#c4"

This reverts commit 263a8fca0f7413e62cf74a0e559e8965b0951e6c.

14 months agoadd dsld. (Rc=1) test, make overflow acceptable to handle_comparison()
Luke Kenneth Casson Leighton [Sat, 29 Oct 2022 15:12:06 +0000 (16:12 +0100)]
add dsld. (Rc=1) test, make overflow acceptable to handle_comparison()
in ISACaller

14 months agoadd tests for carry/overflow calculation of addmeo/subfmeo
Jacob Lifshay [Fri, 28 Oct 2022 22:06:25 +0000 (15:06 -0700)]
add tests for carry/overflow calculation of addmeo/subfmeo

the logic for computing carry/overflow in the simulator is likely broken...

the pseudocode may also need to be changed to add [1] * XLEN like in the
description of addme/subfme

14 months agoformat code
Jacob Lifshay [Fri, 28 Oct 2022 20:38:29 +0000 (13:38 -0700)]
format code

14 months agodsld: MASK(0, 63-n) works just as well as MASK(64, 63-n).
Luke Kenneth Casson Leighton [Fri, 28 Oct 2022 22:09:22 +0000 (23:09 +0100)]
dsld: MASK(0, 63-n) works just as well as MASK(64, 63-n).
also fix "overflow" pseudocode

14 months agooverflow condition in dsld and dsrd if RS is non-zero
Luke Kenneth Casson Leighton [Fri, 28 Oct 2022 12:23:42 +0000 (13:23 +0100)]
overflow condition in dsld and dsrd if RS is non-zero

14 months agofix dsrd pseudocode to use ROTL64 not ROTL128
Luke Kenneth Casson Leighton [Fri, 28 Oct 2022 12:23:08 +0000 (13:23 +0100)]
fix dsrd pseudocode to use ROTL64 not ROTL128

14 months agofix dsld pseudocode to use ROTL64 instead of ROTL128
Luke Kenneth Casson Leighton [Fri, 28 Oct 2022 12:20:10 +0000 (13:20 +0100)]
fix dsld pseudocode to use ROTL64 instead of ROTL128

14 months agoadd test showing that dsld and dsrd are not quite inverses
Luke Kenneth Casson Leighton [Fri, 28 Oct 2022 12:14:11 +0000 (13:14 +0100)]
add test showing that dsld and dsrd are not quite inverses

14 months agoupdate csvs to match make output
Jacob Lifshay [Fri, 28 Oct 2022 09:30:36 +0000 (02:30 -0700)]
update csvs to match make output

14 months agofix bigint shift tests
Jacob Lifshay [Fri, 28 Oct 2022 00:01:45 +0000 (17:01 -0700)]
fix bigint shift tests

14 months agofix dsrd, ROTL128 use 128-n not 64-n,
Luke Kenneth Casson Leighton [Thu, 27 Oct 2022 22:40:02 +0000 (23:40 +0100)]
fix dsrd, ROTL128 use 128-n not 64-n,
fix svp64 dsrd/dsld unit tests

14 months agoredo sv_analysis for dsld/dsrd
Luke Kenneth Casson Leighton [Thu, 27 Oct 2022 22:08:53 +0000 (23:08 +0100)]
redo sv_analysis for dsld/dsrd

14 months agofix dsrd pseudocode for new 3-in 2-out
Luke Kenneth Casson Leighton [Thu, 27 Oct 2022 14:47:53 +0000 (15:47 +0100)]
fix dsrd pseudocode for new 3-in 2-out
https://bugs.libre-soc.org/show_bug.cgi?id=937#c16