Anton Blanchard [Thu, 19 Sep 2019 11:48:22 +0000 (21:48 +1000)]
Merge pull request #65 from antonblanchard/loadstore-opt
A small loadstore optimisation, and some reformatting
Anton Blanchard [Thu, 19 Sep 2019 11:37:43 +0000 (21:37 +1000)]
Reformat loadstore1
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 19 Sep 2019 11:36:51 +0000 (21:36 +1000)]
Reformat loadstore2
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 19 Sep 2019 11:31:34 +0000 (21:31 +1000)]
loads don't do both byte reversal and sign extension
Give the synthesis tools a clue that we don't need to do both byte reversal
and sign extension.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 19 Sep 2019 11:07:31 +0000 (21:07 +1000)]
Merge pull request #64 from antonblanchard/reformat-3
Reformat some more files
Anton Blanchard [Thu, 19 Sep 2019 10:36:26 +0000 (20:36 +1000)]
Merge pull request #63 from antonblanchard/multiply-cleanup
Multiply cleanup
Anton Blanchard [Thu, 19 Sep 2019 10:35:42 +0000 (20:35 +1000)]
Reformat wishbone code
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 19 Sep 2019 10:33:58 +0000 (20:33 +1000)]
Reformat glibc_random
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 19 Sep 2019 10:32:07 +0000 (20:32 +1000)]
Reformat simple_ram_behavioural
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 19 Sep 2019 10:28:37 +0000 (20:28 +1000)]
Reformat sim_console
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 19 Sep 2019 10:26:55 +0000 (20:26 +1000)]
Reformat multiply_tb
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 19 Sep 2019 10:24:29 +0000 (20:24 +1000)]
Reformat execute2
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 19 Sep 2019 10:22:36 +0000 (20:22 +1000)]
Reformat CR file
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 19 Sep 2019 10:21:58 +0000 (20:21 +1000)]
Reformat register file
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 19 Sep 2019 10:19:46 +0000 (20:19 +1000)]
Reformat multiply code
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 19 Sep 2019 10:18:01 +0000 (20:18 +1000)]
Don't use VHDL 2008 condition operator in multiply
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 16 Sep 2019 03:17:37 +0000 (13:17 +1000)]
Merge pull request #62 from antonblanchard/byte-reverse-store-opt
Move byte reversal of stores to first cycle
Anton Blanchard [Mon, 16 Sep 2019 03:14:25 +0000 (13:14 +1000)]
Merge pull request #61 from antonblanchard/execute-cleanup
execute1 no longer needs sim_console
Anton Blanchard [Mon, 16 Sep 2019 01:49:44 +0000 (11:49 +1000)]
Move byte reversal of stores to first cycle
We are seeing some timing issues with the second cycle of loadstore,
and we aren't doing much in the first cycle, so move it here.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 16 Sep 2019 01:18:53 +0000 (11:18 +1000)]
execute1 no longer needs sim_console
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 15 Sep 2019 12:52:14 +0000 (22:52 +1000)]
Merge pull request #60 from antonblanchard/testbenches
Add a few more test benches
Anton Blanchard [Fri, 13 Sep 2019 10:35:08 +0000 (20:35 +1000)]
Fix multiply_tb
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Fri, 13 Sep 2019 10:17:17 +0000 (20:17 +1000)]
Add an icache testbench
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 15 Sep 2019 12:08:57 +0000 (22:08 +1000)]
Merge pull request #56 from antonblanchard/writeback-fix3
Remove cycle in writeback
Anton Blanchard [Sun, 15 Sep 2019 08:03:48 +0000 (18:03 +1000)]
Remove cycle in writeback
The pipeline had a cycle in writeback. Writeback is pretty
simple and unlikely to be a bottleneck, so lets remove it.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 15 Sep 2019 11:37:47 +0000 (21:37 +1000)]
Merge pull request #59 from antonblanchard/trap-decode
Fix make check
Anton Blanchard [Sun, 15 Sep 2019 11:30:30 +0000 (21:30 +1000)]
Merge pull request #58 from antonblanchard/decode2-assert
Fix spurious outstanding assert
Anton Blanchard [Sun, 15 Sep 2019 11:21:36 +0000 (21:21 +1000)]
Fix make check
We need to finish support for all the trap instructions, but for now
we at least need a decode entry for tw, so we know to stall until the
previous instruction completes. Some of our test cases were failing
because the trap executed before the previous instruction completed.
All these trap instructions need to be resolved at completion, not
in execute.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 15 Sep 2019 08:59:24 +0000 (18:59 +1000)]
Fix spurious outstanding assert
Check it in the sequential process, not the combinatorial one.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 15 Sep 2019 08:34:27 +0000 (18:34 +1000)]
Merge pull request #57 from antonblanchard/add-nop
Add a decode for the nop instruction
Anton Blanchard [Sun, 15 Sep 2019 08:18:24 +0000 (18:18 +1000)]
Add a decode for the nop instruction
We want these to go out without any GPR dependencies, so add
a specific entry in decode for them.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 15 Sep 2019 01:18:42 +0000 (11:18 +1000)]
Merge pull request #55 from antonblanchard/fetch-fix
Add a default value for RESET_ADDRESS
Anton Blanchard [Sun, 15 Sep 2019 00:25:57 +0000 (10:25 +1000)]
Add a default value for RESET_ADDRESS
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sat, 14 Sep 2019 23:55:10 +0000 (09:55 +1000)]
Merge pull request #51 from antonblanchard/writeback-fix
Some writeback updates
Anton Blanchard [Sat, 14 Sep 2019 23:07:34 +0000 (09:07 +1000)]
Reformat writeback.vhdl
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sat, 14 Sep 2019 23:04:47 +0000 (09:04 +1000)]
Exit if we try to write more than one GPR or CR in a cycle
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 12 Sep 2019 11:15:24 +0000 (21:15 +1000)]
Merge pull request #50 from antonblanchard/decode1-opt
No need to gate nia or insn in decode1
Anton Blanchard [Thu, 12 Sep 2019 07:06:09 +0000 (17:06 +1000)]
No need to gate nia or insn in decode1
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 12 Sep 2019 06:14:28 +0000 (16:14 +1000)]
Merge pull request #49 from antonblanchard/icache-2
Add a simple direct mapped icache
Anton Blanchard [Wed, 11 Sep 2019 03:05:17 +0000 (13:05 +1000)]
Add a simple direct mapped icache
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 11 Sep 2019 07:21:52 +0000 (17:21 +1000)]
SOC memory wishbone should clear ACK regardless of STB
The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.
Fixing this improves the situation to one transfer every 2 cycles.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 12 Sep 2019 03:03:33 +0000 (13:03 +1000)]
Merge pull request #48 from antonblanchard/clk_gen_bypass
Fix clk_gen_bypass
Anton Blanchard [Thu, 12 Sep 2019 02:25:18 +0000 (12:25 +1000)]
Fix clk_gen_bypass
I broke clk_gen_bypass when updating the SOC reset code.
Fixes
03fd06deaf9f ("Rework SOC reset")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 11 Sep 2019 23:46:22 +0000 (09:46 +1000)]
Merge pull request #47 from antonblanchard/if-fix
Explicitly check against '1' in if statements
Anton Blanchard [Wed, 11 Sep 2019 23:46:01 +0000 (09:46 +1000)]
Merge pull request #46 from antonblanchard/record-fix
Remove names from end record statements
Anton Blanchard [Wed, 11 Sep 2019 23:19:31 +0000 (09:19 +1000)]
Explicitly check against '1' in if statements
nvc doesn't like what I think is a VHDL 2008 construct. Lets just
check against '1' explicitly.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 11 Sep 2019 23:04:02 +0000 (09:04 +1000)]
Remove names from end record statements
These are optional, and vhdlpp from iverilog barfs on them.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 11 Sep 2019 12:53:47 +0000 (22:53 +1000)]
Merge pull request #45 from antonblanchard/fixes
Fix a couple of issues in the recent pipelining merge
Anton Blanchard [Wed, 11 Sep 2019 12:40:53 +0000 (22:40 +1000)]
Fix issue in loadstore1
We weren't using the register in this stage.
Fixes: 819f8200905f ("Register outputs on loadstore1")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 11 Sep 2019 12:39:30 +0000 (22:39 +1000)]
Fix issue in execute2
We weren't using the register in this stage.
Fixes: c7aa683ba8aa ("Register outputs on execute2")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 11 Sep 2019 11:58:01 +0000 (21:58 +1000)]
Merge pull request #44 from antonblanchard/nia-remove
Remove nia from loadstore and multiply
Anton Blanchard [Wed, 11 Sep 2019 11:42:37 +0000 (21:42 +1000)]
Remove nia from loadstore and multiply
Neither unit needs the NIA, so remove it.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 11 Sep 2019 11:42:00 +0000 (21:42 +1000)]
Merge pull request #43 from mikey/trivial
Remove FIXME comment
Michael Neuling [Wed, 11 Sep 2019 06:50:57 +0000 (16:50 +1000)]
Remove FIXME comment
This was mistakenly left behind in
4d5abfb430d1 ("Remove dynamic
ranges from code")
Signed-off-by: Michael Neuling <mikey@neuling.org>
Anton Blanchard [Wed, 11 Sep 2019 06:05:05 +0000 (16:05 +1000)]
Merge pull request #41 from mikey/travis
Allow a full make check on Travis
Anton Blanchard [Wed, 11 Sep 2019 06:04:10 +0000 (16:04 +1000)]
Merge pull request #42 from antonblanchard/fetch-rework-v2
Fetch rework
Anton Blanchard [Tue, 10 Sep 2019 21:55:35 +0000 (07:55 +1000)]
Reformat core.vhdl
Anton Blanchard [Tue, 10 Sep 2019 21:16:56 +0000 (07:16 +1000)]
Remove sim console
We can force all existing code to use the UART console
by passing 0 in bit zero of the sim config register.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 10 Sep 2019 06:22:58 +0000 (16:22 +1000)]
Reduce multiply to 2 cycles
We want all non load/store ops to take 2 cycles to make
tracking write back easier.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 10 Sep 2019 06:04:39 +0000 (16:04 +1000)]
Register outputs on writeback
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 10 Sep 2019 05:40:20 +0000 (15:40 +1000)]
Register outputs on execute2
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 10 Sep 2019 05:39:50 +0000 (15:39 +1000)]
Register outputs on loadstore1
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 10 Sep 2019 05:02:18 +0000 (15:02 +1000)]
Move debug execute output into decode2
This covers all units, and we avoid double printing.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 3 Sep 2019 23:36:30 +0000 (09:36 +1000)]
Rework pipeline, add stall and flush signals
This adds stall and flush signals to the pipeline.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Michael Neuling [Wed, 11 Sep 2019 00:18:19 +0000 (10:18 +1000)]
Allow a full make check on Travis
Some Travis instances allow more CPU time. On these we can perform the
full 'make check'.
This patch allows this longer `make check`. To enable it you need to
go into your Travis configuration and add a TRAVIS_FULL_CHECK
environment variable.
If you don't add this environment, the shorter make check_light is
still run.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Anton Blanchard [Tue, 10 Sep 2019 21:48:19 +0000 (07:48 +1000)]
Merge pull request #40 from antonblanchard/makefile-dependencies
Update Makefile dependencies
Anton Blanchard [Tue, 10 Sep 2019 21:32:00 +0000 (07:32 +1000)]
Update Makefile dependencies
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 10 Sep 2019 15:59:10 +0000 (16:59 +0100)]
Switch soc to use std_ulogic
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 10 Sep 2019 15:40:11 +0000 (16:40 +0100)]
Share soc.vhdl between FPGA and sim
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 10 Sep 2019 15:39:52 +0000 (16:39 +0100)]
Pass wishbone record to bram memory module
(And rename it to mw_soc_memory).
This makes soc.vhdl simpler and provides the same interface as
the simulated memory, which will help when sharing soc.vhdl
with sim later
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 10 Sep 2019 13:52:23 +0000 (14:52 +0100)]
Rework wishbone slave address decoding
Don't make it synchronous, no latches
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Sat, 31 Aug 2019 08:54:58 +0000 (18:54 +1000)]
Move wishbone arbiter out of the core
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 10 Sep 2019 12:01:17 +0000 (13:01 +0100)]
Re-indent and reformat soc.vhdl
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 10 Sep 2019 11:45:33 +0000 (12:45 +0100)]
Split FPGA toplevel from soc
This will be useful when we start needing different toplevels for
different boards.
We keep the reset and clock generators in the toplevel as they will
eventually be taken over by litedram when we integrate it, and they
are more likely to change on different system types.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard [Tue, 10 Sep 2019 07:07:09 +0000 (17:07 +1000)]
Merge pull request #39 from antonblanchard/no-x-state
Don't send out X state from the memory behavioural
Anton Blanchard [Tue, 10 Sep 2019 06:46:41 +0000 (16:46 +1000)]
Don't send out X state from the memory behavioural
Just send out all 1s.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 10 Sep 2019 06:31:37 +0000 (16:31 +1000)]
Merge pull request #36 from mikey/gitignore
Add new files to git ignore
Anton Blanchard [Tue, 10 Sep 2019 06:31:08 +0000 (16:31 +1000)]
Merge pull request #38 from antonblanchard/multiply-warn
Quieten multiply warning
Anton Blanchard [Tue, 10 Sep 2019 05:31:54 +0000 (15:31 +1000)]
Quieten multiply warning
We no longer gate multiply with the valid signal, so it's complaining
a lot. Comment out the warning.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Michael Neuling [Tue, 10 Sep 2019 05:00:35 +0000 (15:00 +1000)]
Add new files to git ignore
Signed-off-by: Michael Neuling <mikey@neuling.org>
Anton Blanchard [Mon, 9 Sep 2019 23:14:31 +0000 (09:14 +1000)]
Merge pull request #35 from antonblanchard/multiply-opt
Simplify multiply
Anton Blanchard [Sun, 8 Sep 2019 01:11:15 +0000 (11:11 +1000)]
Simplify multiply
No need to gate everything with the valid bit.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 9 Sep 2019 22:09:48 +0000 (08:09 +1000)]
Merge pull request #34 from antonblanchard/decode-table
Decode table
Anton Blanchard [Mon, 2 Sep 2019 06:11:31 +0000 (16:11 +1000)]
Add a decode bit to mark an instruction as single through the pipeline
This is used by the pipelining patches. Mark everyone as single through
the pipeline to start.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Benjamin Herrenschmidt [Mon, 2 Sep 2019 22:44:01 +0000 (08:44 +1000)]
decode1 array fix header
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard [Mon, 9 Sep 2019 12:44:34 +0000 (22:44 +1000)]
Merge pull request #33 from antonblanchard/cr-fix
Fix CR forwarding
Anton Blanchard [Mon, 9 Sep 2019 12:21:30 +0000 (22:21 +1000)]
Merge pull request #32 from antonblanchard/register-file-forwarding
Add forwarding in the register file
Benjamin Herrenschmidt [Tue, 27 Aug 2019 14:09:45 +0000 (00:09 +1000)]
Use simulated UART in core test bench
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 27 Aug 2019 14:09:24 +0000 (00:09 +1000)]
Make sim poll non-blocking
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 27 Aug 2019 14:08:54 +0000 (00:08 +1000)]
Add simulated UART design
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard [Mon, 9 Sep 2019 12:16:11 +0000 (22:16 +1000)]
Fix CR forwarding
We weren't actually forwarding writes in the same cycle. Not a
problem right now, but noticed when testing the pipelining series.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 9 Sep 2019 06:36:47 +0000 (16:36 +1000)]
Add forwarding in the register file
We need this for the upcoming pipelining patches.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 9 Sep 2019 06:12:59 +0000 (16:12 +1000)]
Merge pull request #31 from antonblanchard/no-second-write-port-2
More second write port removal
Anton Blanchard [Mon, 9 Sep 2019 06:12:39 +0000 (16:12 +1000)]
Merge pull request #30 from antonblanchard/writeback-assert
Add some assertions to writeback
Anton Blanchard [Mon, 9 Sep 2019 06:00:49 +0000 (16:00 +1000)]
More second write port removal
I missed the register file updates for the second write port
removal.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 9 Sep 2019 05:54:09 +0000 (15:54 +1000)]
Add some assertions to writeback
We want to make sure we never complete more than one
instruction per cycle, or write back more than one GPR
or CR per cycle.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 9 Sep 2019 05:51:34 +0000 (15:51 +1000)]
Merge pull request #29 from antonblanchard/no-second-write-port
Remove second write port
Anton Blanchard [Mon, 9 Sep 2019 05:50:46 +0000 (15:50 +1000)]
Merge pull request #28 from antonblanchard/loadstore-cleanup
Remove some more loadstore debug
Anton Blanchard [Mon, 9 Sep 2019 05:18:09 +0000 (15:18 +1000)]
Remove second write port
We only need two write ports for load with update instructions.
Having two write ports just for this instruction is expensive.
For now we will force them to be the only instruction in the
pipeline, and take two cycles of writeback.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 9 Sep 2019 05:03:06 +0000 (15:03 +1000)]
Remove some more loadstore debug
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>