Clifford Wolf [Thu, 28 Nov 2013 20:34:41 +0000 (21:34 +0100)]
Added pattern support to "ls" command
Clifford Wolf [Thu, 28 Nov 2013 20:13:16 +0000 (21:13 +0100)]
Improved ID matching scheme in select (and thus for all commands)
Clifford Wolf [Thu, 28 Nov 2013 20:02:19 +0000 (21:02 +0100)]
Fixes and improvements in "show" command
Clifford Wolf [Thu, 28 Nov 2013 16:39:16 +0000 (17:39 +0100)]
More progress on AppNote 011
Clifford Wolf [Thu, 28 Nov 2013 16:37:50 +0000 (17:37 +0100)]
Added "src" attribute to processes
Clifford Wolf [Thu, 28 Nov 2013 12:48:38 +0000 (13:48 +0100)]
Started writing appnote 011
Clifford Wolf [Thu, 28 Nov 2013 12:35:28 +0000 (13:35 +0100)]
Added support for "show -pause" and "show -format dot"
Clifford Wolf [Thu, 28 Nov 2013 10:57:25 +0000 (11:57 +0100)]
Added QGraphicsWebView to yosys-svgviewer
Clifford Wolf [Wed, 27 Nov 2013 23:43:17 +0000 (00:43 +0100)]
Updated ABC to
9241719523f6
Clifford Wolf [Wed, 27 Nov 2013 19:43:42 +0000 (20:43 +0100)]
Added some svgviewer code for possible future switch to QGraphicsWebView
Clifford Wolf [Wed, 27 Nov 2013 08:08:42 +0000 (09:08 +0100)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Wed, 27 Nov 2013 08:08:35 +0000 (09:08 +0100)]
Tighter integration of ABC build
Clifford Wolf [Wed, 27 Nov 2013 05:29:13 +0000 (06:29 +0100)]
Set version number to 0.1.0+
Clifford Wolf [Mon, 25 Nov 2013 20:40:00 +0000 (21:40 +0100)]
Started implementing undef support in "sat" command
Clifford Wolf [Mon, 25 Nov 2013 20:08:34 +0000 (21:08 +0100)]
Bugfixes in new "stat" command
Clifford Wolf [Mon, 25 Nov 2013 19:43:57 +0000 (20:43 +0100)]
Added "stat" command
Clifford Wolf [Mon, 25 Nov 2013 15:50:45 +0000 (16:50 +0100)]
Improvements in satgen undef handling
Clifford Wolf [Mon, 25 Nov 2013 14:12:01 +0000 (15:12 +0100)]
Improvements in satgen undef handling
Clifford Wolf [Mon, 25 Nov 2013 14:10:32 +0000 (15:10 +0100)]
Added ezsat vec_const() api
Clifford Wolf [Mon, 25 Nov 2013 03:51:33 +0000 (04:51 +0100)]
Started implementing undef handling in satgen
Clifford Wolf [Mon, 25 Nov 2013 01:50:34 +0000 (02:50 +0100)]
Removed undef feature from ezsat api
Clifford Wolf [Sun, 24 Nov 2013 22:31:14 +0000 (23:31 +0100)]
Using simplemap mappers from techmap
Clifford Wolf [Sun, 24 Nov 2013 21:52:30 +0000 (22:52 +0100)]
Added simplemap pass
Clifford Wolf [Sun, 24 Nov 2013 19:44:00 +0000 (20:44 +0100)]
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
Clifford Wolf [Sun, 24 Nov 2013 19:29:07 +0000 (20:29 +0100)]
Added module->avail_parameters (for advanced techmap features)
Clifford Wolf [Sun, 24 Nov 2013 19:04:48 +0000 (20:04 +0100)]
Added techmap -D and -I options
Clifford Wolf [Sun, 24 Nov 2013 18:57:42 +0000 (19:57 +0100)]
Added verilog frontend -ignore_redef option
Clifford Wolf [Sun, 24 Nov 2013 18:50:25 +0000 (19:50 +0100)]
Added "techmap -share_map" option
Clifford Wolf [Sun, 24 Nov 2013 18:40:23 +0000 (19:40 +0100)]
Early wire/reg/parameter width calculation in ast/simplify
Clifford Wolf [Sun, 24 Nov 2013 16:58:05 +0000 (17:58 +0100)]
Updated TODOs
Clifford Wolf [Sun, 24 Nov 2013 16:55:46 +0000 (17:55 +0100)]
Fixed xilinx/example_sim_counter test bench
Clifford Wolf [Sun, 24 Nov 2013 16:47:22 +0000 (17:47 +0100)]
Added proper dumping of signed/unsigned parameters to verilog backend
Clifford Wolf [Sun, 24 Nov 2013 16:37:27 +0000 (17:37 +0100)]
Added support for signed parameters in ilang
Clifford Wolf [Sun, 24 Nov 2013 16:30:04 +0000 (17:30 +0100)]
Removed now obsolete test cases
Clifford Wolf [Sun, 24 Nov 2013 16:29:11 +0000 (17:29 +0100)]
Remove auto_wire framework (smarter than the verilog standard)
Clifford Wolf [Sun, 24 Nov 2013 16:17:21 +0000 (17:17 +0100)]
Implemented correct handling of signed module parameters
Clifford Wolf [Sun, 24 Nov 2013 14:10:43 +0000 (15:10 +0100)]
Added modelsim support to autotest
Clifford Wolf [Sun, 24 Nov 2013 13:10:46 +0000 (14:10 +0100)]
Fixed "flatten" top-module detection: Only use on fully selected designs
Clifford Wolf [Sun, 24 Nov 2013 04:05:50 +0000 (05:05 +0100)]
Fixed "make install" dependencies
Clifford Wolf [Sun, 24 Nov 2013 04:03:43 +0000 (05:03 +0100)]
Added "top" attribute to mark top module in hierarchy
Clifford Wolf [Sat, 23 Nov 2013 19:09:47 +0000 (20:09 +0100)]
Updated command-reference-manual.tex
Clifford Wolf [Sat, 23 Nov 2013 19:04:51 +0000 (20:04 +0100)]
AppNote 010 typo fixes and corrections
Clifford Wolf [Sat, 23 Nov 2013 16:33:26 +0000 (17:33 +0100)]
AppNote 010 progress
Clifford Wolf [Sat, 23 Nov 2013 15:49:58 +0000 (16:49 +0100)]
Improved handling of techmap special wires
Clifford Wolf [Sat, 23 Nov 2013 15:26:59 +0000 (16:26 +0100)]
Improved handling of initialized registers
Clifford Wolf [Sat, 23 Nov 2013 14:58:06 +0000 (15:58 +0100)]
Added more generic _TECHMAP_ wire mechanism to techmap pass
Clifford Wolf [Sat, 23 Nov 2013 04:46:51 +0000 (05:46 +0100)]
Making prograss on Appnote 010
Clifford Wolf [Fri, 22 Nov 2013 18:08:29 +0000 (19:08 +0100)]
Progress on AppNote 010
Clifford Wolf [Fri, 22 Nov 2013 16:33:59 +0000 (17:33 +0100)]
Started to write on AppNote 010: Verilog to BLIF
Clifford Wolf [Fri, 22 Nov 2013 14:02:40 +0000 (15:02 +0100)]
Updated command-reference-manual.tex
Clifford Wolf [Fri, 22 Nov 2013 14:01:12 +0000 (15:01 +0100)]
Renamed "placeholder" to "blackbox"
Clifford Wolf [Fri, 22 Nov 2013 13:53:57 +0000 (14:53 +0100)]
Some driver changes/fixes
Clifford Wolf [Fri, 22 Nov 2013 13:08:43 +0000 (14:08 +0100)]
Fixed O(n^2) performance bug in verilog preprocessor
Clifford Wolf [Fri, 22 Nov 2013 13:08:10 +0000 (14:08 +0100)]
Added more performance measurement infrastructure
Clifford Wolf [Fri, 22 Nov 2013 11:46:02 +0000 (12:46 +0100)]
Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)
Clifford Wolf [Fri, 22 Nov 2013 03:41:20 +0000 (04:41 +0100)]
Massive performance improvement from refactoring RTLIL::SigSpec::optimize()
Clifford Wolf [Fri, 22 Nov 2013 03:07:13 +0000 (04:07 +0100)]
Added SigBit struct and refactored RTLIL::SigSpec::extract
Clifford Wolf [Fri, 22 Nov 2013 03:05:30 +0000 (04:05 +0100)]
Improved make rules for profiling and debugging
Clifford Wolf [Thu, 21 Nov 2013 21:39:10 +0000 (22:39 +0100)]
Updated abc
Clifford Wolf [Thu, 21 Nov 2013 20:52:30 +0000 (21:52 +0100)]
Implemented $_DFFSR_ expression generator in verilog backend
Clifford Wolf [Thu, 21 Nov 2013 20:26:56 +0000 (21:26 +0100)]
Fixed async proc detection in mem2reg
Clifford Wolf [Thu, 21 Nov 2013 12:49:00 +0000 (13:49 +0100)]
Major improvements in mem2reg and added "init" sync rules
Clifford Wolf [Thu, 21 Nov 2013 02:01:20 +0000 (03:01 +0100)]
Fixed a bug in "add -global_input"
Clifford Wolf [Wed, 20 Nov 2013 20:00:43 +0000 (21:00 +0100)]
Added "proc_arst -global_arst" feature
Clifford Wolf [Wed, 20 Nov 2013 18:55:52 +0000 (19:55 +0100)]
Fixed ilang parser: memory width
Clifford Wolf [Wed, 20 Nov 2013 18:37:40 +0000 (19:37 +0100)]
Added "add" command (only wires for now)
Clifford Wolf [Wed, 20 Nov 2013 12:57:40 +0000 (13:57 +0100)]
Another name resolution bugfix for generate blocks
Clifford Wolf [Wed, 20 Nov 2013 12:05:27 +0000 (13:05 +0100)]
Implemented indexed part selects
Clifford Wolf [Wed, 20 Nov 2013 11:18:46 +0000 (12:18 +0100)]
Do not allow memory bit select on the left side of an assignment
Clifford Wolf [Wed, 20 Nov 2013 10:44:09 +0000 (11:44 +0100)]
Added "synthesis" in (synopsys|synthesis) comment support
Clifford Wolf [Wed, 20 Nov 2013 10:05:58 +0000 (11:05 +0100)]
Fixed name resolution of local tasks and functions in generate block
Clifford Wolf [Wed, 20 Nov 2013 09:51:32 +0000 (10:51 +0100)]
Implemented part/bit select on memory read
Clifford Wolf [Wed, 20 Nov 2013 01:10:48 +0000 (02:10 +0100)]
Updated TODOs in README file
Clifford Wolf [Wed, 20 Nov 2013 00:49:37 +0000 (01:49 +0100)]
Added init= attribute for fpga-style reset values
Clifford Wolf [Tue, 19 Nov 2013 22:13:41 +0000 (23:13 +0100)]
Added "make config-sudo"
Clifford Wolf [Tue, 19 Nov 2013 22:05:46 +0000 (23:05 +0100)]
Install simlib in datdir
Clifford Wolf [Tue, 19 Nov 2013 21:48:48 +0000 (22:48 +0100)]
Large improvements in yosys-config
Clifford Wolf [Tue, 19 Nov 2013 19:35:31 +0000 (20:35 +0100)]
Fixed parsing of module arguments when one type is used for many args
Clifford Wolf [Tue, 19 Nov 2013 00:03:57 +0000 (01:03 +0100)]
Renamed temp module generated by "abc" pass from "logic" to "netlist"
Clifford Wolf [Mon, 18 Nov 2013 18:55:39 +0000 (19:55 +0100)]
Added additional mem2reg testcase
Clifford Wolf [Mon, 18 Nov 2013 18:55:12 +0000 (19:55 +0100)]
Fixed two bugs in mem2reg functionality in AST frontend
Clifford Wolf [Mon, 18 Nov 2013 18:54:36 +0000 (19:54 +0100)]
Added dumping of attributes in AST frontend
Clifford Wolf [Mon, 18 Nov 2013 15:10:50 +0000 (16:10 +0100)]
Fixed parsing of default cases when not last case
Clifford Wolf [Mon, 18 Nov 2013 11:35:41 +0000 (12:35 +0100)]
Fixed mem2reg for reg usage outside always block
Clifford Wolf [Mon, 18 Nov 2013 11:01:00 +0000 (12:01 +0100)]
Added commented-out osu025 maping commands to cmos techmap example
Clifford Wolf [Sun, 17 Nov 2013 12:26:31 +0000 (13:26 +0100)]
Added -v<level> option and some minor driver cleanups
Clifford Wolf [Sat, 16 Nov 2013 14:17:32 +0000 (15:17 +0100)]
Renamed ABCHGPULL to ABCPULL in Makefile
Clifford Wolf [Wed, 13 Nov 2013 14:49:42 +0000 (15:49 +0100)]
Improved building of yosys-abc
Clifford Wolf [Wed, 13 Nov 2013 14:46:28 +0000 (15:46 +0100)]
Fixed abc pass blif parser for constant bits
Clifford Wolf [Wed, 13 Nov 2013 14:30:23 +0000 (15:30 +0100)]
Fixed parsing of "parameter integer"
Clifford Wolf [Sun, 10 Nov 2013 23:02:28 +0000 (00:02 +0100)]
Cleanups and bugfixes in response to new internal cell checker
Clifford Wolf [Sun, 10 Nov 2013 22:25:04 +0000 (23:25 +0100)]
Added information on all internal cell types to internal checker
Clifford Wolf [Sun, 10 Nov 2013 22:24:21 +0000 (23:24 +0100)]
Call internal checker more often
Clifford Wolf [Sat, 9 Nov 2013 11:02:27 +0000 (12:02 +0100)]
Improved user-friendliness of "sat" and "eval" expression parsing
Clifford Wolf [Sat, 9 Nov 2013 11:01:50 +0000 (12:01 +0100)]
Silenced a gcc warning in spice backend
Clifford Wolf [Sat, 9 Nov 2013 10:38:17 +0000 (11:38 +0100)]
Added verification of SAT model to "eval -vloghammer_report" command
Clifford Wolf [Fri, 8 Nov 2013 10:40:36 +0000 (11:40 +0100)]
More undef-propagation related fixes
Clifford Wolf [Fri, 8 Nov 2013 10:06:11 +0000 (11:06 +0100)]
Fixed handling of different signedness in power operands
Clifford Wolf [Fri, 8 Nov 2013 04:20:15 +0000 (05:20 +0100)]
Fixed keep attribute on wires in opt_clean
Clifford Wolf [Fri, 8 Nov 2013 03:44:09 +0000 (04:44 +0100)]
Implemented const folding of ternary op with undef select