anv: Make use of devinfo has_aux_map field

Reworks:
 * Use device rather than physical_device for info. (Lionel)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5572>

iris: Make use of devinfo has_aux_map field

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5572>

gitlab-ci: drop gettext from the build images

Suggested-by: Pierre-Eric Pelloux-Prayer <pelloux@gmail.com>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>

util: rename xmlpool.h to driconf.h

To make it clearer what it is and does.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>

driconf: drop now unused translation facility

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>

driconf: drop 9% swedish translation

Only 7 of the 72 strings are translated, and there doesn't seem to be
any effort to keep it updated.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>

driconf: drop 8% dutch translation

Only 6 of the 72 strings are translated, and there doesn't seem to be
any effort to keep it updated.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>

driconf: drop 6% french translation

Only 4 of the 72 strings are translated, and there doesn't seem to be
any effort to keep it updated.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>

driconf: drop 26% spanish translation

Only 19 of the 72 strings are translated, and there doesn't seem to be
any effort to keep it updated.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>

driconf: drop 15% german translation

Only 11 of the 72 strings are translated, and there doesn't seem to be
any effort to keep it updated.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>

driconf: drop 28% catalan translation

Only 20 of the 72 strings are translated, and there doesn't seem to be
any effort to keep it updated.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>

zink: use correct define value for reserved slot count in ntv

this is zero-indexed, so we need to include the zero index in the count

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5592>

intel/dev: Add device info for DG1

Reworks:
 * Anuj: Set is_dg1
 * Anuj: Add dg1 to gen_device_name_to_pci_device_id
 * Anuj: Update simulator id
 * Rafael: has_llc = false

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>

anv/dg1: Don't use SET_TILING kernel uapi.

It is not available on discrete platforms anymore.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>

iris/bufmgr: Do not use map_gtt or use set/get_tiling on DG1

We are starting to see platforms that don't support the get/set tiling
uAPI. (For example, DG1.)

Additionally on DG1 we shouldn't be using the map_gtt anymore.

Let's add some asserts and make sure we don't take those paths
accidentally.

Rework:
 * Jordan: Only apply for DG1, not all gen12
 * Rafael: Use has_tiling_uapi
 * Jordan: Copy has_tiling_uapi from devinfo
 * Jordan: merge in "iris: Rework iris_bo_import_dmabuf() a little."
 * Jordan: Continue to call get/set_tiling on modifier path

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>

intel/devinfo: Add function to check for DRM_I915_GEM_GET_TILING.

Future (discrete) platforms won't have support for get/set tiling. This
function allows our drivers to query for that, by simply trying to get
the tiling from a dummy buffer.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>

intel/l3: Return the URB size from devinfo for DG1

We don't have any URB size set in the L3 config, since it's a fixed
value now. So just return the value that we know from gen_device_info.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>

intel/isl: Update mocs for DG1

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>

intel/l3: Add DG1 L3 configuration

Reworks:
 * Jordan: Make DG1 L3 config table empty

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>

anv: Set L3 full way allocation at context init if L3 cfg is NULL

If the platform's default L3 config is NULL, then it now gets
initialized only at context init time, and cmd_buffer_config_l3 will
always return immediately.

Rework:
 * Remove unneeded check on !cfg in cmd_buffer_config_l3 (Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>

iris/l3: Enable L3 full way allocation when L3 config is NULL

Reworks:
 * Jordan: Check for cfg == NULL rather than is_dg1

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>

intel/l3: Allow platforms to have no l3 configurations

On some gen12 platforms we will use the L3FullWayAllocationEnable and
never reconfigure the L3 setup.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>

intel/l3: Don't rely on cfg entry URB size being 0 as a sentinal

An example entry with URB size being 0 is in the cnl list.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>

intel/devinfo: Add is_dg1 to device info

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>

turnip: Enable tessellationShader physical device feature

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>

ir3: Unconditionally enable MERGEDREGS on a6xx

As per discussion on !5059, we don't see any particular reason as to
why MERGEDREGS should be disabled on HS/DS/GS, and none of the dEQP
tests (both VK and GL) fail when MERGEDREGS is enabled. In fact, some
of the VK dEQP tests fail when MERGEDREGS is disabled (e.g. tests
with shaders that employ a0.x). As a result, let's just enable
MERGEDREGS unconditionally on a6xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>

turnip: Force sysmem for tessellation

Tessellation is incompatible with HW binning (dEQP tests fail when
we set forcebin), so force sysmem when we finish recording a command
buffer that uses a tess pipeline.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>

turnip: Support tess for draws

This commit adds tessellation support for draws. We store the IR3
patch type in tu_pipeline so we can use it in tu_emit_draw_*. We then
convert the IR3 patch type to the native adreno patch type and set
the appropriate reg values.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>

turnip: Emit HS/DS user consts as draw states

Just like VS/GS/FS.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>

turnip: Update VFD_CONTROL with tess system values

Support for TessCoord, PatchID, TCSHeader.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>

turnip: Allocate tess BOs as a function of draw size

To store tess outputs, the HS stg's into two buffers, one for
per-vertex/per-patch output variables (tess_param) and one for
TessLevelInner/Outer (tess_factor). The addresses of these buffers
are uploaded as consts to the HS/DS and the tess_factor iova is
written to REG_A6XX_PC_TESSFACTOR_ADDR. While the sizes of these
buffers are a function of vetex count and patch count, allocation is
relatively straightforward on freedreno- just keep track of the max
required buffer size for the entire batch and allocate before batch
submit.

In Vulkan, however, a given pipeline can be bound multiple times
across any number of command buffers, each drawing with a different
number of vertices. One solution is to track the max buffer size for
the entire command buffer (similar to fd_batch) and on
vkEndCommandBuffer, allocate appropriately sized tess BOs. Since the
tess BOs addresses are emitted as part of the pipeline state setup
(e.g. PKT4 to REG_A6XX_PC_TESSFACTOR_ADDR), we need to create a new
state group independent of a specific pipeline and parameterize its
IB with the command buffer specific tess BO iovas.

Without a larger refactor, the simplest way to do this is just to
emit per-draw call consts and leverage scratch_bo to re-use buffers.
This way we won't have to store and rewrite earlier packets in the
command stream on vkEndCommandBuffer.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>

turnip: Parse tess state and support PATCH primtype

This commit adds support for VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
primitive topologies.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>

turnip: Offset by component when lowering gl_TessLevel*

lower_tess_ctrl_block assumes that the gl_TessLevel*
intrinsic_store_outputs have already been collapsed into a single
instruction before the tess lowering step:

store_output ... /* base=0 */ /* wrmask=xyzw */ /* component=0 */
store_output ... /* base=1 */ /* wrmask=xy */ /* component=0 */

While this is true in fd because of st_nir_vectorize_io, we don't do
the same lowering in turnip so each tess level component still has
its own store instruction:

store_output ... /* base=0 */ /* wrmask=x */ /* component=0 */
store_output ... /* base=0 */ /* wrmask=x */ /* component=1 */
store_output ... /* base=0 */ /* wrmask=x */ /* component=2 */
store_output ... /* base=0 */ /* wrmask=x */ /* component=3 */
store_output ... /* base=1 */ /* wrmask=x */ /* component=0 */
store_output ... /* base=1 */ /* wrmask=x */ /* component=1 */

This commit adds a component offset to the tess control lowering. An
alternative is to also perform nir_lower_io_to_vector in turnip, but
ir3 seems to generate the same assembly either way and it's nice to
not have a lowering prereq before tess lowering.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>

turnip: Lower shaders for tessellation

To enable lowering of tess-related shaders, this commit sets the
tessellation primitive field of the ir3_shader_key. In addition,
this commit sets various tessellation flags for
spirv_to_nir configuration.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>

nir: Add an option for lowering TessLevelInner/Outer to vecs

The GLSL to NIR compiler supports the LowerTessLevel flag to convert
gl_TessLevelInner/Outer from their GLSL declarations as arrays of
floats to vec4/vec2s to better match how they are represented in
hardware.

This commit adds the similar support to the SPIR-V to NIR compiler so
turnip can use the same IR3/NIR tess lowering passes as freedreno.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>

nir: Support sysval tess levels in SPIR-V to NIR

This commit adds a tess_levels_are_sysvals flag to
spirv_to_nir_options similar to GLSLTessLevelsAsInputs in the GLSL to
NIR compiler options. This will be used by turnip as the tess IR3
lowering pass (ir3_nir_lower_tess) operates on TessLevelInner and
TessLevelOuter in the DS as sysvals.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>

v3d: Disable PIPE_CAP_PRIMITIVE_RESTART

The hardware can only support the PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX
subset. This will make it stop advertising the NV_primitive_restart
extension without breaking GLES 3.0 support.

v2: Update features.txt

Reviewed-by: Eric Anholt <eric@anholt.net> (v1)
Reviewed by: Erik Faye-Lund <erik.faye-lund@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5559>

mesa: Add PrimitiveRestartFixedIndex to gl_constants

This is a fine-grained subset of the NV_primitive_restart extension that
only uses the fixed indices provided by GLES 3.0. There’s no public
extension to advertise this behaviour so the bool is added to
gl_constants instead of gl_extensions.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed by: Erik Faye-Lund <erik.faye-lund@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5559>

gallium: Add pipe cap for primitive restart with fixed index

Adds PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX which is a subset of the
primitive restart cap for when the hardware can only support the fixed
indices specified in GLES.

The switch statements were automatically modified with this command:

find \( \( -name \*.cpp -o -name \*.c \) \! -type l \) \
 -exec sed -i -r \
 's/^(\s*case\s+PIPE_CAP_PRIMITIVE_RESTART)\s*:.*$/\0\n\1_FIXED_INDEX:/' \
 {} \;

v2: Add a note in screen.rst

Reviewed-by: Eric Anholt <eric@anholt.net> (v1)
Reviewed by: Erik Faye-Lund <erik.faye-lund@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5559>

nv50/ir/ra: fix memory corruption when spilling

When doing RA we end up with adding ValueDef references to Values across
all over the shader. This is all fine until we remove the Instruction
defining those Values, which happens when spilling values.

Instead of manipulating the values directly we should just track all
merged in defs in a seperate structure and remove stale references when
an instruction gets deleted in the spiller.

fixes following libasan report:
=================================================================
==612087==ERROR: AddressSanitizer: heap-use-after-free on address 0x6150003ea380 at pc 0x7f1d12142fe9 bp 0x7fffca6fd120 sp 0x7fffca6fd110
READ of size 8 at 0x6150003ea380 thread T0
    #0 0x7f1d12142fe8 in nv50_ir::ValueDef::get() const ../src/gallium/drivers/nouveau/codegen/nv50_ir.h:648
    #1 0x7f1d12143c02 in nv50_ir::Value::getUniqueInsn() const ../src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h:229
    #2 0x7f1d1221530d in nv50_ir::RegAlloc::BuildIntervalsPass::addLiveRange(nv50_ir::Value*, nv50_ir::BasicBlock const*, int) ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:333
    #3 0x7f1d1221872e in nv50_ir::RegAlloc::BuildIntervalsPass::visit(nv50_ir::BasicBlock*) ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:686
    #4 0x7f1d1215676c in nv50_ir::Pass::doRun(nv50_ir::Function*, bool, bool) ../src/gallium/drivers/nouveau/codegen/nv50_ir_bb.cpp:495
    #5 0x7f1d121563ed in nv50_ir::Pass::run(nv50_ir::Function*, bool, bool) ../src/gallium/drivers/nouveau/codegen/nv50_ir_bb.cpp:477
    #6 0x7f1d122262b8 in nv50_ir::RegAlloc::execFunc() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1910
    #7 0x7f1d122256b0 in nv50_ir::RegAlloc::exec() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1849
    #8 0x7f1d12226f1e in nv50_ir::Program::registerAllocation() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1970
    #9 0x7f1d1214092a in nv50_ir_generate_code ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:1275
    #10 0x7f1d1227461b in nvc0_program_translate ../src/gallium/drivers/nouveau/nvc0/nvc0_program.c:634
    #11 0x7f1d12294b21 in nvc0_sp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:620
    #12 0x7f1d12294d90 in nvc0_fp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:661
    #13 0x7f1d12ad4912 in st_create_fp_variant ../src/mesa/state_tracker/st_program.c:1498
    #14 0x7f1d12ad4cd5 in st_get_fp_variant ../src/mesa/state_tracker/st_program.c:1525
    #15 0x7f1d12ad8252 in st_precompile_shader_variant ../src/mesa/state_tracker/st_program.c:2053
    #16 0x7f1d12c9c851 in st_program_string_notify ../src/mesa/state_tracker/st_cb_program.c:185
    #17 0x7f1d12d17731 in st_link_tgsi ../src/mesa/state_tracker/st_glsl_to_tgsi.cpp:7441
    #18 0x7f1d12cabaf0 in st_link_shader ../src/mesa/state_tracker/st_glsl_to_ir.cpp:175
    #19 0x7f1d127c85ca in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3186
    #20 0x7f1d1252a9f7 in link_program ../src/mesa/main/shaderapi.c:1285
    #21 0x7f1d1252a9f7 in link_program_error ../src/mesa/main/shaderapi.c:1384
    #22 0x7f1d1252deb3 in _mesa_LinkProgram ../src/mesa/main/shaderapi.c:1876
    #23 0x403e13 in main._omp_fn.0 /home/kherbst/git/shader-db/run.c:926
    #24 0x7f1d17b8b4b5 in GOMP_parallel (/lib64/libgomp.so.1+0x124b5)
    #25 0x4029e4 in main /home/kherbst/git/shader-db/run.c:765
    #26 0x7f1d179b51a2 in __libc_start_main ../csu/libc-start.c:308
    #27 0x402d1d in _start (/home/kherbst/git/shader-db/run+0x402d1d)

0x6150003ea380 is located 0 bytes inside of 504-byte region [0x6150003ea380,0x6150003ea578)
freed by thread T0 here:
    #0 0x7f1d17e5d96f in operator delete(void*) (/usr/lib64/libasan.so.5.0.0+0x11096f)
    #1 0x7f1d1214ec0f in __gnu_cxx::new_allocator<nv50_ir::ValueDef>::deallocate(nv50_ir::ValueDef*, unsigned long) /usr/include/c++/9/ext/new_allocator.h:128
    #2 0x7f1d1214dc00 in std::allocator_traits<std::allocator<nv50_ir::ValueDef> >::deallocate(std::allocator<nv50_ir::ValueDef>&, nv50_ir::ValueDef*, unsigned long) /usr/include/c++/9/bits/alloc_traits.h:470
    #3 0x7f1d1214c5fb in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_M_deallocate_node(nv50_ir::ValueDef*) /usr/include/c++/9/bits/stl_deque.h:624
    #4 0x7f1d121498c4 in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_M_destroy_nodes(nv50_ir::ValueDef**, nv50_ir::ValueDef**) /usr/include/c++/9/bits/stl_deque.h:758
    #5 0x7f1d1214704d in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::~_Deque_base() /usr/include/c++/9/bits/stl_deque.h:680
    #6 0x7f1d12145371 in std::deque<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::~deque() /usr/include/c++/9/bits/stl_deque.h:1069
    #7 0x7f1d1213bc5b in nv50_ir::Instruction::~Instruction() ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:615
    #8 0x7f1d1213fb2f in nv50_ir::Program::releaseInstruction(nv50_ir::Instruction*) ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:1148
    #9 0x7f1d122250fb in nv50_ir::SpillCodeInserter::run(std::__cxx11::list<std::pair<nv50_ir::Value*, nv50_ir::Value*>, std::allocator<std::pair<nv50_ir::Value*, nv50_ir::Value*> > > const&) ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1830
    #10 0x7f1d12221445 in nv50_ir::GCRA::allocateRegisters(nv50_ir::ArrayList&) ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1541
    #11 0x7f1d122262e9 in nv50_ir::RegAlloc::execFunc() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1913
    #12 0x7f1d122256b0 in nv50_ir::RegAlloc::exec() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1849
    #13 0x7f1d12226f1e in nv50_ir::Program::registerAllocation() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1970
    #14 0x7f1d1214092a in nv50_ir_generate_code ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:1275
    #15 0x7f1d1227461b in nvc0_program_translate ../src/gallium/drivers/nouveau/nvc0/nvc0_program.c:634
    #16 0x7f1d12294b21 in nvc0_sp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:620
    #17 0x7f1d12294d90 in nvc0_fp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:661
    #18 0x7f1d12ad4912 in st_create_fp_variant ../src/mesa/state_tracker/st_program.c:1498
    #19 0x7f1d12ad4cd5 in st_get_fp_variant ../src/mesa/state_tracker/st_program.c:1525
    #20 0x7f1d12ad8252 in st_precompile_shader_variant ../src/mesa/state_tracker/st_program.c:2053
    #21 0x7f1d12c9c851 in st_program_string_notify ../src/mesa/state_tracker/st_cb_program.c:185
    #22 0x7f1d12d17731 in st_link_tgsi ../src/mesa/state_tracker/st_glsl_to_tgsi.cpp:7441
    #23 0x7f1d12cabaf0 in st_link_shader ../src/mesa/state_tracker/st_glsl_to_ir.cpp:175
    #24 0x7f1d127c85ca in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3186
    #25 0x7f1d1252a9f7 in link_program ../src/mesa/main/shaderapi.c:1285
    #26 0x7f1d1252a9f7 in link_program_error ../src/mesa/main/shaderapi.c:1384
    #27 0x7f1d1252deb3 in _mesa_LinkProgram ../src/mesa/main/shaderapi.c:1876
    #28 0x403e13 in main._omp_fn.0 /home/kherbst/git/shader-db/run.c:926

previously allocated by thread T0 here:
    #0 0x7f1d17e5c9d7 in operator new(unsigned long) (/usr/lib64/libasan.so.5.0.0+0x10f9d7)
    #1 0x7f1d1215046f in __gnu_cxx::new_allocator<nv50_ir::ValueDef>::allocate(unsigned long, void const*) /usr/include/c++/9/ext/new_allocator.h:114
    #2 0x7f1d1214ebec in std::allocator_traits<std::allocator<nv50_ir::ValueDef> >::allocate(std::allocator<nv50_ir::ValueDef>&, unsigned long) /usr/include/c++/9/bits/alloc_traits.h:444
    #3 0x7f1d1214dbd3 in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_M_allocate_node() /usr/include/c++/9/bits/stl_deque.h:617
    #4 0x7f1d1214c464 in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_M_create_nodes(nv50_ir::ValueDef**, nv50_ir::ValueDef**) (/home/kherbst/local/lib64/dri//nouveau_dri.so+0x829464)
    #5 0x7f1d121495cd in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_M_initialize_map(unsigned long) /usr/include/c++/9/bits/stl_deque.h:716
    #6 0x7f1d12146f7d in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_Deque_base() /usr/include/c++/9/bits/stl_deque.h:507
    #7 0x7f1d1214518d in std::deque<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::deque() /usr/include/c++/9/bits/stl_deque.h:912
    #8 0x7f1d1213b9c9 in nv50_ir::Instruction::Instruction(nv50_ir::Function*, nv50_ir::operation, nv50_ir::DataType) ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:605
    #9 0x7f1d1224dd44 in nv50_ir::Function::convertToSSA() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ssa.cpp:385
    #10 0x7f1d1224d381 in nv50_ir::Program::convertToSSA() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ssa.cpp:310
    #11 0x7f1d121407c0 in nv50_ir_generate_code ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:1264
    #12 0x7f1d1227461b in nvc0_program_translate ../src/gallium/drivers/nouveau/nvc0/nvc0_program.c:634
    #13 0x7f1d12294b21 in nvc0_sp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:620
    #14 0x7f1d12294d90 in nvc0_fp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:661
    #15 0x7f1d12ad4912 in st_create_fp_variant ../src/mesa/state_tracker/st_program.c:1498
    #16 0x7f1d12ad4cd5 in st_get_fp_variant ../src/mesa/state_tracker/st_program.c:1525
    #17 0x7f1d12ad8252 in st_precompile_shader_variant ../src/mesa/state_tracker/st_program.c:2053
    #18 0x7f1d12c9c851 in st_program_string_notify ../src/mesa/state_tracker/st_cb_program.c:185
    #19 0x7f1d12d17731 in st_link_tgsi ../src/mesa/state_tracker/st_glsl_to_tgsi.cpp:7441
    #20 0x7f1d12cabaf0 in st_link_shader ../src/mesa/state_tracker/st_glsl_to_ir.cpp:175
    #21 0x7f1d127c85ca in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3186
    #22 0x7f1d1252a9f7 in link_program ../src/mesa/main/shaderapi.c:1285
    #23 0x7f1d1252a9f7 in link_program_error ../src/mesa/main/shaderapi.c:1384
    #24 0x7f1d1252deb3 in _mesa_LinkProgram ../src/mesa/main/shaderapi.c:1876
    #25 0x403e13 in main._omp_fn.0 /home/kherbst/git/shader-db/run.c:926

SUMMARY: AddressSanitizer: heap-use-after-free ../src/gallium/drivers/nouveau/codegen/nv50_ir.h:648 in nv50_ir::ValueDef::get() const
Shadow bytes around the buggy address:
  0x0c2a80075420: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  0x0c2a80075430: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  0x0c2a80075440: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  0x0c2a80075450: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa
  0x0c2a80075460: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
=>0x0c2a80075470:[fd]fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd
  0x0c2a80075480: fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd
  0x0c2a80075490: fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd
  0x0c2a800754a0: fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fa
  0x0c2a800754b0: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
  0x0c2a800754c0: fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd
Shadow byte legend (one shadow byte represents 8 application bytes):
  Addressable:           00
  Partially addressable: 01 02 03 04 05 06 07
  Heap left redzone:       fa
  Freed heap region:       fd
  Stack left redzone:      f1
  Stack mid redzone:       f2
  Stack right redzone:     f3
  Stack after return:      f5
  Stack use after scope:   f8
  Global redzone:          f9
  Global init order:       f6
  Poisoned by user:        f7
  Container overflow:      fc
  Array cookie:            ac
  Intra object redzone:    bb
  ASan internal:           fe
  Left alloca redzone:     ca
  Right alloca redzone:    cb
  Shadow gap:              cc
==612087==ABORTING

v2: full rework
v3: manage a full copy instead of recreating new lists on every access

Closes: #3066
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5277>

nv50/ir/ra: convert some for loops to Range-based for loops

I will touch them in the next commit

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5277>

panfrost: Copy resources when mapping to avoid waiting for readers

It is often faster to copy the whole resource and modify that than
to flush and wait for readers of the BO.

Helps anything which updates textures after already using them in a
frame, such as most GLQuake ports.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5573>

panfrost: Update sampler views when the texture bo changes

The BO reallocation path in panfrost_transfer_map caused textures and
sampler views to get out of sync.

v2: Use the GPU address of the BO in case two BOs get allocated at the
    same address.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5573>

panfrost: RGBA4 and RGB5_A1 framebuffer support

Tested with fbo_firecube.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5573>

pan/mdg: Fix max_comp calculation for constant printing

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5573>

pan/decode: Add missing wrap modes

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5573>

pan/decode: Fix helper invocations when tracing

midgard1.flags_lo was being changed when tracing, causing helper
invocations to be disabled.

This was found by using mprotect to make BOs read only in
pandecode_fetch_gpu_mem.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5573>

r600/sfn: Don't set num_components on TESS sysvalue intrinsics

These instructions are not vectorized, and validation rules added for
this with 167fa2887f09
    nir/validate: validate intr->num_components

Fixes: 46a3033b43b9b51cae5c60eea39e7e5af325c4db
    r600/sfn: Emit some LDS instructions

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5575>

r600/sfn: Add support for shared atomics

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5575>

r600/sfn: Add lowering pass for shared IO

Lower shared load and store to use the r600 specific intrinsics.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5575>

nv50/ir/nir: rework CFG handling

Remove all convergency handling as it was broken and get the code to be a
bit closer to TGSI. Also removes pointless asserts.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>

nv50/ir/nir: rework input output handling

New code is a bit more structurized and fixes a bunch of int64 and double
fails. Also disables lower_to_scalar which gives us nice vectorized inputs
and outputs.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>

nv50/ir/nir: handle clip vertex for tess eval shaders

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>

nv50/ir/nir: don't emit a restart with set a stream_id

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>

nvc0: enable spirv caps with nir

This enables the SPIR-V GL extensions moving us a step closer to GL 4.6.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>

nv50/ir/nir: fix nv_viewport_array2

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>

nv50/ir/nir: fix ext_demote_to_helper_invocation

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>

nv50/ir/print: add missing VIEWPORT_MASK handling

Also add an STATIC_ASSERT so we catch those issues automatically.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>

nv50/ir/nir: add workaround for double vertex attribs

Gallium adjusts the vertrix attrib types for doubles, but can run out of
bounds this way. As the slot is counted from 0 anyway, just fix it.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>

aco: improve validation checks for readlane/writelane

This allows literals for the lane select on GFX10+. The doc says
that is should be a SGPR or a constant but VOP3 on GFX10+ allows
literals.

Some later validation code checks if literals are allowed anyways.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5010>

radv/aco: implement logic64 instead of lowering

to make use of the scalar ALU

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5527>

nir: slight correction to cube_face_coord constant folding

ACO does the division with a rcp and then a multiplication.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5547>

aco: fix printing ASM on GFX6-7 if clrxdisasm is not found

Fixes some dEQP-VK.pipeline.executable_properties.* which expect
a valid string to be returned.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5560>

v3d: Let scheduler know GS doesn’t have shared I/O memory

Unlike the vertex shaders, the memory for inputs and outputs is stored
in separate segments so the scheduler doesn’t need to serialise them.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5561>

nir/scheduler: Add an option to specify what stages share memory for I/O

The scheduler has code to handle hardware that shares the same memory
for inputs and outputs. Seeing as the specific stages that need this is
probably hardware-dependent, this patch makes it a configurable option
instead of hard-coding it to everything but fragment shaders.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5561>

nir/schedule: Store a pointer to the scoreboard in nir_deps_state

nir_deps_state is a struct used as a closure for calculating the
dependencies. Previously it had two fields copied out of the scoreboard.
The closure is initialised in two seperate places. In order to make it
easier to access other members of the scoreboard in the callbacks in
later patches, the closure now just contains a pointer to the scoreboard
and the two bits of copied information are removed.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5561>

v3d: Remove unused member of v3d_compile

It looks like gs_input_sizes was added when GS shaders were implemented
but it was never used anywhere.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5561>

nir/scheduler: Handle nir_intrinsic_load_per_vertex_input

load_per_vertex_input should probably be handled in the same way as a
regular load_input. I think the nir_schedule pass was written before V3D
had geometry shader support, so that is probably why it hasn’t taken
this into account until now.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5561>

gv100/ir: fix OP_TXG for shadow textures

doesn't seem to fix any tests now, but the previous code was obviously
incorrect and I still see fails in those CTS tests:

KHR-GL46.texture_gather.*depth*

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5576>

gv100/ir: fix shift lowering

Wrap was ignored. Also merge functions to share code.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5576>

gv100/ir: fix atom cas

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5576>

freedreno/a4xx: simplify setup_slices

Note: untested

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5132>

freedreno/a4xx: restore pitch to bytes change to layout code

I lost this change when rebasing the commit moving this.

Fixes: aa2186db0 ("freedreno: move a4xx specific layout code to a4xx code")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5132>

vulkan/wsi: Really terminate DRM lease in wsi_release_display().

wsi_release_display() implements vkReleaseDisplayEXT() which
is supposed to return control to the lessor of an output
upon call.

We need to terminate the wsi->wait_thread when close()'ing
the wsi->fd, otherwise the wait_thread holds another reference
to the wsi->fd, keeping the lease active, and thereby the
leased output blocked, until vkDestroyInstance() is called.

This gives users their GUI back, instead of extended darkness.

Fixes: 352d320a0745 ("vulkan: Add EXT_direct_mode_display [v2]")
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5396>

freedreno/ir3: split ubo analysis/lowering passes

Since binning pass variants share the same const_state with their
draw-pass counterpart, we should re-use the draw-pass variant's ubo
range analysis.  So split the two functions of the existing pass
into two parts.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5526>

freedreno/ir3: splitup get_existing_range()

This serves two purposes, one during ubo range analysis, where we want
to create new ranges, and another during the actual ubo lowering.  Split
these in two, with read-only ubo analysis state in the second case, to
prepare to split this pass in two.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5526>

freedreno/ir3: split out ubo info from range

Split out the description of the ubo from the ubo-range.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5526>

turnip: remove unnecessary OVERFLOW_FLAG_REG check

The HW deals with overflow automatically, and presumably does it better
(only disabling for pipes that had overflow, and using the visiblity data
available before the overflow)

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5565>

freedreno/a6xx: remove unnecessary OVERFLOW_FLAG_REG check

The HW deals with overflow automatically, and presumably does it better
(only disabling for pipes that had overflow, and using the visiblity data
available before the overflow)

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5565>

freedreno/a6xx: VSC "STRM_ARRAY_PITCH" is "STRM_LIMIT"

This was being set wrong in both freedreno and turnip, and setting it
correctly should avoid hangs when there is overflow.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5565>

radv: enable radv_no_dynamic_bounds for more Path of Exile executables

It looks like there's also a standalone version and a 32-bit version.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5574>

gallium/util: add missing include

This source-file uses PIPE_OS_WINDOWS to enable the Windows
functionality. But witout including p_config.h, this pre-processor
symbol won't be defined at all.

Let's fix this by adding the missing include, enabling stack-traces on
Windows.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5497>

gallium/util: limit STACK_LEN on Windows

The Windows implementation of debug_backtrace_capture has a limiation
of max 62 frames in total. Subtract a start-frame of 1 and the wrapping
functions frame, and we land at 60.

So let's lower this number on Windows to avoid triggering an assert.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5497>

graw/gdi: do not depend on UNICODE macro

Similar to the previous patch, we currently depend on the UNICODE macro
not being set, but it sometimes ends up getting set after all.

Unlike the previous patch, the easier thing to do here, is to lean into
the Unicode wrappers, and use the TEXT()-macro to define a Unicode
or ASCII literal, depending on the setting of the UNICODE macro.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5497>

gallium/os: call "ANSI" version of GetCommandLine

The GetCommandLine API comes in two versions, GetCommandLineA (which
returns "ANSI" results), and GetCommandLineW which returns UTF-16
("WIDE") results. Then finally, windows.h provides a wrapper-macro that
defines GetCommandLine to either of the two, based on the setting of
the UNICODE macro.

More information about this mechanism can be found here:
https://docs.microsoft.com/en-us/windows/win32/intl/unicode-in-the-windows-api

For some reason, the UNICODE macro is set during build, even if we're
not explicitly setting it. This leads to us trying to cast a UTF-16
result to a char-pointer, which is obviously not going to do the right
thing.

So let's be defensive, and just call GetCommandLineA directly instead.
This avoids us depending on the setting of the UNICODE-macro in the
first place.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5497>

intel/compiler: Always apply sample mask on Vulkan.

With OpenGL, shader writes to the sample mask are ignored when not
rendering to a multisample render target. However, on Vulkan, writes to
the sample mask have still have their effect in that case.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3016
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5156>

radv: enable radv_no_dynamic_bounds for Path of Exile

To workaround game bugs. This also enables it for the D3D11 renderer but
that shouldn't be an issue.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3081
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3084
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3080
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5569>

radv: add new drirc option radv_no_dynamic_bounds

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5569>

iris: Support I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5420>

iris: Refactor modifier_is_supported for gen12

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5420>

iris: Handle importing aux-enabled surfaces on TGL

Ensure main surfaces are properly 64KB-aligned (as suggested by Jordan)
and map the main surface addresses to aux surface addresses on import.

v2. Add a Bspec quote. (Sagar)
v3. Add a bit more to the Bspec comment. (Ken)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v2)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5420>

gallium/dri2: Support I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS

Add a case for this modifier in dri2_get_modifier_num_planes.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5420>

isl/drm: Support I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS

Add an entry for this modifier in the modifier_info array.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5420>

iris: Use ISL_AUX_USAGE_GEN12_CCS_E on gen12

Makes iris pass a subtest of the fcc-write-after-clear piglit test
(fast-clear tracking across layers 1 -> 0 -> 1) on gen12.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5363>

iris: Don't support sRGB + Y_TILED_CCS on gen9

Delete some code that would otherwise need updating for
ISL_AUX_USAGE_GEN12_CCS_E.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5363>

intel: Add ISL_AUX_USAGE_GEN12_CCS_E

Add a new aux usage which more accurately describes the behavior of
CCS_E on gen12. On this platform, writes using the 3D engine are either
compressed or substituted with fast-cleared blocks.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5363>

ci: Enable NIR validation on a630 GLES2 and VK tests.

We get through GLES2 in 5.5 minutes and the vk subset in 8 minutes, so we
can spare the CPU time on these tests.

Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5554>

ci: Bump vulkan CTS to 1.2.3.0.

Looks like it fixes some potentially important VK test bugs.  But also, it
fixes the GLES31 SSBO layout tests to not be so excessively large, so we
can run them in a reasonable time now.  Note that a630 fail list is reset,
since the test list has changed and so we end up with a different subset
of tests being run.  Interestingly, in the process the semaphore tests are
now reporting "NotSupported (Exporting and importing semaphore type not
supported at vktSynchronizationSignalOrderTests.cpp:513)" where they
weren't before.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5554>

iris: Disable sRGB fast-clears for non-0/1 values

For texturing and draw calls, HW expects the clear color to be in two
different color spaces after sRGB fast-clears - sRGB in the former and
linear in the latter. Up until now, iris has stored the clear color in
the sRGB color space. Limit the allowable clear colors for sRGB
fast-clears to 0/1 so that both color space requirements are satisfied.

Makes iris pass the sRGB -> sRGB subtest of the fcc-write-after-clear
piglit test on gen9+.

v2:
* Drop iris_context::blend_enables. (Ken)
* Drop some more resolve-related blend-state-tracking code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>

iris: Avoid fast-clear with incompatible view

For rendering operations, avoid adding or using fast-cleared blocks if
the render format is incompatible with the clear color interpretation.
Note that the clear color is currently interpreted through the
resource's surface format.

Makes iris pass subtests of the fcc-write-after-clear piglit test:

* UNORM -> SNORM, partial block on gen8+.
* linear -> sRGB, partial block on gen9+.
* UNORM -> SNORM, full block on gen12.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>