nir/lower_io: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_system_values: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_phis_to_scalar: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_indirect_derefs: fixup for new foreach_block()

v2 (Jason Ekstrand): Use nir_foreach_block_safe

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/nir_lower_global_vars: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_atomics: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_load_const: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_locals_to_regs: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_gs_intrinsics: fixup for new foreach_block()

v2 (Jason Ekstrand): Use nir_foreach_block_safe

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/nir: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_clip: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_alu_to_scalar: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/liveness: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/inline_functions: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/from_ssa: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/dominance: fixup for new foreach_block()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nvc0: stick compute kernel arguments into uniform_bo

Having one buffer object for input kernel arguments coming from clover
and an other one for OpenGL user uniforms is unnecessary. Using the
uniform_bo object for both GL/CL uniforms avoids to declare a new BO.

This only affects compute programs but it should not hurt anything
because the states are dirtied and data will get reuploaded.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

swr: remove duplicated constant update code

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

gallium/radeon: add the size only once in r600_context_add_resource_size

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

winsys/radeon: enlarge buffer_indices_hashlist

Enlarge the buffer hashlist to prevent large numbers of misses
due to adding more buffers than can be cached in the hashlist.

Ported from winsys/amdgpu: 6373845d985d65c00f7c62b793e67ae5106eabff

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

gallium/radeon: drop support for LINEAR_GENERAL layout

Unused. All texture imports use LINEAR_ALIGNED regardless of what
the DDX does.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: rework clear_buffer flags

Changes:
- don't flush DB for fast color clears
- don't flush any caches for initial clears
- remove the flag from si_copy_buffer, always assume shader coherency

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

anv/dynamic_offsets: Fix the order of arguments to nir_build_imm

anv: Fix a build error caused by recent fp64 NIR changes

nir: Try to warn when C99 extensions are used in nir headers.

Ideally we'd have nir.h being included with -Wpedantic too, but it fails
with:

src/compiler/nir/nir.h:754:20: warning: ISO C++ forbids zero-size array ‘src’ [-Wpedantic]
    nir_alu_src src[];
                    ^
In file included from src/compiler/nir/glsl_to_nir.cpp:42:0:
src/compiler/nir/nir.h:919:16: warning: ISO C++ forbids zero-size array ‘src’ [-Wpedantic]
    nir_src src[];

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: Remove spurious ; after nir_builder functions.

Makes -pedantic happy.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: Remove spurious ; after namespace.

Makes -pedantic happy.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: Avoid C99 field initializers.

As they are not standard C++ and are not supported by MSVC C++ compiler.

Just have nir_imm_double match nir_imm_float above.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>

gallium/util: s/Elements/ARRAY_SIZE/

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: improve comment on _mesa_check_disallowed_mapping(), return bool

The old comment was a bit terse.  Also, change the function return
type to bool.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

radeonsi: remove needless cache flushes at the end of CP DMA operations

not needed AFAIK

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove flushes at the beginning and end of IBs done by the kernel

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

nir: Add lrp lowering for doubles in opt_algebraic

Some hardware (i965 on Broadwell generation, for example) does not support
natively the execution of lrp instruction with double arguments.

Add 'lower_flrp64' flag to lower this instruction in that case.

v2:
   - Rename lower_flrp_double to lower_flrp64 (Jason)
   - Fix typo (Jason)
   - Adapt the code to define bit_size information in the opcodes.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: rename lower_flrp to lower_flrp32

A later patch will add lower_flrp64 option to NIR.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_double_ops: lower round_even()

At least i965 hardware does not have native support for round_even() on doubles.

Reviewed-by: Matt Turner <mattst88@gmail.com>

nir/lower_double_ops: lower fract()

At least i965 hardware does not have native support for fract() on doubles.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_double_ops: lower ceil()

At least i965 hardware does not have native support for ceil on doubles.

v2 (Sam):
   - Improve the lowering pass to remove one bcsel (Jason).

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_double_ops: lower floor()

At least i965 hardware does not have native support for floor on doubles.

v2 (Sam):
  - Improve the lowering pass to remove one bcsel (Jason)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_double_ops: lower trunc()

At least i965 hardware does not have native support for truncating doubles.

v2:
  - Simplified the implementation significantly.
  - Fixed the else branch, that was not doing what we wanted.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: add a pass to lower some double operations

v2: Move to compiler/nir (Iago)
v3: Use nir_imm_int() to load the constants (Sam)
v4 (Sam):
  - Undo line-wrap (Jason).
  - Fix comment (Jason).
  - Improve generated code for get_signed_inf() function (Connor).

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/builder: add nir_imm_double()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/builder: Add bit_size info to nir_build_imm()

v2:
- Group num_components and bit_size together (Jason)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

radeonsi: check if value is negative

Fixes a Coverity defect by adding checks to see if a value is negative
before using it to index an array. By checking the value first it makes
the code a bit safer but overall should not have a big impact.

CID: 1355598

Signed-off-by: Jakob Sinclair <sinclair.jakob@openmailbox.org>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

clover: Fix build against clang SVN >= r267772

(Re-pushing previous fix for clang SVN r265359, which was reverted in
the meantime)

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

glsl: fix lowering outputs for early/nested returns

Return statements in conditional blocks were not having their
output varyings lowered correctly.

This patch fixes the following piglit tests:
/spec/glsl-1.10/execution/vs-float-main-return
/spec/glsl-1.10/execution/vs-vec2-main-return
/spec/glsl-1.10/execution/vs-vec3-main-return

Signed-off-by: Lars Hamre <chemecse@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

nir: rewrite nir_foreach_block and friends

Previously, these were functions which took a callback. This meant that
the per-block code had to be in a separate function, and all the data
that you wanted to pass in had to be a single void *. They walked the
control flow tree recursively, doing a depth-first search, and called
the callback in a preorder, matching the order of the original source
code. But since each node in the control flow tree has a pointer to its
parent, we can implement a "get-next" and "get-previous" method that
does the same thing that the recursive function did with no state at
all. This lets us rewrite nir_foreach_block() as a simple for loop,
which lets us greatly simplify its users in some cases. This does
require us to rewrite every user, although the transformation from the
old nir_foreach_block() to the new nir_foreach_block() is mostly
trivial.

One subtlety, though, is that the new nir_foreach_block() won't handle
the case where the current block is deleted, which the old one could.
There's a new nir_foreach_block_safe() which implements the standard
trick for solving this. Most users don't modify control flow, though, so
they won't need it. Right now, only opt_select_peephole needs it.

The old functions are reimplemented in terms of the new macros, although
they'll go away after everything is converted.

v2: keep an implementation of the old functions around
v3 (Jason Ekstrand): A small cosmetic change and a bugfix in the loop
   handling of nir_cf_node_cf_tree_last().
v4 (Jason Ekstrand): Use the _safe macro in foreach_block_reverse_call

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/opt_cp: use nir_block_get_following_if()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

vbo: Return INVALID_OPERATION during draw with a mapped buffer

Fixes the OpenGLES 3.1 CTS:
 * ESEXT-CTS.draw_elements_base_vertex_tests.invalid_mapped_bos

Because this is triggering the error message after the normal API
validation phase, we don't have the API function name available, and
therefore we generate an error message without the draw call name:

Mesa: User error: GL_INVALID_OPERATION in draw call (vertex buffers are mapped)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95142
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

anv/formats: Return proper error code for unsupported formats

Fixes some failures in dEQP-VK.api.info.image_format_properties.* and
enables the test group to execute without assert failing.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94896
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/device: Set the compressed texture feature flags correctly

Sampling from an ETC2 texture is supported on Bay Trail and
from Gen8 onwards. While ASTC_LDR is supported on Gen9, the
logic to handle such formats has not yet been implemented in
the driver.

Fixes dEQP-VK.api.info.format_properties.compressed_formats.

v2: Enable ETC2 for Bay Trail (Kenneth Graunke)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94896
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir/algebraic: Add a bit-size validator

This commit adds a validator that ensures that all expressions passed
through nir_algebraic are 100% non-ambiguous as far as bit-sizes are
concerned.  This way it's a compile-time error rather than a hard-to-trace
C exception some time later.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

nir/opt_algebraic: Fix some expressions with ambiguous bit sizes

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir/search: Respect the bit_size parameter on nir_search_value

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir/algebraic: Add a mechanism for specifying the bit size of a value

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir/algebraic: Use "uint" instead of "unsigned" for uint types

This is consistent with the rename done for the rest of NIR.  Currently,
"bool" is the only type specifier used in nir_opt_algebraic.py so this is
really a no-op.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir/algebraic: Do better error reporting of bad expressions

Previously, if an exception was encountered anywhere, nir_algebraic would
just die in a fire with no indication whatsoever as to where the actual bug
is.  This commit makes it print out the particular search-and-replace
expression that is causing problems along with the exception.  Also, it
will now report all of the errors it finds and then exit at the end like a
standard C compiler would do.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

isl: move -lm at the end of tests_ldadd

The test was failing to build with "undefined reference to `roundf'" errors,
so Make check on mesa was failing.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965/blorp/gen8: Fix blitting of interleaved msaa surfaces

Fixes ES31-CTS.gtf.GL31Tests.texture_stencil8.texture_stencil8_multisample.

Current logic divides given layer of one by number of samples (four)
trashing the layer to zero. Layer adjustment is only to be used with
non-interleaved msaa surfaces where samples for particular layer are
in multiple slices.

I copy-pasted a bit of documentation from
brw_blorp.c::brw_blorp_compute_tile_offsets().

Also took the opportunity to fix the comment regarding sampling
as 2D, cube textures are the only exception.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

llvmpipe: s/Elements/ARRAY_SIZE/

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

tgsi: s/Elements/ARRAY_SIZE/

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

os: s/Elements/ARRAY_SIZE/

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

hud: s/Elements/ARRAY_SIZE/

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

gallivm: s/Elements/ARRAY_SIZE/

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

draw: s/Elements/ARRAY_SIZE/

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

softpipe: s/Elements/ARRAY_SIZE/

Try to standardize on the later, which is defined in the common util/
directory.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

winsys/radeon: remove use_reusable_pool parameter from buffer_create

All callers set this parameter to true.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: remove use_reusable_pool parameter from r600_init_resource

All callers set it to true.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeon/video: always use the reusable buffer pool

A semantic error was introduced in a past refactoring that caused the bind
parameter to be passed into the use_reusable_pool parameter of buffer_create.
Since this clearly makes no sense, and there is no clear reason why the
cache _shouldn't_ be used, just use the cache always.

Cc: Christian König <christian.koenig@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: work around an MSAA fast stencil clear problem

A piglit test (arb_texture_multisample-stencil-clear) has been sent.
This problem was discovered analyzing

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93767
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: expclear must be disabled on first Z/S clear

The documentation and the HW team say so.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: move blend choice out of loop in si_blit_decompress_color

It does not depend on the level or layer.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: use level mask for early out in si_blit_decompress_color

Mostly for consistency with the other decompress functions, but note that
in the non-DCC decompress case, the function can now early-out in slightly
more (albeit probably rare) cases.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: si_blit_decompress_depth is only used for staging

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: only decompress the required ZS planes from si_blit

This happens to "fix" a rendering bug in KotOR2, because it avoids a still
not quite understood bug with MSAA fast stencil clear decompress. For the
stencil clear bug, I have sent a piglit test (arb_texture_multisample-stencil-clear).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93767
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: decompress Z & S planes in one pass

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: early out of si_blit_decompress_depth_in_place based on dirty mask

Avoid dirtying the db_render_state atom when possible.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: use MIN2 instead of expanded ?: operator

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: fix brace style

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/util: add u_bit_consecutive for generating a consecutive range of bits

There are some undefined behavior subtleties, so having a function to match
the u_bit_scan_consecutive_range makes sense.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

swr: s/Elements/ARRAY_SIZE/

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

radeonsi: emit s_waitcnt for shader memory barriers and volatile

Turns out that this is needed after all to satisfy some strengthened
coherency tests. Depends on support in LLVM, added in r267729.

v2: updated to reflect changes to the LLVM intrinsic

Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)

swr: [rasterizer] warning cleanup

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] implement legacy depth bias enable

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer jitter] support for dumping x86 asm

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] more backend refactoring

BackendPixelRate should be easier to read/maintain now hopefully.

Small perf bump by moving some of the pfn's to inline functions
without template params.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer jitter] add mSimdInt1Ty

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] backend refactor

Lump all template args into a bundle of traits, and add some
functionality to the MSAA traits.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

svga: use the SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS query

Instead of a hard-coded 512.  The query typically returns 65536 now.
Fall back to 512 if the query fails as we do for vertex shaders (which
should never happen).

Note that we don't actually enforce this limit in our shaders but it gets
reported via the glGetProgramivARB(GL_MAX_PROGRAM_INSTRUCTIONS_ARB) query.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

nouveau: codegen: LOAD: Take src swizzle into account

The llvm TGSI backend uses pointers in registers and does things
like:

LOAD TEMP[0].y, MEMORY[0], TEMP[0]

Expecting the data at address TEMP[0].x to get loaded to
TEMP[0].y. But this will cause the data at TEMP[0].x + 4 to be
loaded instead.

This commit adds support for a swizzle suffix for the 1st source
operand, which allows using:

LOAD TEMP[0].y, MEMORY[0].xxxx, TEMP[0]

And actually getting the desired behavior

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nouveau: codegen: LOAD: Do not call fetchSrc(1) if the address is immediate

"off" later gets set to NULL when the address is immediate, so move the
fetchSrc(1) call to the non-immediate branch of the if-else. This brings
handleLOAD's offset handling inline with how it is done in handleSTORE.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nouveau: codegen: LOAD: Always use component 0 when getting the address

LOAD loads upto 4 components from the specified resource starting at
the passed in x value of the 2nd source operand, the y, z and w
components of the address should not be used.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

dri3: Check for dummyContext to see if the glx_context is valid

According to the comments in src/glx/glxcurrent.c __glXGetCurrentContext()
always returns a valid pointer. If no context is made current, it will
contain dummyContext. Thus a test for NULL will always fail.

https://lists.freedesktop.org/archives/mesa-dev/2016-April/113962.html

Signed-off-by: Stefan Dirsch <sndirsch@suse.de>
Reviewed-by: Egbert Eich <eich@freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

dri2: Check for dummyContext to see if the glx_context is valid

According to the comments in src/glx/glxcurrent.c __glXGetCurrentContext()
always returns a valid pointer. If no context is made current, it will
contain dummyContext. Thus a test for NULL will always fail.

https://bugzilla.opensuse.org/show_bug.cgi?id=962609

Tested-by: Olaf Hering <ohering@suse.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

glsl: move uniform block validation to link_uniform_blocks.cpp

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

docs: Mention that {ARB,OES}_texture_stencil8 is supported on i965/gen8+

Thanks to Thomas Helland for reminding me to do this.

i965: Enable ARB_texture_stencil8 and OES_texture_stencil8 on Gen8+.

Stencil texturing is required by ES 3.1.  Apparently we never actually
turned it on.  Do that now.  Also turn on the desktop extension.

Fixes nine dEQP-GLES31.functional tests:

stencil_texturing.format.stencil_index8_2d
texture.border_clamp.formats.stencil_index8.nearest_size_pot
texture.border_clamp.formats.stencil_index8.nearest_size_npot
texture.border_clamp.formats.stencil_index8.gather_size_pot
texture.border_clamp.formats.stencil_index8.gather_size_npot
texture.border_clamp.unused_channels.stencil_index8
state_query.internal_format.renderbuffer.stencil_index8_samples
state_query.internal_format.texture_2d_multisample.stencil_index8_samples
state_query.internal_format.texture_2d_multisample_array.stencil_index8_samples

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

mesa: Try to fix CopyTex[Sub]Image of stencil textures.

ES prohibits this, but GL appears to allow it.  We at least need this
much, or else we'll crash as there's no source to read from.

This fixed crashes in the ES tests before I realized I needed to
prohibit stencil instead.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

mesa: Disallow CopyTexSubImage on stencil formats in ES.

Fixes
- ES31-CTS.gtf.GL31Tests.texture_stencil8.texture_stencil8
- ES31-CTS.gtf.GL31Tests.texture_stencil8.texture_stencil8_multisample

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Fix MapTextureImage for multi-slice/level stencil buffers.

We called intel_miptree_get_image_offset() to get the image offsets
for the current level/slice, but then proceeded to ignore the results
and clobber level/slice 0 every time.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94713
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Move TCS output indirect_offset.file check out a level.

I want to add another condition.  Moving the indirect_offset.file
check out a level should make this a little easier.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>