Nilay Vaish [Tue, 18 Jan 2011 00:46:16 +0000 (18:46 -0600)]
Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.
I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.
Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.
Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.
All the protocols have been modified to conform with the new interface.
Gabe Black [Sat, 15 Jan 2011 23:30:34 +0000 (15:30 -0800)]
SPARC: Update stats for the call r15 as source change.
Gabe Black [Sat, 15 Jan 2011 23:30:17 +0000 (15:30 -0800)]
SPARC: Adjust the "call" instruction so R15 doesn't get marked as a source.
Nilay Vaish [Fri, 14 Jan 2011 04:48:03 +0000 (22:48 -0600)]
Regression Tests: Update the output for MESI_CMP_directory
This patch updates the output for regression tests that are carried out on
MESI_CMP_directory protocol. The changes made to the protocol in order to
remove the bugs present result in regression failure for the 60.rubytest.
Since the earlier protocol was incorrect, so we certainly cannot relay on the
earlier reference output. Hence, the update.
Nilay Vaish [Fri, 14 Jan 2011 04:17:11 +0000 (22:17 -0600)]
Ruby: Fixes MESI CMP directory protocol
The current implementation of MESI CMP directory protocol is broken.
This patch, from Arkaprava Basu, fixes the protocol.
Gabe Black [Thu, 13 Jan 2011 20:30:18 +0000 (12:30 -0800)]
Style checker: Fix a couple bugs in style.py.
Korey Sewell [Wed, 12 Jan 2011 16:52:29 +0000 (11:52 -0500)]
inorder: fix RUBY_FS build
the current code was using incorrect dummy instruction in interrupts function
Nathan Binkert [Mon, 10 Jan 2011 19:11:20 +0000 (11:11 -0800)]
ruby: get rid of ruby's Debug.hh
Get rid of the Debug class
Get rid of ASSERT and use assert
Use DPRINTFR for ProtocolTrace
Nathan Binkert [Mon, 10 Jan 2011 19:11:17 +0000 (11:11 -0800)]
stats: Add a histogram statistic type
Nathan Binkert [Mon, 10 Jan 2011 19:11:17 +0000 (11:11 -0800)]
stats: fix stat test from curTick change
Nathan Binkert [Mon, 10 Jan 2011 19:11:16 +0000 (11:11 -0800)]
stats: fix the distribution stat
Nathan Binkert [Mon, 10 Jan 2011 19:11:16 +0000 (11:11 -0800)]
style: prevent the style hook from aborting uncleanly because of an exception
Nathan Binkert [Mon, 10 Jan 2011 19:11:15 +0000 (11:11 -0800)]
style: clean up style hook code a bit
I've renamed the check_whitespace operation to check_style. You're going to
need to change your .hg/hgrc file. While you're at it, add a pre-qrefresh
hook please.
Gabe Black [Mon, 10 Jan 2011 12:53:34 +0000 (04:53 -0800)]
Root: Get rid of unnecessary includes in root.cc.
Gabe Black [Mon, 10 Jan 2011 12:53:20 +0000 (04:53 -0800)]
Curtick: Fix mysql.cc build needing curTick.
Gabe Black [Mon, 10 Jan 2011 11:56:42 +0000 (03:56 -0800)]
RefCount: Add a unit test for reference counting pointers.
This test exercises each of the functions in the reference counting pointer
implementation individually (except get()) and verifies they have some
minimially expected behavior. It also checks that reference counted objects
are freed when their usage count goes to 0 in some basic situations,
specifically a pointer being set to NULL and a pointer being deleted.
Steve Reinhardt [Sat, 8 Jan 2011 05:50:29 +0000 (21:50 -0800)]
Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
Steve Reinhardt [Sat, 8 Jan 2011 05:50:29 +0000 (21:50 -0800)]
stats: rename StatEvent() function to schedStatEvent().
This follows the style rules and is more descriptive.
Steve Reinhardt [Sat, 8 Jan 2011 05:50:29 +0000 (21:50 -0800)]
sim: clean up CountedDrainEvent slightly.
There's no reason for it to derive from SimLoopExitEvent.
This whole drain thing needs to be redone eventually,
but this is a stopgap to make later changes to
SimLoopExitEvent feasible.
Steve Reinhardt [Sat, 8 Jan 2011 05:50:29 +0000 (21:50 -0800)]
sim: delete unused CheckSwapEvent code.
There's no way to even create one of these anymore.
Steve Reinhardt [Sat, 8 Jan 2011 05:50:29 +0000 (21:50 -0800)]
pseudoinst: get rid of mainEventQueue references.
Avoid direct references to mainEventQueue in pseudo-insts
by indirecting through associated CPU object.
Made exitSimLoop() more flexible to enable some of these.
Steve Reinhardt [Sat, 8 Jan 2011 05:50:29 +0000 (21:50 -0800)]
inorder: replace schedEvent() code with reschedule().
There were several copies of similar functions that looked
like they all replicated reschedule(), so I replaced them
with direct calls. Keeping this separate from the previous
cset since there may be some subtle functional differences
if the code ever reschedules an event that is scheduled but
not squashed (though none were detected in the regressions).
Steve Reinhardt [Sat, 8 Jan 2011 05:50:29 +0000 (21:50 -0800)]
inorder: get rid of references to mainEventQueue.
Events need to be scheduled on the queue assigned
to the SimObject, not on the global queue (which
should be going away).
Also cleaned up a number of redundant expressions
that made the code unnecessarily verbose.
Steve Reinhardt [Sat, 8 Jan 2011 05:50:13 +0000 (21:50 -0800)]
scons: show sources and targets when building, and colorize output.
I like the brevity of Ali's recent change, but the ambiguity of
sometimes showing the source and sometimes the target is a little
confusing. This patch makes scons typically list all sources and
all targets for each action, with the common path prefix factored
out for brevity. It's a little more verbose now but also more
informative.
Somehow Ali talked me into adding colors too, which is a whole
'nother story.
Nilay Vaish [Wed, 5 Jan 2011 03:40:49 +0000 (21:40 -0600)]
Ruby: Updates MOESI Hammer protocol
This patch changes the manner in which data is copied from L1 to L2 cache in
the implementation of the Hammer's cache coherence protocol. Earlier, data was
copied directly from one cache entry to another. This has been broken in to
two parts. First, the data is copied from the source cache entry to a
transaction buffer entry. Then, data is copied from the transaction buffer
entry to the destination cache entry.
This has been done to maintain the invariant - at any given instant, multiple
caches under a controller are exclusive with respect to each other.
Gabe Black [Tue, 4 Jan 2011 22:11:49 +0000 (17:11 -0500)]
Params: Print the IP components in the right order.
Steve Reinhardt [Mon, 3 Jan 2011 22:35:47 +0000 (14:35 -0800)]
Move sched_list.hh and timebuf.hh from src/base to src/cpu.
These files really aren't general enough to belong in src/base.
This patch doesn't reorder include lines, leaving them unsorted
in many cases, but Nate's magic script will fix that up shortly.
--HG--
rename : src/base/sched_list.hh => src/cpu/sched_list.hh
rename : src/base/timebuf.hh => src/cpu/timebuf.hh
Steve Reinhardt [Mon, 3 Jan 2011 22:35:45 +0000 (14:35 -0800)]
Delete unused files from src/base directory.
Steve Reinhardt [Mon, 3 Jan 2011 22:35:43 +0000 (14:35 -0800)]
Make commenting on close namespace brackets consistent.
Ran all the source files through 'perl -pi' with this script:
s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;
Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
Gabe Black [Mon, 3 Jan 2011 20:31:20 +0000 (15:31 -0500)]
RefCount: Fix reference counting pointer == and != with a T* on the left.
These operators were expecting a const T& instead of a const T*, and were not
being picked up and used by gcc in the right places as a result. Apparently no
one used these operators before. A unit test which exposed these problems,
verified the solution, and checks other basic functionality is on the way.
Nilay Vaish [Mon, 3 Jan 2011 18:40:31 +0000 (12:40 -0600)]
Ruby: Add option for random seed to Ruby.py
This patch adds an option to the script Ruby.py for setting the parameter
m_random_seed used for randomizing delays in the memory system. The option
can be specified as "--random_seed <seed value>".
Nathan Binkert [Thu, 30 Dec 2010 17:51:04 +0000 (12:51 -0500)]
swig: use <> for system %includes instead of ""
Nathan Binkert [Thu, 30 Dec 2010 17:53:56 +0000 (12:53 -0500)]
style: make style hook work with pre-qrefresh and update to use new code
clean up the code a little bit while we're at it.
I recommend that everyone adds the pre-qrefresh hook below since it
will make qref run the style hook and not just commit/qpush
[extensions]
style = <m5 path>/util/style.py
[hooks]
pretxncommit.style = python:style.check_whitespace
pre-qrefresh.style = python:style.check_whitespace
Nilay Vaish [Thu, 23 Dec 2010 19:36:18 +0000 (13:36 -0600)]
PerfectCacheMemory: Add return statements to two functions.
Two functions in src/mem/ruby/system/PerfectCacheMemory.hh, tryCacheAccess()
and cacheProbe(), end with calls to panic(). Both of these functions have
return type other than void. Any file that includes this header file fails
to compile because of the missing return statement. This patch adds dummy
values so as to avoid the compiler warnings.
Nilay Vaish [Thu, 23 Dec 2010 05:15:24 +0000 (23:15 -0600)]
This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh file. These statements have been replaced with warn(), panic() and fatal() defined in src/base/misc.hh
Steve Reinhardt [Wed, 22 Dec 2010 06:57:29 +0000 (22:57 -0800)]
memtest: delete some crufty dead code
Steve Reinhardt [Wed, 22 Dec 2010 06:39:26 +0000 (22:39 -0800)]
Get rid of unused file src/base/dbl_list.hh
Nathan Binkert [Tue, 21 Dec 2010 16:02:41 +0000 (08:02 -0800)]
stats: allow stats to be reset even if no objects have been instantiated
Nathan Binkert [Tue, 21 Dec 2010 16:02:40 +0000 (08:02 -0800)]
importer: fix error message
Nathan Binkert [Tue, 21 Dec 2010 16:02:39 +0000 (08:02 -0800)]
scons: remove extra dependencies
Gabe Black [Mon, 20 Dec 2010 21:24:40 +0000 (16:24 -0500)]
Style: Replace some tabs with spaces.
Gabe Black [Mon, 20 Dec 2010 09:20:58 +0000 (04:20 -0500)]
Params: Fix a broken error message in verifyIp.
Gabe Black [Thu, 9 Dec 2010 22:45:17 +0000 (14:45 -0800)]
ARM: Take advantage of new PCState syntax.
Gabe Black [Thu, 9 Dec 2010 22:45:04 +0000 (14:45 -0800)]
ARM: Get rid of some unused FP operands.
Gabe Black [Thu, 9 Dec 2010 00:52:38 +0000 (16:52 -0800)]
Merge.
Brad Beckmann [Wed, 8 Dec 2010 19:52:02 +0000 (11:52 -0800)]
ruby: remove Ruby asserts for m5.fast
This diff is for changing the way ASSERT is handled in Ruby. m5.fast
compiles out the assert statements by using the macro NDEBUG. Ruby uses the
macro RUBY_NO_ASSERT to do so. This macro has been removed and NDEBUG has
been put in its place.
Gabe Black [Wed, 8 Dec 2010 18:55:33 +0000 (10:55 -0800)]
Alpha: Take advantage of new PCState syntax.
Gabe Black [Wed, 8 Dec 2010 18:45:14 +0000 (10:45 -0800)]
MIPS: Take advantage of new PCState syntax.
Gabe Black [Wed, 8 Dec 2010 18:33:03 +0000 (10:33 -0800)]
POWER: Take advantage of new PCState syntax.
Gabe Black [Wed, 8 Dec 2010 08:27:43 +0000 (00:27 -0800)]
SPARC: Take advantage of new PCState syntax.
Gabe Black [Wed, 8 Dec 2010 08:27:23 +0000 (00:27 -0800)]
X86: Take advantage of new PCState syntax.
Gabe Black [Wed, 8 Dec 2010 07:08:05 +0000 (23:08 -0800)]
ISA: Get the parser to support pc state components more elegantly.
Ali Saidi [Wed, 8 Dec 2010 00:19:57 +0000 (16:19 -0800)]
Configs: Automatically choose the correct hello world binary.
Ali Saidi [Wed, 8 Dec 2010 00:19:57 +0000 (16:19 -0800)]
O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).
The store queue doesn't need to be ISA specific and architectures can
frequently store more than an int registers worth of data. A 128 bits seems
more common, but even 256 bits may be appropriate. Pretty much anything less
than a cache line size is buildable.
Ali Saidi [Wed, 8 Dec 2010 00:19:57 +0000 (16:19 -0800)]
Stats: Fix stats for cumulative flags change.
Ali Saidi [Wed, 8 Dec 2010 00:19:57 +0000 (16:19 -0800)]
O3: Support squashing all state after special instruction
For SPARC ASIs are added to the ExtMachInst. If the ASI is changed simply
marking the instruction as Serializing isn't enough beacuse that only
stops rename. This provides a mechanism to squash all the instructions
and refetch them
Giacomo Gabrielli [Wed, 8 Dec 2010 00:19:57 +0000 (16:19 -0800)]
O3: Make all instructions that write a misc. register not perform the write until commit.
ARM instructions updating cumulative flags (ARM FP exceptions and saturation
flags) are not serialized.
Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed
write accesses to the FP condition codes for most ARM VFP instructions: only
VCMP and VCMPE instructions update the FP condition codes. Removed a potential
cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).
Min Kyu Jeong [Wed, 8 Dec 2010 00:19:57 +0000 (16:19 -0800)]
O3: Support SWAP and predicated loads/store in ARM.
Ali Saidi [Wed, 8 Dec 2010 00:19:57 +0000 (16:19 -0800)]
ARM: Support switchover with hardware table walkers
Nilay Vaish [Wed, 1 Dec 2010 19:30:04 +0000 (11:30 -0800)]
ruby: Converted old ruby debug calls to M5 debug calls
This patch developed by Nilay Vaish converts all the old GEMS-style ruby
debug calls to the appropriate M5 debug calls.
Ali Saidi [Sat, 27 Nov 2010 01:47:23 +0000 (20:47 -0500)]
IGbE: return 0 on an invalid descriptor size instead of -1.
Asserts where descSize() get called with assert if we end up returning
0.
Gabe Black [Tue, 23 Nov 2010 22:08:41 +0000 (17:08 -0500)]
Copyright: Add AMD copyright to the param changes I just made.
Gabe Black [Tue, 23 Nov 2010 20:54:43 +0000 (15:54 -0500)]
Params: Add parameter types for IP addresses in various forms.
New parameter forms are:
IP address in the format "a.b.c.d" where a-d are from decimal 0 to 255.
IP address with netmask which is an IP followed by "/n" where n is a netmask
length in bits from decimal 0 to 32 or by "/e.f.g.h" where e-h are from
decimal 0 to 255 and which is all 1 bits followed by all 0 bits when
represented in binary. These can also be specified as an integral IP and
netmask passed in separately.
IP address with port which is an IP followed by ":p" where p is a port index
from decimal 0 to 65535. These can also be specified as an integral IP and
port value passed in separately.
Gabe Black [Tue, 23 Nov 2010 11:11:50 +0000 (06:11 -0500)]
X86: Loosen an assert for x86 and connect the APIC ports when caches are used.
Gabe Black [Tue, 23 Nov 2010 11:10:17 +0000 (06:10 -0500)]
X86: Obey the PCD (cache disable) bit in the page tables.
Gabe Black [Mon, 22 Nov 2010 10:49:03 +0000 (05:49 -0500)]
X86: Mark IO space accesses as uncachable.
Gabe Black [Mon, 22 Nov 2010 10:47:54 +0000 (05:47 -0500)]
X86: Remove reserved* from the m5 utility program for x86.
Gabe Black [Mon, 22 Nov 2010 07:33:47 +0000 (02:33 -0500)]
IDE,X86: Fix IDE controller BAR configuration for x86.
Nathan Binkert [Sat, 20 Nov 2010 20:12:27 +0000 (12:12 -0800)]
random: small comment about our random number generator and its origin
Ali Saidi [Sat, 20 Nov 2010 00:01:01 +0000 (18:01 -0600)]
SE: Fix simulating more than 4GB of RAM in SE mode
This change removes some dead code in PhysicalMemory, uses a 64 bit type
for the page pointer in System (instead of 32 bit) and cleans up some style.
Ali Saidi [Sat, 20 Nov 2010 00:00:59 +0000 (18:00 -0600)]
SCons: Fix compilation on OS X
Ali Saidi [Sat, 20 Nov 2010 00:00:39 +0000 (18:00 -0600)]
SCons: Support building without an ISA
Gabe Black [Thu, 18 Nov 2010 18:11:36 +0000 (13:11 -0500)]
O3: Fix fp destination register flattening, and index offset adjusting.
This change makes O3 flatten floating point destination registers, and also
fixes misc register flattening so that it's correctly repositioned relative to
the resized regions for integer and floating point indices.
It also fixes some overly long lines.
Gabe Black [Thu, 18 Nov 2010 04:16:19 +0000 (23:16 -0500)]
Config: Change misleading "cycle" message to say "tick".
Most of the messages in the config scripts that report a time value already
print "@ tick" followed by the current tick value, but a few were printing
"@ cycle". Since this is a distinction that's frequently confusing to new
users, this changes those message to the more accurate and consistent "@ tick".
Gabe Black [Tue, 16 Nov 2010 03:37:15 +0000 (19:37 -0800)]
Stats: Update the O3 fetch stats for SPARC.
Gabe Black [Tue, 16 Nov 2010 03:37:03 +0000 (19:37 -0800)]
O3: Make O3 support variably lengthed instructions.
Ali Saidi [Mon, 15 Nov 2010 20:04:05 +0000 (14:04 -0600)]
O3: reset architetural state by calling clear()
Ali Saidi [Mon, 15 Nov 2010 20:04:05 +0000 (14:04 -0600)]
ARM: Add comment about the organization of the IT state register
Ali Saidi [Mon, 15 Nov 2010 20:04:05 +0000 (14:04 -0600)]
Regressions: Update regressions for SIMD opclass changes
Giacomo Gabrielli [Mon, 15 Nov 2010 20:04:04 +0000 (14:04 -0600)]
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
Ali Saidi [Mon, 15 Nov 2010 20:04:04 +0000 (14:04 -0600)]
ARM: Compile O3 CPU by default
Min Kyu Jeong [Mon, 15 Nov 2010 20:04:04 +0000 (14:04 -0600)]
O3: prevent a squash when completeAcc() modifies misc reg through TC.
This happens on ARM instructions when they update the IT state bits.
Code and associated comment was copied from execute() and initiateAcc() methods
Ali Saidi [Mon, 15 Nov 2010 20:04:04 +0000 (14:04 -0600)]
ARM: Return an FailUnimp instruction when an unimplemented CP15 register is accessed.
Just panicing in readMiscReg() doesn't work because a speculative access
in the o3 model can end the simulation.
Ali Saidi [Mon, 15 Nov 2010 20:04:04 +0000 (14:04 -0600)]
SCons: Cleanup SCons output during compile
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Update regressions for CLCD and KMI additions
William Wang [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Add a Keyboard Mouse Interface controller
William Wang [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Implement a CLCD Frame buffer
William Wang [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Add support for GDB on ARM
--HG--
rename : src/arch/alpha/remote_gdb.cc => src/arch/arm/remote_gdb.cc
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Make utility.hh meet style guidelines
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Add support for a dumb IDE controller
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Add support for switching CPUs
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Use the correct delete operator for RFE
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Fix SRS instruction to micro-code memory operation and register update.
Previously the SRS instruction attempted to writeback in initiateAcc() which
worked until a recent change, but was incorrect.
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
CPU: Fix bug when a split transaction is issued to a faster cache
In the case of a split transaction and a cache that is faster than a CPU we
could get two responses before next_tick expires. Add an event that is
scheduled in this case and return false rather than asserting.
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Do something predictable for an UNPREDICTABLE branch.
Gabe Black [Thu, 11 Nov 2010 19:58:09 +0000 (11:58 -0800)]
Params: Fix an off by one error and a misleading comment.
Gabe Black [Thu, 11 Nov 2010 19:41:13 +0000 (11:41 -0800)]
SimObject: Add a comment near clear_child that it's unlikely to be called.
Gabe Black [Thu, 11 Nov 2010 10:03:58 +0000 (02:03 -0800)]
SPARC: Clean up some historical style issues.
Ali Saidi [Wed, 10 Nov 2010 06:48:03 +0000 (00:48 -0600)]
Update EIO regressions for last set of patches