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Luke Kenneth Casson Leighton [Mon, 28 Mar 2022 12:57:02 +0000 (13:57 +0100)]
add cs_latch as a peer of bus_latch in case the address changes
add a "ck_active" signal in hyperram.py
Luke Kenneth Casson Leighton [Mon, 28 Mar 2022 11:36:06 +0000 (12:36 +0100)]
minor simplification of hyperram: using constants
in m.If(test) can be done as plain python "if(test)"
Luke Kenneth Casson Leighton [Mon, 28 Mar 2022 11:27:38 +0000 (12:27 +0100)]
extend cs in hyperram to multiple bits
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 15:56:26 +0000 (16:56 +0100)]
update code-comments
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 12:07:42 +0000 (13:07 +0100)]
add reset pad to hyperram, should be set externally
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 22:37:24 +0000 (22:37 +0000)]
hyperram CS inverted (corrected)
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 21:20:15 +0000 (21:20 +0000)]
sort out hyperram ports down to test class
Luke Kenneth Casson Leighton [Fri, 25 Mar 2022 17:37:03 +0000 (17:37 +0000)]
fix attributes, sort out address
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 12:34:57 +0000 (12:34 +0000)]
rename hyperram clk pads to "ck"
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 12:51:30 +0000 (12:51 +0000)]
cleanup
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 12:51:25 +0000 (12:51 +0000)]
add ports function to HyperRAMPHY
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 12:45:41 +0000 (12:45 +0000)]
rename TestHyperRAMPHY to just HyperRAMPHY
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 12:41:04 +0000 (12:41 +0000)]
move HyperRAMPads and Test PHY to hyperram.py module
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 09:16:24 +0000 (09:16 +0000)]
remove redundant implementation of migen "timeline"
(this is the 2nd copy seen in the wild, the other is in GRAM by Jean-Thomas)
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 09:15:32 +0000 (09:15 +0000)]
document useful "add_extension" for HyperRAM PMODs
Luke Kenneth Casson Leighton [Wed, 16 Mar 2022 20:20:50 +0000 (20:20 +0000)]
update HyperRAM module and add unit test
Luke Kenneth Casson Leighton [Tue, 15 Mar 2022 10:06:48 +0000 (10:06 +0000)]
add first version of hyperram.py
Jean-François Nguyen [Fri, 29 Oct 2021 21:31:18 +0000 (23:31 +0200)]
examples/minerva_soc: fix typo.
Jean-François Nguyen [Fri, 29 Oct 2021 18:36:52 +0000 (20:36 +0200)]
sim.blackboxes.serial: add missing Verilog blackbox.
Jean-François Nguyen [Fri, 29 Oct 2021 18:24:11 +0000 (20:24 +0200)]
cores.litedram: add device to generated YAML configuration.
Also, fix wrong build product path.
Jean-François Nguyen [Fri, 29 Oct 2021 18:22:26 +0000 (20:22 +0200)]
test: fix broken tests.
Jean-François Nguyen [Fri, 29 Oct 2021 18:21:24 +0000 (20:21 +0200)]
Add LiteEth support.
Jean-François Nguyen [Fri, 29 Oct 2021 17:31:23 +0000 (19:31 +0200)]
soc.cpu: generate BIOS configuration from SoC constants.
Also, merge examples/{sdram,sram}_soc as minerva_soc.
Jean-François Nguyen [Fri, 29 Oct 2021 16:55:33 +0000 (18:55 +0200)]
periph.serial: add PHY as parameter, in order to use a blackbox.
Jean-François Nguyen [Fri, 29 Oct 2021 16:42:02 +0000 (18:42 +0200)]
periph: conform with nmigen-soc breaking changes.
* use window names for CSR banks and bus interfaces.
* do not assign a memory map at window creation (doing so would freeze the
memory map)
* use ResourceInfo when dumping resources.
Jean-François Nguyen [Fri, 29 Oct 2021 16:27:16 +0000 (18:27 +0200)]
cores.litedram: remove name_force parameter from Core constructor.
It was previously moved to Core.build().
Jean-François Nguyen [Fri, 29 Oct 2021 16:25:35 +0000 (18:25 +0200)]
cores.litedram: add SDR DRAM type.
Jean-François Nguyen [Fri, 29 Oct 2021 16:21:52 +0000 (18:21 +0200)]
Add support for configuration constants.
Jean-François Nguyen [Fri, 29 Oct 2021 14:41:22 +0000 (16:41 +0200)]
cores.pll: add PLL generators for Lattice ECP5 and Xilinx 7 Series.
Jean-François Nguyen [Fri, 29 Oct 2021 12:10:08 +0000 (14:10 +0200)]
sim.blackboxes: add serial blackbox, with a serial_pty driver.
Jean-François Nguyen [Fri, 29 Oct 2021 12:08:53 +0000 (14:08 +0200)]
sim: add CXXRTL integration.
Jean-François Nguyen [Thu, 1 Jul 2021 13:49:17 +0000 (15:49 +0200)]
examples/sdram_soc: reduce L1 sizes to 1KB to meet timing.
Jean-François Nguyen [Thu, 1 Jul 2021 12:33:33 +0000 (14:33 +0200)]
software/bios: bump version.
Also, pin LiteX dependencies to the revision used by lambdasoc-bios.
Jean-François Nguyen [Wed, 30 Jun 2021 16:02:28 +0000 (18:02 +0200)]
setup.py,requirements.txt: add LiteX dependencies.
Jean-François Nguyen [Wed, 30 Jun 2021 15:41:47 +0000 (17:41 +0200)]
examples/sram_soc: fix platform paremeter help.
Jean-François Nguyen [Wed, 30 Jun 2021 15:40:57 +0000 (17:40 +0200)]
examples/{sram,sdram}_soc: add --build-dir parameter.
Jean-François Nguyen [Wed, 30 Jun 2021 15:36:34 +0000 (17:36 +0200)]
examples/sdram_soc: add --platform parameter.
Jean-François Nguyen [Tue, 29 Jun 2021 16:39:59 +0000 (18:39 +0200)]
cores.litedram: move memory map population to _populate_ctrl_map().
Jean-François Nguyen [Tue, 29 Jun 2021 16:37:35 +0000 (18:37 +0200)]
cores.litedram: move name conflict detection to the builder.
Jean-François Nguyen [Mon, 28 Jun 2021 18:27:45 +0000 (20:27 +0200)]
Add SDRAMPeripheral and SDRAMSoC example.
Jean-François Nguyen [Mon, 28 Jun 2021 17:56:47 +0000 (19:56 +0200)]
soc.base: add support for adding user-provided template parameters.
Jean-François Nguyen [Mon, 28 Jun 2021 17:49:27 +0000 (19:49 +0200)]
soc.base: add socproperty(weak=True) for optional properties.
Jean-François Nguyen [Mon, 28 Jun 2021 15:45:48 +0000 (17:45 +0200)]
cores: add LiteDRAM core.
Jean-François Nguyen [Mon, 28 Jun 2021 14:27:39 +0000 (16:27 +0200)]
tools.flterm: warn and continue after failed TIOCMBIC ioctl.
Jean-François Nguyen [Mon, 28 Jun 2021 14:19:13 +0000 (16:19 +0200)]
periph.serial: update default rx_depth value to 256.
This is allows the RX FIFO to buffer a complete SFL frame, to avoid a
race condition during a serialboot at a high baudrate.
Jean-François Nguyen [Mon, 28 Jun 2021 14:18:10 +0000 (16:18 +0200)]
periph.serial: use buffered FIFOs to help BRAM inference.
Jean-François Nguyen [Mon, 28 Jun 2021 14:16:15 +0000 (16:16 +0200)]
test.test_periph_serial: fix loopback test.
Jean-François Nguyen [Mon, 28 Jun 2021 13:47:15 +0000 (15:47 +0200)]
test: _wishbone.py → utils/wishbone.py
Jean-François Nguyen [Mon, 28 Jun 2021 13:42:45 +0000 (15:42 +0200)]
test: move to sim = Simulator(dut) instead of context manager.
Jean-François Nguyen [Tue, 8 Jun 2021 12:53:50 +0000 (14:53 +0200)]
setup.py: update dependencies.
Also, add nmigen to requirements.txt.
Jean-François Nguyen [Tue, 8 Jun 2021 12:49:21 +0000 (14:49 +0200)]
software/bios: bump version.
Jean-François Nguyen [Tue, 1 Jun 2021 19:07:53 +0000 (21:07 +0200)]
setup.py: do not install package as a zip file.
Jean-François Nguyen [Tue, 1 Jun 2021 19:07:29 +0000 (21:07 +0200)]
MANIFEST.in: fix compiler-rt path.
Jean-François Nguyen [Tue, 18 May 2021 17:16:27 +0000 (19:16 +0200)]
periph.base: use bridge granularity as CSR bus data width.
Jean-François Nguyen [Tue, 18 May 2021 17:11:39 +0000 (19:11 +0200)]
periph.event: clear pending bits of level-triggered events.
Jean-François Nguyen [Mon, 31 May 2021 17:29:15 +0000 (19:29 +0200)]
software/bios: bump version.
Fixes #9
Jean-François Nguyen [Tue, 16 Jun 2020 11:41:44 +0000 (13:41 +0200)]
Merge pull request #4 from jeanthom/fix-base-soc
Fix ConfigBuilder instantiation in SoC base class
Jean-François Nguyen [Tue, 16 Jun 2020 11:38:25 +0000 (13:38 +0200)]
Merge pull request #3 from jeanthom/master
Throw exception if two CSR in the same bank have the same name
Jean THOMAS [Mon, 15 Jun 2020 09:13:09 +0000 (11:13 +0200)]
Fix ConfigBuilder instantiation in SoC base class
Jean THOMAS [Mon, 8 Jun 2020 11:23:48 +0000 (13:23 +0200)]
Throw exception if two CSR have the same name
Jean-François Nguyen [Fri, 24 Apr 2020 10:27:04 +0000 (12:27 +0200)]
Use HTTPS for lambdasoc-bios submodule URL.
Fixes #1.
Jean-François Nguyen [Thu, 9 Apr 2020 16:38:23 +0000 (18:38 +0200)]
soc.cpu: log build output to stderr
Jean-François Nguyen [Mon, 30 Mar 2020 15:18:30 +0000 (17:18 +0200)]
README: fix install instructions
Jean-François Nguyen [Mon, 30 Mar 2020 15:12:20 +0000 (17:12 +0200)]
Move non-PyPI dependencies to requirements.txt
Jean-François Nguyen [Mon, 30 Mar 2020 15:04:09 +0000 (17:04 +0200)]
MANIFEST: fix non-directory includes
Jean-François Nguyen [Mon, 30 Mar 2020 13:38:03 +0000 (15:38 +0200)]
Add software/bios to MANIFEST.in
Jean-François Nguyen [Mon, 30 Mar 2020 12:41:05 +0000 (14:41 +0200)]
Add README and LICENSE
Jean-François Nguyen [Mon, 30 Mar 2020 11:59:25 +0000 (13:59 +0200)]
tools: add flterm
Jean-François Nguyen [Thu, 26 Mar 2020 12:40:29 +0000 (13:40 +0100)]
examples: add sram_soc example
Jean-François Nguyen [Thu, 26 Mar 2020 11:27:02 +0000 (12:27 +0100)]
soc.cpu: add CPUSoC and BIOSBuilder
Jean-François Nguyen [Thu, 26 Mar 2020 11:15:24 +0000 (12:15 +0100)]
soc.base: add SoC and ConfigBuilder
Jean-François Nguyen [Thu, 26 Mar 2020 09:00:07 +0000 (10:00 +0100)]
cpu: add MinervaCPU
Jean-François Nguyen [Wed, 25 Mar 2020 18:00:38 +0000 (19:00 +0100)]
Add .gitignore
Jean-François Nguyen [Wed, 25 Mar 2020 16:41:41 +0000 (17:41 +0100)]
periph.intc: add GenericInterruptController
Jean-François Nguyen [Wed, 25 Mar 2020 14:51:57 +0000 (15:51 +0100)]
periph.serial: add AsyncSerialPeripheral
Jean-François Nguyen [Wed, 25 Mar 2020 13:24:04 +0000 (14:24 +0100)]
periph._event → periph.event
Jean-François Nguyen [Wed, 25 Mar 2020 12:28:16 +0000 (13:28 +0100)]
periph.sram: add SRAMPeripheral
Jean-François Nguyen [Wed, 25 Mar 2020 12:22:08 +0000 (13:22 +0100)]
periph.timer: add TimerPeripheral
Jean-François Nguyen [Wed, 25 Mar 2020 11:54:45 +0000 (12:54 +0100)]
periph: add Peripheral base class
Jean-François Nguyen [Wed, 25 Mar 2020 11:50:08 +0000 (12:50 +0100)]
Add setup.py
Jean-François Nguyen [Fri, 13 Mar 2020 19:28:48 +0000 (20:28 +0100)]
Initial commit