openpower-isa.git
3 years agoidentify SVP64 LD bit-reverse pattern as pseudo-assembler
Luke Kenneth Casson Leighton [Fri, 25 Jun 2021 18:18:35 +0000 (19:18 +0100)]
identify SVP64 LD bit-reverse pattern as pseudo-assembler
rewrite it before it gets too far into SVP64Asm
morph any "sv.ldxxxxbr" into "sv.ld/br" and rewrite the fields

3 years agoonly set conditions in PowerDecoder2 for svp64 mode
Luke Kenneth Casson Leighton [Fri, 25 Jun 2021 18:12:13 +0000 (19:12 +0100)]
only set conditions in PowerDecoder2 for svp64 mode

3 years agoupdate sv_analysis.py to match new CONDITIONs field in CSV files
Luke Kenneth Casson Leighton [Fri, 25 Jun 2021 13:42:55 +0000 (14:42 +0100)]
update sv_analysis.py to match new CONDITIONs field in CSV files

3 years agorename svp64 bit-reversed LD instructions to not conflict with v3.0B
Luke Kenneth Casson Leighton [Fri, 25 Jun 2021 13:42:23 +0000 (14:42 +0100)]
rename svp64 bit-reversed LD instructions to not conflict with v3.0B

3 years agowhoops SVP64 bit-rev LDs need to use SVD and SVDS immediate not D and DS
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 21:17:02 +0000 (22:17 +0100)]
whoops SVP64 bit-rev LDs need to use SVD and SVDS immediate not D and DS

3 years agoallow default decoder to be created with no col/row subset
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 21:11:26 +0000 (22:11 +0100)]
allow default decoder to be created with no col/row subset

3 years agoadd in Power Decoder conditions to select SVP64 bit-rev decoding
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 21:07:53 +0000 (22:07 +0100)]
add in Power Decoder conditions to select SVP64 bit-rev decoding

3 years agoadd "conditions" for PowerDecoder, basic test
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 21:02:07 +0000 (22:02 +0100)]
add "conditions" for PowerDecoder, basic test

3 years agoremove svp64 ld/st decoder tree
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 21:00:58 +0000 (22:00 +0100)]
remove svp64 ld/st decoder tree

3 years agomust pass in conditions into Sub-decoders
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 19:10:52 +0000 (20:10 +0100)]
must pass in conditions into Sub-decoders

3 years agosearch for CSV "Conditions", set to static (disabled) for now
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 19:09:06 +0000 (20:09 +0100)]
search for CSV "Conditions", set to static (disabled) for now
conditions in CSV files activate an additional case statement

3 years agoadd major.csv LD operations with SVP64BREV condition
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 18:23:54 +0000 (19:23 +0100)]
add major.csv LD operations with SVP64BREV condition

3 years agoadd PowerDecoder condition switches (untested, doesnt break anything)
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 18:19:26 +0000 (19:19 +0100)]
add PowerDecoder condition switches (untested, doesnt break anything)

3 years agowas going to set 2nd decoder up through MUX but now too complicated
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 18:01:27 +0000 (19:01 +0100)]
was going to set 2nd decoder up through MUX but now too complicated
going to do "decoder conditions" instead

3 years agoadd extra CONDITION column to CSVs
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 17:59:47 +0000 (18:59 +0100)]
add extra CONDITION column to CSVs

3 years agowhoops fix rounding error in mapreduce unit test
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 15:09:25 +0000 (16:09 +0100)]
whoops fix rounding error in mapreduce unit test

3 years agoonly add svdecldst in PowerDecoder2 or LDST PowerDecodeSubset
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 15:07:23 +0000 (16:07 +0100)]
only add svdecldst in PowerDecoder2 or LDST PowerDecodeSubset

3 years agouse PowerOp copy of PowerDecodeSubset in get_op
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 15:04:09 +0000 (16:04 +0100)]
use PowerOp copy of PowerDecodeSubset in get_op
not the one in the "main" decoder.
in preparation for MUXing onto self.op

3 years agoadd "user_svp64_ldst_dec" flag to PowerDecodeSubset
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 14:50:32 +0000 (15:50 +0100)]
add "user_svp64_ldst_dec" flag to PowerDecodeSubset

3 years agouse new PowerOp.like function in PowerDecoder, fix missing fields
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 14:34:43 +0000 (15:34 +0100)]
use new PowerOp.like function in PowerDecoder, fix missing fields

3 years agouse get_op on "internal_op" instead of self.dec.op in PowerDecoder2
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 14:24:11 +0000 (15:24 +0100)]
use get_op on "internal_op" instead of self.dec.op in PowerDecoder2

3 years agodo shorter-path detection of SVP64 LD/ST bitreverse mode
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 12:25:45 +0000 (13:25 +0100)]
do shorter-path detection of SVP64 LD/ST bitreverse mode
needs to be very quick, because the entire decode path is to be MUXED

3 years agotidy up PowerOp and rename svp64 ldst decoder creater
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 12:24:22 +0000 (13:24 +0100)]
tidy up PowerOp and rename svp64 ldst decoder creater

3 years agoadd comment about perfcounters
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 11:47:45 +0000 (12:47 +0100)]
add comment about perfcounters

3 years agoget op always using function PowerDecoder.op_get
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 22:32:07 +0000 (23:32 +0100)]
get op always using function PowerDecoder.op_get
need to mux this when doing SVP64 bitrev LD/ST detection

3 years agoadd PowerOp.like function to be able to duplicate a PowerOp
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 22:15:04 +0000 (23:15 +0100)]
add PowerOp.like function to be able to duplicate a PowerOp

3 years agoadd SVP64 alternative LDST decoder (unused so far)
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 21:57:30 +0000 (22:57 +0100)]
add SVP64 alternative LDST decoder (unused so far)

3 years agoonly add SVP64 bitreverse mode for LDs at the moment. ST would need 4 operands
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 21:42:37 +0000 (22:42 +0100)]
only add SVP64 bitreverse mode for LDs at the moment. ST would need 4 operands
add RC to PowerDecoder
add create_decode_svp64
sort out Forms and Const names in enums

3 years agoadd SVP64 LD/ST "bitrev" alternative CSV
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 20:17:47 +0000 (21:17 +0100)]
add SVP64 LD/ST "bitrev" alternative CSV

3 years agoadd sv bitrev "major" CSV table
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 20:12:48 +0000 (21:12 +0100)]
add sv bitrev "major" CSV table

3 years agoadd start of bit-reverse mode for LD/ST to SVP64 encode/decode
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 17:57:22 +0000 (18:57 +0100)]
add start of bit-reverse mode for LD/ST to SVP64 encode/decode

3 years agolooks like spec error on maddhd etc. should be a comma rather than fullstop
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 16:31:55 +0000 (17:31 +0100)]
looks like spec error on maddhd etc. should be a comma rather than fullstop

3 years agoadd mul-add to list of instructions
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 16:28:34 +0000 (17:28 +0100)]
add mul-add to list of instructions

3 years agoadd ASCII art example to int predicated SVP64
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 16:21:05 +0000 (17:21 +0100)]
add ASCII art example to int predicated SVP64

3 years agoadd VL and srcstep to ISACaller namespace
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 15:33:32 +0000 (16:33 +0100)]
add VL and srcstep to ISACaller namespace

3 years agoadd SHL64 helper function
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 15:29:54 +0000 (16:29 +0100)]
add SHL64 helper function

3 years agoadd bitrev to pywriter autogenerator
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 15:26:02 +0000 (16:26 +0100)]
add bitrev to pywriter autogenerator

3 years agoadd bitrev function to be used in LD-ST-bitrev FFT/DCT
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 15:23:56 +0000 (16:23 +0100)]
add bitrev function to be used in LD-ST-bitrev FFT/DCT

3 years agobetter ways to do sign-inversion (without multiply which rounds)
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 15:07:12 +0000 (16:07 +0100)]
better ways to do sign-inversion (without multiply which rounds)
also fix FP unit tests

3 years agoadd sign-inversion argument to FPMUL/DIV helpers
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 14:46:02 +0000 (15:46 +0100)]
add sign-inversion argument to FPMUL/DIV helpers

3 years agoadd comments for SVP64 FP FFT/DCT
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 13:48:31 +0000 (14:48 +0100)]
add comments for SVP64 FP FFT/DCT

3 years agoadd FFT/DCT to titles
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 13:44:24 +0000 (14:44 +0100)]
add FFT/DCT to titles

3 years agoadd SV FP arithmetic in "Overflow" mode for FFT/DCT +/-
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 13:42:40 +0000 (14:42 +0100)]
add SV FP arithmetic in "Overflow" mode for FFT/DCT +/-

3 years agouse SHL64 function for shift because "<<" operator doesnt exist in
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 11:26:37 +0000 (12:26 +0100)]
use SHL64 function for shift because "<<" operator doesnt exist in
v3.0B pseudocode syntax

3 years agoadd in bitreverse function call into svfixedload
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 11:19:04 +0000 (12:19 +0100)]
add in bitreverse function call into svfixedload

3 years agoadd RC and SVD/SVDS-Form to svfixedload
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 11:06:33 +0000 (12:06 +0100)]
add RC and SVD/SVDS-Form to svfixedload

3 years agoadd svfixedload.mdwn at correct place
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 11:04:53 +0000 (12:04 +0100)]
add svfixedload.mdwn at correct place

3 years agoadd SVD-Form and SVDS-Form, variants of fixedload for SVP64
Luke Kenneth Casson Leighton [Wed, 23 Jun 2021 11:04:06 +0000 (12:04 +0100)]
add SVD-Form and SVDS-Form, variants of fixedload for SVP64

3 years ago128 regs added to simulator - works
Luke Kenneth Casson Leighton [Sat, 19 Jun 2021 19:41:14 +0000 (20:41 +0100)]
128 regs added to simulator - works

3 years agosigh cannot add comments at end of SV lines in SVP64 asm yet
Luke Kenneth Casson Leighton [Sat, 19 Jun 2021 19:40:13 +0000 (20:40 +0100)]
sigh cannot add comments at end of SV lines in SVP64 asm yet

3 years agoincrease number of registers to 128 in pypowersim
Luke Kenneth Casson Leighton [Sat, 19 Jun 2021 18:57:36 +0000 (19:57 +0100)]
increase number of registers to 128 in pypowersim

3 years agoset regfile in ISACaller equal to length of initial variables
Luke Kenneth Casson Leighton [Sat, 19 Jun 2021 18:53:50 +0000 (19:53 +0100)]
set regfile in ISACaller equal to length of initial variables

3 years agoadd mapreduce "reverse gear" unit tests
Luke Kenneth Casson Leighton [Sat, 19 Jun 2021 12:52:42 +0000 (13:52 +0100)]
add mapreduce "reverse gear" unit tests
add svp64 assembly mode "/mrr" - mapreduce reverse
add non-reverse mapreduce unit test as well (pascal triangle)

3 years agoadd mapreduce "reverse gear" to PowerDecoder2. gets the reg num to
Luke Kenneth Casson Leighton [Sat, 19 Jun 2021 12:13:33 +0000 (13:13 +0100)]
add mapreduce "reverse gear" to PowerDecoder2. gets the reg num to
swap direction instead of 0..VL-1 it is VL-1..0

3 years agoadd decode of "reverse gear" in SVP64 reduce mode
Luke Kenneth Casson Leighton [Sat, 19 Jun 2021 12:02:03 +0000 (13:02 +0100)]
add decode of "reverse gear" in SVP64 reduce mode

3 years agoadd "reverse-gear" mode to mapreduce in SVP64
Luke Kenneth Casson Leighton [Sat, 19 Jun 2021 11:47:56 +0000 (12:47 +0100)]
add "reverse-gear" mode to mapreduce in SVP64

3 years agoadd SV Context SPRs (SVCTX0-7)
Luke Kenneth Casson Leighton [Fri, 18 Jun 2021 12:16:13 +0000 (13:16 +0100)]
add SV Context SPRs (SVCTX0-7)

3 years agoadd SVR-Form and associated fields
Luke Kenneth Casson Leighton [Fri, 18 Jun 2021 11:57:59 +0000 (12:57 +0100)]
add SVR-Form and associated fields

3 years agoadd four SVSHAPE SPRs for REMAP
Luke Kenneth Casson Leighton [Fri, 18 Jun 2021 11:27:02 +0000 (12:27 +0100)]
add four SVSHAPE SPRs for REMAP
https://libre-soc.org/openpower/sv/remap/

3 years agoadd SV "Context Propagation" Form
Luke Kenneth Casson Leighton [Thu, 17 Jun 2021 18:57:57 +0000 (19:57 +0100)]
add SV "Context Propagation" Form

3 years agoadd SVP64REMAP Record
Luke Kenneth Casson Leighton [Thu, 17 Jun 2021 18:43:00 +0000 (19:43 +0100)]
add SVP64REMAP Record
https://libre-soc.org/openpower/sv/remap/

3 years agoshuffle comments
Luke Kenneth Casson Leighton [Thu, 17 Jun 2021 14:47:19 +0000 (15:47 +0100)]
shuffle comments

3 years agofix MP3 CODEC basic demo by using fmuls and fadds/fsubs not fmadds
Luke Kenneth Casson Leighton [Thu, 17 Jun 2021 10:30:44 +0000 (11:30 +0100)]
fix MP3 CODEC basic demo by using fmuls and fadds/fsubs not fmadds
now accurate to scalar version

3 years agosorted out order of FPMULADD32 helper, only have rounding errors now
Luke Kenneth Casson Leighton [Wed, 16 Jun 2021 19:29:54 +0000 (20:29 +0100)]
sorted out order of FPMULADD32 helper, only have rounding errors now

3 years agoadd extra comments to mp3 svp64 codec assembler
Luke Kenneth Casson Leighton [Wed, 16 Jun 2021 19:27:40 +0000 (20:27 +0100)]
add extra comments to mp3 svp64 codec assembler

3 years agofix fmadds/fmsubs FPMULADD32 helper
Luke Kenneth Casson Leighton [Wed, 16 Jun 2021 18:58:37 +0000 (19:58 +0100)]
fix fmadds/fmsubs FPMULADD32 helper

3 years agomore code-comments in mp3 codec svp64 example
Luke Kenneth Casson Leighton [Wed, 16 Jun 2021 18:41:59 +0000 (19:41 +0100)]
more code-comments in mp3 codec svp64 example

3 years agoalthough unused read first sum from *dither_state
Luke Kenneth Casson Leighton [Wed, 16 Jun 2021 16:59:11 +0000 (17:59 +0100)]
although unused read first sum from *dither_state

3 years agouse addi where sv.addi is inappropriate (scalar values)
Luke Kenneth Casson Leighton [Wed, 16 Jun 2021 16:47:49 +0000 (17:47 +0100)]
use addi where sv.addi is inappropriate (scalar values)
although later win and win2 will move to above 32.
looking for possible discrepancies in assembler code

3 years agoreorder arguments to FPMULADD32 to match pseudocode
Luke Kenneth Casson Leighton [Wed, 16 Jun 2021 16:20:51 +0000 (17:20 +0100)]
reorder arguments to FPMULADD32 to match pseudocode

3 years agouse fnmsubs instead of fmadds followed by fsubs
Luke Kenneth Casson Leighton [Wed, 16 Jun 2021 12:14:48 +0000 (13:14 +0100)]
use fnmsubs instead of fmadds followed by fsubs

3 years agofnmadds and fnmsubs were inverted
Luke Kenneth Casson Leighton [Wed, 16 Jun 2021 12:14:07 +0000 (13:14 +0100)]
fnmadds and fnmsubs were inverted

3 years agoad fnmadd and fnmsubs to ISA pseudocode
Luke Kenneth Casson Leighton [Wed, 16 Jun 2021 12:07:34 +0000 (13:07 +0100)]
ad fnmadd and fnmsubs to ISA pseudocode

3 years agoreverting removal of tmpsum and tmpsum2, not using fmsubs
Luke Kenneth Casson Leighton [Wed, 16 Jun 2021 10:24:48 +0000 (11:24 +0100)]
reverting removal of tmpsum and tmpsum2, not using fmsubs
see http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-June/003145.html

3 years agowhoops forgot import
Luke Kenneth Casson Leighton [Tue, 15 Jun 2021 19:22:50 +0000 (20:22 +0100)]
whoops forgot import

3 years agowhoops still using DOUBLE(SINGLE(x)) rather than DOUBLE2SINGLE
Luke Kenneth Casson Leighton [Tue, 15 Jun 2021 19:21:58 +0000 (20:21 +0100)]
whoops still using DOUBLE(SINGLE(x)) rather than DOUBLE2SINGLE

3 years agoremove predicate mask r30, no longer needed
Luke Kenneth Casson Leighton [Tue, 15 Jun 2021 18:14:03 +0000 (19:14 +0100)]
remove predicate mask r30, no longer needed

3 years agono need for tmpsu or tmpsum2, fmadds if replaced with fmsubs does the job
Luke Kenneth Casson Leighton [Tue, 15 Jun 2021 17:58:50 +0000 (18:58 +0100)]
no need for tmpsu or tmpsum2, fmadds if replaced with fmsubs does the job

3 years agouse new sv.fmadds SVP64 instruction in MP3 CODEC assembler
Luke Kenneth Casson Leighton [Tue, 15 Jun 2021 17:43:50 +0000 (18:43 +0100)]
use new sv.fmadds SVP64 instruction in MP3 CODEC assembler

3 years agofix sv_analysis.py for 3R-1W-CRo case, add fmadds/fmsubs and SVP64 tests
Luke Kenneth Casson Leighton [Tue, 15 Jun 2021 17:43:18 +0000 (18:43 +0100)]
fix sv_analysis.py for 3R-1W-CRo case, add fmadds/fmsubs and SVP64 tests

3 years agomark as possible bug, the fneg sum,sum
Luke Kenneth Casson Leighton [Tue, 15 Jun 2021 15:47:45 +0000 (16:47 +0100)]
mark as possible bug, the fneg sum,sum

3 years agoadd fmadds and fmsubs to Power ISA pseudo-code, add unit test (scalar)
Luke Kenneth Casson Leighton [Tue, 15 Jun 2021 15:36:59 +0000 (16:36 +0100)]
add fmadds and fmsubs to Power ISA pseudo-code, add unit test (scalar)

3 years agoremove negate of sum for last value in SVP64 MP3 CODEC assembler
Luke Kenneth Casson Leighton [Tue, 15 Jun 2021 15:01:29 +0000 (16:01 +0100)]
remove negate of sum for last value in SVP64 MP3 CODEC assembler

3 years agoSVP64 mp3 assembler almost correct
Luke Kenneth Casson Leighton [Tue, 15 Jun 2021 14:53:41 +0000 (15:53 +0100)]
SVP64 mp3 assembler almost correct
lkcl@fizzy:~/src/libresoc/openpower-isa/media$ diff -u /tmp/x1 /tmp/x2
--- /tmp/x1     2021-06-15 15:51:06.016530558 +0100
+++ /tmp/x2     2021-06-15 15:51:16.816549772 +0100
@@ -2,7 +2,7 @@
 00000010  91 38 c2 aa b0 65 00 2a  ec 4d ea 2a c6 99 f3 ab  |.8...e.*.M.*....|
 00000020  5e 86 5c 2b c7 79 ce aa  05 b1 30 ab c2 b7 35 2c  |^.\+.y....0...5,|
 00000030  b2 48 35 ab 00 d8 91 2b  26 7e 6c 2b 52 c9 ac ac  |.H5....+&~l+R...|
-00000040  00 00 00 00 fc 57 cf 2c  61 ee ce ab 00 3a ff ab  |.....W.,a....:..|
+00000040  00 00 00 80 fc 57 cf 2c  61 ee ce ab 00 3a ff ab  |.....W.,a....:..|
 00000050  42 b6 f1 2b d2 49 08 ad  46 dd 5c 2c b9 f3 0d 2c  |B..+.I..F.\,...,|
 00000060  2c 2d b3 ac 8d 26 55 2d  ec 4d ea ac 0b 6c 08 ac  |,-...&U-.M...l..|
 00000070  2c a3 e6 2c 52 97 db ac  a8 7c 03 2d 1d b3 58 ac  |,..,R....|.-..X.|

3 years agoadd comments into mapreduce example
Luke Kenneth Casson Leighton [Tue, 15 Jun 2021 14:32:15 +0000 (15:32 +0100)]
add comments into mapreduce example

3 years agowhoops overlap of fv0-2 with sum/2/tmp, move further up
Luke Kenneth Casson Leighton [Tue, 15 Jun 2021 10:09:03 +0000 (11:09 +0100)]
whoops overlap of fv0-2 with sum/2/tmp, move further up

3 years agosigh bug in setvl, temporarily setting to 7 not 8
Luke Kenneth Casson Leighton [Mon, 14 Jun 2021 23:53:54 +0000 (00:53 +0100)]
sigh bug in setvl, temporarily setting to 7 not 8

3 years agonope, win = win2 + 31
Luke Kenneth Casson Leighton [Mon, 14 Jun 2021 23:40:21 +0000 (00:40 +0100)]
nope, win = win2 + 31

3 years agoguessing probably supposed to be 128 not 124
Luke Kenneth Casson Leighton [Mon, 14 Jun 2021 23:39:31 +0000 (00:39 +0100)]
guessing probably supposed to be 128 not 124

3 years agotmpsum2 probably needed to be fp3
Luke Kenneth Casson Leighton [Mon, 14 Jun 2021 23:37:09 +0000 (00:37 +0100)]
tmpsum2 probably needed to be fp3

3 years agotemporary move regs into range 0-31
Luke Kenneth Casson Leighton [Mon, 14 Jun 2021 22:00:24 +0000 (23:00 +0100)]
temporary move regs into range 0-31

3 years agorecognise setvl instruction during SVP64 translation
Luke Kenneth Casson Leighton [Mon, 14 Jun 2021 22:00:06 +0000 (23:00 +0100)]
recognise setvl instruction during SVP64 translation

3 years agowhoops forgot format-to-format conversion
Luke Kenneth Casson Leighton [Mon, 14 Jun 2021 21:49:59 +0000 (22:49 +0100)]
whoops forgot format-to-format conversion

3 years agoseries of text macro formats to look for: x.v, x.s (x)
Luke Kenneth Casson Leighton [Mon, 14 Jun 2021 21:46:57 +0000 (22:46 +0100)]
series of text macro formats to look for: x.v, x.s (x)

3 years agoadd basic "macro" (.set) support to SVP64Asm
Luke Kenneth Casson Leighton [Mon, 14 Jun 2021 21:36:16 +0000 (22:36 +0100)]
add basic "macro" (.set) support to SVP64Asm
also fix bug where immediate fields were not being translated

3 years agomp3_0 initial sv
Lauri Kasanen [Mon, 14 Jun 2021 12:25:12 +0000 (15:25 +0300)]
mp3_0 initial sv

3 years agoReorder mp3_0_basicsv back to the C loop style
Lauri Kasanen [Mon, 14 Jun 2021 11:53:40 +0000 (14:53 +0300)]
Reorder mp3_0_basicsv back to the C loop style

3 years agoUpdate mp3_1.gpr missed in b04990f79c
Lauri Kasanen [Mon, 14 Jun 2021 11:20:56 +0000 (14:20 +0300)]
Update mp3_1.gpr missed in b04990f79c

3 years agoadd some more comments in the mapreduce svp64 examples/unit tests
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 20:33:16 +0000 (21:33 +0100)]
add some more comments in the mapreduce svp64 examples/unit tests

3 years agoadd sv.fmuls/mr - mapreduce - FP multiply-single test
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 17:31:25 +0000 (18:31 +0100)]
add sv.fmuls/mr - mapreduce - FP multiply-single test