Andreas Hansson [Fri, 1 Nov 2013 15:56:13 +0000 (11:56 -0400)]
sim: Clarify the difference between tracing and debugging
This patch changes the name the command-line options related to debug
output to all start with "debug" rather than being a mix of that and
"trace". It also makes it clear that the breakpoint time is specified
in ticks and not in cycles.
Chander Sudanthi [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
ARM: add support for TEEHBR access
Thumb2 ARM kernels may access the TEEHBR via thumbee_notifier
in arch/arm/kernel/thumbee.c. The Linux kernel code just seems
to be saving and restoring the register. This patch adds support
for the TEEHBR cp14 register. Note, this may be a special case
when restoring from an image that was run on a system that
supports ThumbEE.
Matt Evans [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
dev: Add 'OSC' oscillator sys control reg support to VersatileExpress
The VE motherboard provides a set of system control registers through which
various motherboard and coretile registers are accessed. Voltage regulators and
oscillator (DLL/PLL) config are examples. These registers must be impleted to
boot Linux 3.9+ kernels.
Geoffrey Blake [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
dev: Add support for MSI-X and Capability Lists for ARM and PCI devices
This patch adds the registers and fields to the PCI device to support
Capability lists and to support MSI-X in the GIC.
Geoffrey Blake [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
dev: Fix race conditions in IDE device on newer kernels
Newer linux kernels and distros exercise more functionality in the IDE device
than previously, exposing 2 races. The first race is the handling of aborted
DMA commands would immediately report the device is ready back to the kernel
and cause already in flight commands to assert the simulator when they returned
and discovered an inconsitent device state. The second race was due to the
Status register not being handled correctly, the interrupt status bit would get
stuck at 1 and the driver eventually views this as a bad state and logs the
condition to the terminal. This patch fixes these two conditions by making the
device handle aborted commands gracefully and properly handles clearing the
interrupt status bit in the Status register.
Geoffrey Blake [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
base: Add support for ipv6 into inet.hh/inet.cc
Faissal Sleiman [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
cpu: Construct ROB with cpu params struct instead of each variable
Most other structures/stages get passed the cpu params struct.
Geoffrey Blake [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
config: Fix handling of parents for simobject vectors
SimObjectVector objects did not provide the same interface to
the _parent attribute through get_parent() like a normal
SimObject. It also handled assigning a _parent incorrectly
if objects in a SimObjectVector were changed post-creation,
leading to errors later when the simulator tried to execute.
This patch fixes these two omissions.
Dam Sunwoo [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
sim: added option to serialize SimLoopExitEvent
SimLoopExitEvents weren't serialized by default. Some benchmarks
utilize a delayed m5 exit pseudo op call to terminate the simulation
and this event was lost when resuming from a checkpoint generated
after the pseudo op call. This patch adds the capability to serialize
the SimLoopExitEvents and enable serialization for m5_exit and m5_fail
pseudo ops by default. Does not affect other generic
SimLoopExitEvents.
Stephan Diestelhorst [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
mem: Add "const" attribute to Packet getters
Add a "const" keywords to the getters in the Packet class so these can be
invoked on const Packet objects.
Prakash Ramrakhyani [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
mem: Add privilege info to request class
This patch adds a flag in the request class that indicates if the request
was made in privileged mode.
Ali Saidi [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
arm: fix m5ops binary for ARM and add m5fail.
Changes to make m5ops work under virtualization seemed to break them working
with non-virtualized systems and the recently added m5 fail command makes
the m5op binary not compile. For now remove the code for virtualization.
Ali Saidi [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
cpu: Fix O3 issuse with load+barrier instructions.
Fix a problem in the O3 CPU for instructions that are both
memory loads and memory barriers (e.g. load acquire) and
to uncacheable memory. This combination can confuse the
commit stage into commitng an instruction that hasn't
executed and got it's value yet. At the same time refactor
the code slightly to remove duplication between two of
the cases.
Lluc Alvarez [Wed, 30 Oct 2013 15:35:06 +0000 (10:35 -0500)]
ruby: set SenderMachine in messages of MOESI_CMP_directory
This patch adds missing initializations of the SenderMachine field of
out_msg's when thery are created in the L2 cache controller of the
MOESI_CMP_directory coherence protocol. When an out_msg is created and this
field is left uninitialized, it is set to the default value MachineType_NUM.
This causes a panic in the MachineType_to_string function when gem5 is
executed with the Ruby debug flag on and it tries to print the message.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Emilio Castillo [Wed, 30 Oct 2013 15:35:05 +0000 (10:35 -0500)]
ruby: Fixed a deadlock when restoring a checkpoint with garnet
This patch fixes a problem where in Garnet, the enqueue time in the
VCallocator and the SWallocator which is of type Cycles was being stored
inside a variable with int type.
This lead to a known problem restoring checkpoints with garnet & the fixed
pipeline enabled. That value was really big and didn't fit in the variable
overflowing it, therefore some conditions on the VC allocation stage & the
SW allocation stage were not met and the packets didn't advance through the
network, leading to a deadlock panic right after the checkpoint was restored.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Stephan Diestelhorst [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
mem: De-virtualise interfaces in the CoherentBus
The CoherentBus eventually got virtual methods for its interface. The
"virtuality" of the CoherentBus, however, comes already from the virtual
interface of the bus' ports. There is no need to add another layer of virtual
functions, here.
Matt Horsnell [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
cpu: add consistent guarding to *_impl.hh files.
Sascha Bischoff [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
mem: Add PortID to QueuedMasterPort constructor
This patch adds the PortID to the QueuedMasterPort. This allows a PortID to be
specified as it previously was set to the detault value of -1.
Matt Evans [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
arm: Add a 'clear PPI' method to gic_pl390
The underlying assumption that all PPIs must be edge-triggered is
strained when the architected timers and VGIC interfaces make
level-behaviour observable. For example, a virtual timer interrupt
'goes away' when the hypervisor is entered and the vtimer is disabled;
this requires a PPI to be de-activated.
The new method simply clears the interrupt pending state.
Geoffrey Blake [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
config: Fix ommission of number base in ethernet address param
The ethernet address param tries to convert a hexadecimal
string using int() in python, which defaults to base 10,
need to specify base 16 in this case.
Geoffrey Blake [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
config: Fix for port references generated multiple times
SimObjects are expected to only generate one port reference per
port belonging to them. There is a subtle bug with using "not"
here as a VectorPort is seen as not having a reference if it is
either None or empty as per Python docs sec 9.9 for Standard operators.
Intended behavior is to only check if we have not created the reference.
Dam Sunwoo [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
dev: Add option to disable framebuffer .bmp dump in run folder
There is an option to enable/disable all framebuffer dumps, but the
last frame always gets dumped in the run folder with no other way to
disable it. These files can add up very quickly running many experiments.
This patch adds an option to disable them. The default behavior
remains unchanged.
Faissal Sleiman [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
cpu: Removing an unused variable in rename
Faissal Sleiman [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
cpu: Change IEW DPRINTF to use IEW debug flag
IEW DPRINTF uses Decode debug flag, which appears to be a copying error. This
patch changes this to the IEW Debug flag.
Faissal Sleiman [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
cpu: Put in assertions to check for maximum supported LQ/SQ size
LSQSenderState represents the LQ/SQ index using uint8_t, which supports up to
256 entries (including the sentinel entry). Sending packets to memory with a
higher index than 255 truncates the index, such that the response matches the
wrong entry. For instance, this can result in a deadlock if a store completion
does not clear the head entry.
Dam Sunwoo [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
util: Streamline .apc project convertsion script
This Python script generates an ARM DS-5 Streamline .apc project based
on gem5 run. To successfully convert, the gem5 runs needs to be run
with the context-switch-based stats dump option enabled (The guest
kernel also needs to be patched to allow gem5 interrogate its task
information.) See help for more information.
Eric Van Hensbergen [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
arm: Accomodate function name changes in newer linux kernels
Ali Saidi [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
arm: Fix a GIC mask register bug
This resulted in a kernel printk that said,
"GIC CPU mask not found - kernel will fail to boot."
Ali Saidi [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
cpu: Fix O3 uncacheable load that is replayed but misses the TLB
This change fixes an issue in the O3 CPU where an uncachable instruction
is attempted to be executed before it reaches the head of the ROB. It is
determined to be uncacheable, and is replayed, but a PanicFault is attached
to the instruction to make sure that it is properly executed before
committing. If the TLB entry it was using is replaced in the interveaning
time, the TLB returns a delayed translation when the load is replayed at
the head of the ROB, however the LSQ code can't differntiate between the
old fault and the new one. If the translation isn't complete it can't
be faulting, so clear the fault.
Ali Saidi [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
mem: Make MemoryAccess flag more verbose
This patch extends the MemoryAccess debug flag to report who sent the
requests and the cacheability.
Andreas Hansson [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
build: Place proto output in the same directory, also for EXTRAS
This patch changes the ProtoBuf builder such that the generated source
and header is placed in the build directory of the proto file. This
was previously not the case for the directories included as EXTRAS. To
make this work, we also ensure that the build directory for the EXTRAS
are added to the include path (which does not seem to automatically be
the case).
Ali Saidi [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
arm, config: Fix a small issue with the dtb file being specified
Ali Saidi [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
config: Fix memtest example script
Ali Saidi [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
dev: Allow additional UART interrupts to be set
This patch allows setting a few additional interrupts for status
changes that should never occur.
Stan Czerniawski [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
build: Enable color diagnostics in clang by preserving TERM.
Andreas Sandberg [Wed, 16 Oct 2013 16:12:15 +0000 (18:12 +0200)]
kvm: Fix latency calculation of IPR accesses
When handling IPR accesses in doMMIOAccess, the KVM CPU used
clockEdge() to convert between cycles and ticks. This is incorrect
since doMMIOAccess is supposed to return a latency in ticks rather
than when the access is done. This changeset fixes this issue by
returning clockPeriod() * ipr_delay instead.
Steve Reinhardt [Wed, 16 Oct 2013 14:44:12 +0000 (10:44 -0400)]
test: update stats
Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
Steve Reinhardt [Tue, 15 Oct 2013 22:22:49 +0000 (18:22 -0400)]
ruby: eliminate non-determinism from ruby.stats output
Get rid of non-deterministic "stats" in ruby.stats output
such as time & date of run, elapsed & CPU time used,
and memory usage. These values cause spurious
miscomparisons when looking at output diffs (though
they don't affect regressions, since the regressions
pass/fail status currently ignores ruby.stats entirely).
Most of this information is already captured in other
places (time & date in stdout, elapsed time & mem usage
in stats.txt), where the regression script is smart
enough to filter it out. It seems easier to get rid of
the redundant output rather than teaching the
regression tester to ignore the same information in
two different places.
Steve Reinhardt [Tue, 15 Oct 2013 22:22:41 +0000 (18:22 -0400)]
scons: fix minor update-ref bug in regressions
In the unusual case that regressions are run with --update-ref
when there is no existing regression output, scons gets
confused because it depends on stats.txt to trigger the
update, but it has no indication that running the test will
generate the stats.txt file. (In the typical case where
stats.txt already exists, scons doesn't care about where
it came from.)
It's easy to fix this just by adding the stats.txt file
to the target list for the test action.
Yasuko Eckert [Tue, 15 Oct 2013 18:22:44 +0000 (14:22 -0400)]
arch/x86: add support for explicit CC register file
Convert condition code registers from being specialized
("pseudo") integer registers to using the recently
added CC register class.
Nilay Vaish also contributed to this patch.
Yasuko Eckert [Tue, 15 Oct 2013 18:22:44 +0000 (14:22 -0400)]
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Steve Reinhardt [Tue, 15 Oct 2013 18:22:44 +0000 (14:22 -0400)]
cpu/o3: clean up rename map and free list
Restructured rename map and free list to clean up some
extraneous code and separate out common code that can
be reused across different register classes (int and fp
at this point). Both components now consist of a set
of Simple* objects that are stand-alone rename map &
free list for each class, plus a Unified* object that
presents a unified interface across all register
classes and then redirects accesses to the appropriate
Simple* object as needed.
Moved free list initialization to PhysRegFile to better
isolate knowledge of physical register index mappings
to that class (and remove the need to pass a number
of parameters to the free list constructor).
Causes a small change to these stats:
cpu.rename.int_rename_lookups
cpu.rename.fp_rename_lookups
because they are now categorized on a per-operand basis
rather than a per-instruction basis.
That is, an instruction with mixed fp/int/misc operand
types will have each operand categorized independently,
where previously the lookup was categorized based on
the instruction type.
Steve Reinhardt [Tue, 15 Oct 2013 18:22:43 +0000 (14:22 -0400)]
cpu: rename *_DepTag constants to *_Reg_Base
Make these names more meaningful.
Specifically, made these substitutions:
s/FP_Base_DepTag/FP_Reg_Base/g;
s/Ctrl_Base_DepTag/Misc_Reg_Base/g;
s/Max_DepTag/Max_Reg_Index/g;
Steve Reinhardt [Tue, 15 Oct 2013 18:22:43 +0000 (14:22 -0400)]
isa: clean up register constants
Clean up and add some consistency to the *_Base_DepTag
constants as well as some related register constants:
- Get rid of NumMiscArchRegs, TotalArchRegs, and TotalDataRegs
since they're never used and not always defined
- Set FP_Base_DepTag = NumIntRegs when possible (i.e.,
every case except x86)
- Set Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs
(this was true before, but wasn't always expressed
that way)
- Drastically reduce the number of arbitrary constants
appearing in these calculations
Steve Reinhardt [Tue, 15 Oct 2013 18:22:43 +0000 (14:22 -0400)]
cpu/o3: clean up scoreboard object
It had a bunch of fields (and associated constructor
parameters) thet it didn't really use, and the array
initialization was needlessly verbose.
Also just hardwired the getReg() method to aleays
return true for misc regs, rather than having an array
of bits that we always kept marked as ready.
Steve Reinhardt [Tue, 15 Oct 2013 18:22:43 +0000 (14:22 -0400)]
cpu/o3: clean up physical register file
No need for PhysRegFile to be a template class, or
have a pointer back to the CPU. Also made some methods
for checking the physical register type (int vs. float)
based on the phys reg index, which will come in handy later.
Steve Reinhardt [Tue, 15 Oct 2013 18:22:43 +0000 (14:22 -0400)]
cpu/inorder: merge register class enums
The previous patch introduced a RegClass enum to clean
up register classification. The inorder model already
had an equivalent enum (RegType) that was used internally.
This patch replaces RegType with RegClass to get rid
of the now-redundant code.
Steve Reinhardt [Tue, 15 Oct 2013 18:22:42 +0000 (14:22 -0400)]
cpu: clean up architectural register classification
Move from a poorly documented scheme where the mapping
of unified architectural register indices to register
classes is hardcoded all over to one where there's an
enum for the register classes and a function that
encapsulates the mapping.
Andreas Sandberg [Tue, 15 Oct 2013 11:26:34 +0000 (13:26 +0200)]
mem: Rename the ASI_BITS flag field in Request
ASI_BITS in the Request object were originally used to store a memory
request's ASI on SPARC. This is not the case any more since other ISAs
use the ASI bits to store architecture-dependent information. This
changeset renames the ASI_BITS to ARCH_BITS which better describes
their use. Additionally, the getAsi() accessor is renamed to
getArchFlags().
Andreas Sandberg [Tue, 15 Oct 2013 11:24:35 +0000 (13:24 +0200)]
mem: Use a flag instead of address bit 63 for generic IPRs
Using address bit 63 to identify generic IPRs caused problems on
SPARC, where IPRs are heavily used. This changeset redefines how
generic IPRs are identified. Instead of using bit 63, we now use a
separate flag (GENERIC_IPR) a memory request.
Nilay Vaish [Mon, 14 Oct 2013 18:58:02 +0000 (13:58 -0500)]
Added tag stable_2013_10_14 to the changeset
6a043adb1e8d
Nilay Vaish [Wed, 9 Oct 2013 22:28:14 +0000 (17:28 -0500)]
config: correct example ruby scripts
A couple of recent changesets added/deleted/edited some variables
that are needed for running the example ruby scripts. This changeset
edits these scripts to bring them to a working state.
Andreas Hansson [Wed, 9 Oct 2013 08:41:19 +0000 (04:41 -0400)]
stats: Bump pc-simple-timing-ruby stats
This patch simply brings the stats for the pc-simple-timing-ruby
regression up to date. The particular regression seems to give
different results on different systems unfortunately, and this update
reflects the current behaviour on zizzer.
Nilay Vaish [Mon, 7 Oct 2013 23:05:50 +0000 (18:05 -0500)]
config: set cwd for processes in se.py
Nilay Vaish [Mon, 7 Oct 2013 23:05:49 +0000 (18:05 -0500)]
x86: enables lstat and readlink syscalls
Andreas Sandberg [Mon, 7 Oct 2013 14:03:15 +0000 (16:03 +0200)]
base: Fix a potential race in PollQueue::setupAsyncIO
There is a potential race between enabling asynchronous IO and
selecting the target for the SIGIO signal. This changeset move the
F_SETOWN call to before the F_SETFL call that enables SIGIO
delivery. This ensures that signals are always sent to the correct
process.
Andreas Sandberg [Thu, 3 Oct 2013 09:00:18 +0000 (11:00 +0200)]
kvm: Service events in the instruction event queues
This changset adds calls to the service the instruction event queues
that accidentally went missing from commit [
0063c7dd18ec]. The
original commit only included the code needed to schedule instruction
stops from KVM and missed the functionality to actually service the
events.
Andreas Hansson [Wed, 2 Oct 2013 10:08:45 +0000 (06:08 -0400)]
kvm: Only include KVM support for supported kernels
This patch adds a check to ensure that the KVM API provided by the
running kernel is what we are expecting.
Andreas Hansson [Wed, 2 Oct 2013 10:08:43 +0000 (06:08 -0400)]
ext: Fix fputils compiler flags to ensure ISO C99
The fp code relies on C99, and depending on gcc version, the default
is to use c89. This patch adds -std=c99 when using gcc to ensure the
code is compiled in ISO C99 mode.
Andreas Sandberg [Wed, 2 Oct 2013 09:03:38 +0000 (11:03 +0200)]
stats: Update x86 stats after x87 fixes
The updates to the x87 caused the stats for several regressions to
change. This was mainly caused by the addition of a working 32-bit and
80-bit FP load instruction and xsave support.
Andreas Sandberg [Tue, 1 Oct 2013 13:56:47 +0000 (15:56 +0200)]
scons, kvm: Check for the presence of POSIX timers
The kvm-based CPU module requires support for POSIX timers. This
changeset adds a check for POSIX timers and ensures that gem5 is
linked with librt if necessary. KVM support is disabled if POSIX
timers are not supported by the host. This fixes a compilation issue
for some glibc versions where clock_nanosleep and timer_create are in
different libraries.
Andreas Sandberg [Tue, 1 Oct 2013 13:19:56 +0000 (15:19 +0200)]
ext: Update fputils to rev
52b6190b4e
This changeset updates the external library to git revision
52b6190b4e. This update includes changes that fix compilation errors
on old gcc versions and fixes to test a case that affect ICC.
Andreas Sandberg [Mon, 30 Sep 2013 10:20:53 +0000 (12:20 +0200)]
x86: Add support for m5ops through a memory mapped interface
In order to support m5ops in virtualized environments, we need to use
a memory mapped interface. This changeset adds support for that by
reserving 0xFFFF0000-0xFFFFFFFF and mapping those to the generic IPR
interface for m5ops. The mapping is done in the
X86ISA::TLB::finalizePhysical() which means that it just works for all
of the CPU models, including virtualized ones.
Andreas Sandberg [Mon, 30 Sep 2013 10:20:43 +0000 (12:20 +0200)]
arch: Add support for m5ops using mmapped IPRs
In order to support m5ops on virtualized CPUs, we need to either
intercept hypercall instructions or provide a memory mapped m5ops
interface. Since KVM does not normally pass the results of hypercalls
to userspace, which makes that method unfeasible. This changeset
introduces support for m5ops using memory mapped mmapped IPRs. This is
implemented by adding a class of "generic" IPRs which are handled by
architecture-independent code. Such IPRs always have bit 63 set and
are handled by handleGenericIprRead() and
handleGenericIprWrite(). Platform specific impementations of
handleIprRead and handleIprWrite should use
GenericISA::isGenericIprAccess to determine if an IPR address should
be handled by the generic code instead of the architecture-specific
code. Platforms that don't need their own IPR support can reuse
GenericISA::handleIprRead() and GenericISA::handleIprWrite().
Andreas Sandberg [Mon, 30 Sep 2013 10:06:36 +0000 (12:06 +0200)]
x86: Add support for FXSAVE, FXSAVE64, FXRSTOR, and FXRSTOR64
Andreas Sandberg [Mon, 30 Sep 2013 10:04:36 +0000 (12:04 +0200)]
x86: Add support for FLDENV & FNSTENV
Andreas Sandberg [Mon, 30 Sep 2013 10:00:20 +0000 (12:00 +0200)]
x86: Add support for loading 32-bit and 80-bit floats in the x87
The x87 FPU supports three floating point formats: 32-bit, 64-bit, and
80-bit floats. The current gem5 implementation supports 32-bit and
64-bit floats, but only works correctly for 64-bit floats. This
changeset fixes the 32-bit float handling by correctly loading and
rounding (using truncation) 32-bit floats instead of simply truncating
the bit pattern.
80-bit floats are loaded by first loading the 80-bits of the float to
two temporary integer registers. A micro-op (cvtint_fp80) then
converts the contents of the two integer registers to the internal FP
representation (double). Similarly, when storing an 80-bit float,
there are two conversion routines (ctvfp80h_int and cvtfp80l_int) that
convert an internal FP register to 80-bit and stores the upper 64-bits
or lower 32-bits to an integer register, which is the written to
memory using normal integer stores.
Andreas Sandberg [Mon, 30 Sep 2013 09:51:25 +0000 (11:51 +0200)]
x86: Fix re-entrancy problems in x87 store instructions
X87 store instructions typically loads and pops the top value of the
stack and stores it in memory. The current implementation pops the
stack at the same time as the floating point value is loaded to a
temporary register. This will corrupt the state of the x87 stack if
the store fails. This changeset introduces a pop87 micro-instruction
that pops the stack and uses this instruction in the affected
macro-instructions to pop the stack after storing the value to memory.
Andreas Sandberg [Mon, 30 Sep 2013 07:53:52 +0000 (09:53 +0200)]
kvm: Add support for thread-specific instruction events
Instruction events are currently ignored when executing in KVM. This
changeset adds support for triggering KVM exits based on instruction
counts using hardware performance counters. Depending on the
underlying performance counter implementation, there might be some
inaccuracies due to instructions being counted in the host kernel when
entering/exiting KVM.
Due to limitations/bugs in Linux's performance counter interface, we
can't reliably change the period of an overflow counter. We work
around this issue by detaching and reattaching the counter if we need
to reconfigure it.
Andreas Sandberg [Mon, 30 Sep 2013 07:45:43 +0000 (09:45 +0200)]
config: Add a 'kvm' CPU alias
Add a CPU alias, 'kvm', for the first available KVM-accelerated CPU
model.
Andreas Sandberg [Mon, 30 Sep 2013 07:43:43 +0000 (09:43 +0200)]
kvm: FPU synchronization support on x86
This changeset adds support for synchronizing the FPU and SIMD state
of a virtual x86 CPU with gem5. It supports both the XSave API and the
KVM_(GET|SET)_FPU kernel API. The XSave interface can be disabled
using the useXSave parameter (in case of kernel
issues). Unfortunately, KVM_(GET|SET)_FPU interface seems to be buggy
in some kernels (specifically, the MXCSR register isn't always
synchronized), which means that it might not be possible to
synchronize MXCSR on old kernels without the XSave interface.
This changeset depends on the __float80 type in gcc and might not
build using llvm.
Andreas Sandberg [Mon, 30 Sep 2013 07:42:30 +0000 (09:42 +0200)]
x86: Add support routines to load and store 80-bit floats
The x87 FPU on x86 supports extended floating point. We currently
handle all floating point on x86 as double and don't support 80-bit
loads/stores. This changeset add a utility function to load and
convert 80-bit floats to doubles (loadFloat80) and another function to
store doubles as 80-bit floats (storeFloat80). Both functions use
libfputils to do the conversion in software. The functions are
currently not used, but are required to handle floating point in KVM
and to properly support all x87 loads/stores.
Andreas Sandberg [Mon, 30 Sep 2013 07:40:26 +0000 (09:40 +0200)]
ext: Include libfputils
This changeset includes libfputils from revision
bbf0d61d75. This
library can be used to convert to and from 80-bit floats and query the
type of an 80-bit float, which is needed to support the x87 FPU.
Andreas Sandberg [Mon, 30 Sep 2013 07:37:17 +0000 (09:37 +0200)]
x86: Add limited support for extracting function call arguments
Add support for extracting the first 6 64-bit integer argumements to a
function call in X86ISA::getArgument().
Andreas Sandberg [Mon, 30 Sep 2013 07:36:54 +0000 (09:36 +0200)]
kvm: x86: Fix segment registers to make them VMX compatible
There are cases when the segment registers in gem5 are not compatible
with VMX. This changeset works around all known such issues. Specifically:
* The accessed bits in CS, SS, DD, ES, FS, GS are forced to 1.
* The busy bit in TR is forced to 1.
* The protection level of SS is forced to the same protection level as
CS. The difference /seems/ to be caused by a bug in gem5's x86
implementation.
Steve Reinhardt [Sat, 28 Sep 2013 19:25:17 +0000 (15:25 -0400)]
tests: update reference outputs
Apparently only stats.txt was updated the last time, so
this changeset updates other reference output files
(config.ini, simout, simerr, ruby.stats) so that
test output diffs should not be cluttered with irrelevant
changes. There are a few stats.txt updates too, but
they are in the minority.
Andreas Sandberg [Wed, 25 Sep 2013 10:35:21 +0000 (12:35 +0200)]
kvm: Add x86 segment register verification to help debugging
Andreas Sandberg [Wed, 25 Sep 2013 10:24:26 +0000 (12:24 +0200)]
kvm: Initial x86 support
This changeset adds support for KVM on x86. Full support is split
across a number of commits since some features are relatively
complex. This changeset includes support for:
* Integer state synchronization (including segment regs)
* CPUID (gem5's CPUID values are inserted into KVM)
* x86 legacy IO (remapped and handled by gem5's memory system)
* Memory mapped IO
* PCI
* MSRs
* State dumping
Most of the functionality is fairly straight forward. There are some
quirks to support PCI enumerations since this is done in the TLB(!) in
the simulated CPUs. We currently replicate some of that code.
Unlike the ARM implementation, the x86 implementation of the virtual
CPU does not use the cycles hardware counter. KVM on x86 simulates the
time stamp counter (TSC) in the kernel. If we just measure host cycles
using perfevent, we might end up measuring a slightly different number
of cycles. If we don't get the cycle accounting right, we might end up
rewinding the TSC, with all kinds of chaos as a result.
An additional feature of the KVM CPU on x86 is extended state
dumping. This enables Python scripts controlling the simulator to
request dumping of a subset of the processor state. The following
methods are currenlty supported:
* dumpFpuRegs
* dumpIntRegs
* dumpSpecRegs
* dumpDebugRegs
* dumpXCRs
* dumpXSave
* dumpVCpuEvents
* dumpMSRs
Known limitations:
* M5 ops are currently not supported.
* FPU synchronization is not supported (only affects CPU switching).
Both of the limitations will be addressed in separate commits.
Andreas Sandberg [Thu, 19 Sep 2013 15:55:04 +0000 (17:55 +0200)]
kvm: Correctly handle the return value from handleIpr(Read|Write)
The KVM base class incorrectly assumed that handleIprRead and
handleIprWrite both return ticks. This is not the case, instead they
return cycles. This changeset converts the returned cycles to ticks
when handling IPR accesses.
Andreas Sandberg [Thu, 19 Sep 2013 15:55:03 +0000 (17:55 +0200)]
kvm: Fix a case where the run timers weren't armed properly
There is a possibility that the timespec used to arm a timer becomes
zero if the number of ticks used when arming a timer is close to the
resolution of the timer. Due to the semantics of POSIX timers, this
actually disarms the timer. This changeset fixes this issue by
eliminating the rounding error (we always round away from zero
now). It also reuses the minimum number of cycles, which were
previously only used for cycle-based timers, to calculate a more
useful resolution.
Andreas Sandberg [Thu, 19 Sep 2013 15:30:26 +0000 (17:30 +0200)]
x86: Add support routines to convert between x87 tag formats
This changeset adds the convX87XTagsToTags() and convX87TagsToXTags()
which convert between the tag formats in the FTW register and the
format used in the xsave area. The conversion from to the x87 FTW
representation is currently loses some information since it does not
reconstruct the valid/zero/special flags which are not included in the
xsave representation.
Andreas Sandberg [Wed, 18 Sep 2013 15:08:35 +0000 (17:08 +0200)]
sim: Fix undefined behavior in the pseudo-inst interface
The order between updating and using arg_num in
PseudoInst::pseudoInst() is currently undefined. This changeset
explicitly updates arg_num after it has been used to extract an
argument.
--HG--
extra : rebase_source :
67c46dc3333d16ce56687ee8aea41ce6c6d133bb
Andreas Hansson [Wed, 18 Sep 2013 12:46:33 +0000 (08:46 -0400)]
mem: Fix scheduling bug in SimpleMemory
This patch ensures that a dequeue event is not scheduled if the memory
controller is waiting for a retry already. Without this check it is
possible for the controller to attempt sending something whilst
already having one packet that is in retry, thus causing the bus to
have an assertion failure.
Andreas Hansson [Wed, 18 Sep 2013 12:46:32 +0000 (08:46 -0400)]
swig: Warn on use of incompatible swig/gcc combinations
This patch removes the fixed swig warning concerning 2.0.9/2.0.10 and
adds a warning message for incompatible combinations of swig and gcc.
Andreas Hansson [Wed, 18 Sep 2013 12:46:31 +0000 (08:46 -0400)]
swig: Fix issue with circular import in 2.0.9/2.0.10
This patch fixes an issue which prevented gem5 from running when built
using swig 2.0.9 and 2.0.10. The generated event.py tried to import
m5.internal which in turn relied on importing event. This patch seems
to fix the problem, and so far has not caused any other issues.
Andreas Sandberg [Wed, 18 Sep 2013 09:28:28 +0000 (11:28 +0200)]
x86: Expose the raw hash map of MSRs
This patch allows the KVM CPU module to initialize it's MSRs by
enumerating the MSRs in the gem5 x86 implementation.
Andreas Sandberg [Wed, 18 Sep 2013 09:28:27 +0000 (11:28 +0200)]
x86: Add support for checking the raw state of an interrupt
In order to support hardware virtualization, we need to be able to
check if there are any interrupts pending irregardless of the
rflags.intf value. This changeset adds the checkInterruptsRaw() method
to the x86 interrupt control. It returns true if there are pending
interrupts that can be delivered as soon as the CPU is ready for
interrupt delivery.
Andreas Sandberg [Wed, 18 Sep 2013 09:28:24 +0000 (11:28 +0200)]
x86: Expose the interrupt vector in faults
This patch allows a hardware virtualized CPU to discover which interrupt
to deliver to the guest.
Joel Hestness [Wed, 18 Sep 2013 00:39:11 +0000 (19:39 -0500)]
configs: Fix ruby_fs.py cache line size
Recent changes added setting of system-wide cache line size and these settings
occur in the top-level configs (se.py and fs.py). This setting also needs to
take place in ruby_fs.py. This change sets the cache line size as appropriate.
Nilay Vaish [Sun, 15 Sep 2013 18:45:59 +0000 (13:45 -0500)]
stats: update sparc fs due to recent changes to memory class.
Andreas Hansson [Thu, 12 Sep 2013 21:49:12 +0000 (17:49 -0400)]
config: Add voltage domain to Ruby example scripts
This patch adds the minimum required voltage domain configuration to
the Ruby example scripts.
Joel Hestness [Wed, 11 Sep 2013 20:35:18 +0000 (15:35 -0500)]
ruby: Fix Topology throttle connections
The Topology source sets up input and output buffers for each of the external
nodes of a topology by indexing on Ruby's generated controller unique IDs.
These unique IDs are found by adding the MachineType_base_number to the version
number of each controller (see any generated *_Controller.cc - init() calls
getToNetQueue and getFromNetQueue using m_version + base). However, the
Topology object used the cntrl_id - which is required to be unique across all
controllers - to index the controllers list as they are being connected to
their input and output buffers. If the cntrl_ids did not match the Ruby unique
ID, the throttles end up connected to incorrectly indexed nodes in the network,
resulting in packets traversing incorrect network paths. This patch fixes the
Topology indexing scheme by using the Ruby unique ID to match that of the
SimpleNetwork buffer vectors.
Joel Hestness [Wed, 11 Sep 2013 20:34:50 +0000 (15:34 -0500)]
cpu: Dynamically instantiate O3 CPU LSQUnits
Previously, the LSQ would instantiate MaxThreads LSQUnits in the body of it's
object, but it would only initialize numThreads LSQUnits as specified by the
user. This had the effect of leaving some LSQUnits uninitialized when the
number of threads was less than MaxThreads, and when adding statistics to the
LSQUnit that must be initialized, this caused the stats initialization check to
fail. By dynamically instantiating LSQUnits, they are all initialized and this
avoids uninitialized LSQUnits from floating around during runtime.
Joel Hestness [Wed, 11 Sep 2013 20:34:21 +0000 (15:34 -0500)]
config: Initialize and check cpt_starttick
The previous changeset (9816) that fixes the use of max ticks introduced the
variable cpt_starttick, which is used for setting the relative max tick.
Unfortunately, with checkpointing at an instruction count or with simpoints,
the checkpoint tick is not stored conveniently, so to ensure that cpt_starttick
is initialized, set it to 0. Also, if using --rel-max-tick, check the use of
instruction counts or simpoints to warn the user that the max tick setting does
not include the checkpoint ticks.
Joel Hestness [Wed, 11 Sep 2013 20:33:27 +0000 (15:33 -0500)]
ruby: Statically allocate stats in SimpleNetwork, Switch, Throttle
The previous changeset (9863:
9483739f83ee) used STL vector containers to
dynamically allocate stats in the Ruby SimpleNetwork, Switch and Throttle. For
gcc versions before at least 4.6.3, this causes the standard vector allocator
to call Stats copy constructors (a no-no, since stats should be allocated in
the body of each SimObject instance). Since the size of these stats arrays is
known at compile time (NOTE: after code generation), this patch changes their
allocation to be static rather than using an STL vector.
Nilay Vaish [Mon, 9 Sep 2013 23:52:23 +0000 (18:52 -0500)]
stats: add operator= for DataWrapVec class
gcc/g++ 4.4.7 complained about the operator= being undefined.
This changeset adds the operator.
Nilay Vaish [Fri, 6 Sep 2013 21:21:36 +0000 (16:21 -0500)]
stats: ruby: updates due to recent changes.
Nilay Vaish [Fri, 6 Sep 2013 21:21:35 +0000 (16:21 -0500)]
ruby: network: convert to gem5 style stats
Nilay Vaish [Fri, 6 Sep 2013 21:21:33 +0000 (16:21 -0500)]
ruby: network: correct naming of routers
The routers are created before the network class. This results in the routers
becoming children of the first link they are connected to and they get generic
names like int_node and node_b. This patch creates the network object first
and passes it to the topology creation function. Now the routers are children
of the network object and names are much more sensible.
Nilay Vaish [Fri, 6 Sep 2013 21:21:32 +0000 (16:21 -0500)]
ruby: profiler: removes function resourceUsage()