litex.git
9 years agotargets: add Lattice ECP3 versa
Florent Kermarrec [Tue, 17 Mar 2015 18:08:31 +0000 (19:08 +0100)]
targets: add Lattice ECP3 versa

9 years agolitescope/drivers: do not build regs when addrmap is None
Florent Kermarrec [Tue, 17 Mar 2015 15:04:07 +0000 (16:04 +0100)]
litescope/drivers: do not build regs when addrmap is None

9 years agoLiteXXX cores: fix frequency print in test/test_regs.py
Florent Kermarrec [Tue, 17 Mar 2015 15:01:12 +0000 (16:01 +0100)]
LiteXXX cores: fix frequency print in test/test_regs.py

9 years agoLiteXXX cores: convert port parameter to int if is digit in test/make.py
Florent Kermarrec [Tue, 17 Mar 2015 14:58:21 +0000 (15:58 +0100)]
LiteXXX cores: convert port parameter to int if is digit in test/make.py

9 years agoliteeth/phy/gmii : set tx_er to 0 only if it exits
Florent Kermarrec [Tue, 17 Mar 2015 11:24:06 +0000 (12:24 +0100)]
liteeth/phy/gmii : set tx_er to 0 only if it exits

9 years agoliteeth: use default programmer in make.py
Florent Kermarrec [Tue, 17 Mar 2015 11:12:21 +0000 (12:12 +0100)]
liteeth: use default programmer in make.py

9 years agoliteeth: use CRG from Migen in base example
Florent Kermarrec [Tue, 17 Mar 2015 11:11:51 +0000 (12:11 +0100)]
liteeth: use CRG from Migen in base example

9 years agolitescope: use CRG from Migen
Florent Kermarrec [Tue, 17 Mar 2015 10:52:54 +0000 (11:52 +0100)]
litescope: use CRG from Migen

9 years agotargets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC...
Florent Kermarrec [Tue, 17 Mar 2015 00:07:44 +0000 (01:07 +0100)]
targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains)

9 years agoliteeth: make gmii phy generic
Florent Kermarrec [Mon, 16 Mar 2015 22:04:37 +0000 (23:04 +0100)]
liteeth: make gmii phy generic

9 years agolitesata: avoid hack on kc705 platform with new mibuild toolchain management
Florent Kermarrec [Sat, 14 Mar 2015 00:08:36 +0000 (01:08 +0100)]
litesata: avoid hack on kc705 platform with new mibuild toolchain management

9 years agosoc: rename with_sdram option to with_main_ram (with_sdram was confusing)
Florent Kermarrec [Fri, 13 Mar 2015 23:46:52 +0000 (00:46 +0100)]
soc: rename with_sdram option to with_main_ram (with_sdram was confusing)

9 years agotargets/simple: use mibuild default clock
Sebastien Bourdeauducq [Fri, 13 Mar 2015 23:11:59 +0000 (00:11 +0100)]
targets/simple: use mibuild default clock

9 years agosoc/sdram: sync with new mibuild toolchain management
Sebastien Bourdeauducq [Fri, 13 Mar 2015 22:19:08 +0000 (23:19 +0100)]
soc/sdram: sync with new mibuild toolchain management

9 years agoliteeth/phy: typo (thanks sb)
Florent Kermarrec [Thu, 12 Mar 2015 20:54:10 +0000 (21:54 +0100)]
liteeth/phy: typo (thanks sb)

9 years agotargets/simple: use new generic DifferentialInput
Florent Kermarrec [Thu, 12 Mar 2015 17:36:04 +0000 (18:36 +0100)]
targets/simple: use new generic DifferentialInput

9 years agotargets/simple: insert IBUFDS for Xilinx devices (not implemented for others vendors)
Florent Kermarrec [Thu, 12 Mar 2015 16:25:01 +0000 (17:25 +0100)]
targets/simple: insert IBUFDS for Xilinx devices (not implemented for others vendors)

9 years agosoc/sdram: add workaround for Vivado issue with our L2 cache, reported to Xilinx...
Florent Kermarrec [Thu, 12 Mar 2015 16:12:35 +0000 (17:12 +0100)]
soc/sdram: add workaround for Vivado issue with our L2 cache, reported to Xilinx in november 2014, remove it when fixed by Xilinx

9 years agouart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported...
Florent Kermarrec [Thu, 12 Mar 2015 15:57:38 +0000 (16:57 +0100)]
uart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported on Windows since based on pty).

9 years agouart/sim: add pty (optional, to use flterm)
Florent Kermarrec [Mon, 9 Mar 2015 22:29:06 +0000 (23:29 +0100)]
uart/sim: add pty (optional, to use flterm)

9 years agoliteeth/mac: fix padding limit (+1), netboot OK with sim platform
Florent Kermarrec [Mon, 9 Mar 2015 19:59:34 +0000 (20:59 +0100)]
liteeth/mac: fix padding limit (+1), netboot OK with sim platform

9 years agoliteeth/mac: use Counter in sram and move some logic outside of fsms
Florent Kermarrec [Mon, 9 Mar 2015 19:22:14 +0000 (20:22 +0100)]
liteeth/mac: use Counter in sram and move some logic outside of fsms

9 years agoliteeth/phy/sim: create ethernet tap in __init__ and destroy it in do_exit
Florent Kermarrec [Mon, 9 Mar 2015 16:21:29 +0000 (17:21 +0100)]
liteeth/phy/sim: create ethernet tap in __init__ and destroy it in do_exit

9 years agosoc: do_exit is now provided by modules
Florent Kermarrec [Mon, 9 Mar 2015 16:18:42 +0000 (17:18 +0100)]
soc: do_exit is now provided by modules

9 years agoliteeth: fix cnt_inc in IDLE state (we should wait sop to inc counter)
Florent Kermarrec [Mon, 9 Mar 2015 11:45:46 +0000 (12:45 +0100)]
liteeth: fix cnt_inc in IDLE state (we should wait sop to inc counter)

9 years agoliteeth: do not insert CRC/Preamble in simulation to allow direct connection to ether...
Florent Kermarrec [Mon, 9 Mar 2015 11:48:45 +0000 (12:48 +0100)]
liteeth: do not insert CRC/Preamble in simulation to allow direct connection to ethernet tap

9 years agouart: pass *args, **kwargs to sim phy
Florent Kermarrec [Fri, 6 Mar 2015 11:08:10 +0000 (12:08 +0100)]
uart: pass *args, **kwargs to sim phy

9 years agouart: add phy autodetect function
Florent Kermarrec [Fri, 6 Mar 2015 09:19:29 +0000 (10:19 +0100)]
uart: add phy autodetect function

9 years agotargets/simple: add MiniSoC
Florent Kermarrec [Fri, 6 Mar 2015 09:10:58 +0000 (10:10 +0100)]
targets/simple: add MiniSoC

9 years agoliteeth: add phy autodetect function (phy can still be instanciated directly)
Florent Kermarrec [Fri, 6 Mar 2015 09:10:34 +0000 (10:10 +0100)]
liteeth: add phy autodetect function (phy can still be instanciated directly)

9 years agosoc: enforce cpu_reset_address to 0 when with_rom is True
Florent Kermarrec [Fri, 6 Mar 2015 07:21:16 +0000 (08:21 +0100)]
soc: enforce cpu_reset_address to 0 when with_rom is True

9 years agotargets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdr...
Florent Kermarrec [Fri, 6 Mar 2015 06:51:44 +0000 (07:51 +0100)]
targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True)

9 years agoLiteXXX cores: fix test_reg.py
Florent Kermarrec [Wed, 4 Mar 2015 22:13:14 +0000 (23:13 +0100)]
LiteXXX cores: fix test_reg.py

9 years agoMerge branch 'master' of https://github.com/m-labs/misoc
Sebastien Bourdeauducq [Wed, 4 Mar 2015 00:46:41 +0000 (00:46 +0000)]
Merge branch 'master' of https://github.com/m-labs/misoc

9 years agolitesata: fix permissions and imports
Sebastien Bourdeauducq [Wed, 4 Mar 2015 00:46:24 +0000 (00:46 +0000)]
litesata: fix permissions and imports

9 years agouart: generate ack for rx (serialboot OK with sim)
Florent Kermarrec [Tue, 3 Mar 2015 23:57:37 +0000 (00:57 +0100)]
uart: generate ack for rx (serialboot OK with sim)

9 years agocom/spi: use .format in tb
Florent Kermarrec [Tue, 3 Mar 2015 09:44:05 +0000 (10:44 +0100)]
com/spi: use .format in tb

9 years agotargets: keep the SPI flash core even if with_rom is enabled, so that flash booting...
Florent Kermarrec [Tue, 3 Mar 2015 09:39:31 +0000 (10:39 +0100)]
targets: keep the SPI flash core even if with_rom is enabled, so that flash booting in the BIOS still works

9 years agoLiteXXX cores: use format in prints
Florent Kermarrec [Tue, 3 Mar 2015 09:29:28 +0000 (10:29 +0100)]
LiteXXX cores: use format in prints

9 years agolitesata: remove unneeded clock constraint
Florent Kermarrec [Tue, 3 Mar 2015 09:24:05 +0000 (10:24 +0100)]
litesata: remove unneeded clock constraint

9 years agosoc: remove is_sim function
Florent Kermarrec [Tue, 3 Mar 2015 09:15:11 +0000 (10:15 +0100)]
soc: remove is_sim function

9 years agosdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move...
Florent Kermarrec [Tue, 3 Mar 2015 08:49:57 +0000 (09:49 +0100)]
sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy

9 years agosdram: pass phy_settings to LASMIcon, MiniCON and init_sequence
Florent Kermarrec [Tue, 3 Mar 2015 08:14:30 +0000 (09:14 +0100)]
sdram: pass phy_settings to LASMIcon, MiniCON and init_sequence

9 years agosdram: revert use of scalar values for DFIInjector
Florent Kermarrec [Tue, 3 Mar 2015 08:09:14 +0000 (09:09 +0100)]
sdram: revert use of scalar values for DFIInjector

9 years agolasmicon: better management of optional bandwidth module (automatically inserted...
Florent Kermarrec [Tue, 3 Mar 2015 08:02:53 +0000 (09:02 +0100)]
lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True)

9 years agolitesata/kc705: use FMC pin names
Sebastien Bourdeauducq [Tue, 3 Mar 2015 01:02:50 +0000 (01:02 +0000)]
litesata/kc705: use FMC pin names

9 years agospiflash: style
Sebastien Bourdeauducq [Tue, 3 Mar 2015 00:54:30 +0000 (00:54 +0000)]
spiflash: style

9 years agoREADME: 80 columns
Sebastien Bourdeauducq [Tue, 3 Mar 2015 00:17:34 +0000 (00:17 +0000)]
README: 80 columns

9 years agomake.py: use ternary getattr
Sebastien Bourdeauducq [Mon, 2 Mar 2015 23:54:00 +0000 (23:54 +0000)]
make.py: use ternary getattr

9 years agosdram: disable by default bandwidth_measurement on lasmicon
Florent Kermarrec [Mon, 2 Mar 2015 18:53:16 +0000 (19:53 +0100)]
sdram: disable by default bandwidth_measurement on lasmicon

9 years agoREADME: add Pipistrello
Florent Kermarrec [Mon, 2 Mar 2015 18:18:46 +0000 (19:18 +0100)]
README: add Pipistrello

9 years agoupdate README
Florent Kermarrec [Mon, 2 Mar 2015 17:39:03 +0000 (18:39 +0100)]
update README

9 years agotargets: fix mlabs_video FramebufferSoC
Florent Kermarrec [Mon, 2 Mar 2015 17:38:43 +0000 (18:38 +0100)]
targets: fix mlabs_video FramebufferSoC

9 years agocpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems...
Florent Kermarrec [Mon, 2 Mar 2015 11:25:59 +0000 (12:25 +0100)]
cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)

9 years agosdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move...
Florent Kermarrec [Mon, 2 Mar 2015 11:05:50 +0000 (12:05 +0100)]
sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core

9 years agosoc/sdram: be more generic in naming
Florent Kermarrec [Mon, 2 Mar 2015 10:55:28 +0000 (11:55 +0100)]
soc/sdram: be more generic in naming

9 years agosdram: create core dir and move lasmicon/minicon in it
Florent Kermarrec [Mon, 2 Mar 2015 10:35:53 +0000 (11:35 +0100)]
sdram: create core dir and move lasmicon/minicon in it

9 years agosdram: rename self.phy_settings to self.settings (using phy.settings instead of phy...
Florent Kermarrec [Mon, 2 Mar 2015 10:21:13 +0000 (11:21 +0100)]
sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner)

9 years agosdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending...
Florent Kermarrec [Mon, 2 Mar 2015 09:59:43 +0000 (10:59 +0100)]
sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)

9 years agosdram: improve memtest by adding 2 different writes/reads
Florent Kermarrec [Mon, 2 Mar 2015 09:51:53 +0000 (10:51 +0100)]
sdram: improve memtest by adding 2 different writes/reads
doing only a write and read is not enough: if we reloaded a fpga with write that is not working after functional fpga, it would not trigger an error.

9 years agosdram: for now revert dat_ack change (it seems there is an small issue, will have...
Florent Kermarrec [Mon, 2 Mar 2015 09:28:53 +0000 (10:28 +0100)]
sdram: for now revert dat_ack change (it seems there is an small issue, will have a closer look)

9 years agosdram/lasmicon: create a separate file for the crossbar and remove it from lasmibus
Florent Kermarrec [Mon, 2 Mar 2015 08:18:32 +0000 (09:18 +0100)]
sdram/lasmicon: create a separate file for the crossbar and remove it from lasmibus

9 years agosdram: move dfii to phy
Florent Kermarrec [Mon, 2 Mar 2015 08:08:28 +0000 (09:08 +0100)]
sdram: move dfii to phy

9 years agosdram: fix remaining data_valid in dma_lasmi
Florent Kermarrec [Mon, 2 Mar 2015 08:05:18 +0000 (09:05 +0100)]
sdram: fix remaining data_valid in dma_lasmi

9 years agosdram: create test dir and move lasmicon/minicon tests to it
Florent Kermarrec [Mon, 2 Mar 2015 07:42:55 +0000 (08:42 +0100)]
sdram: create test dir and move lasmicon/minicon tests to it

9 years agosdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it
Florent Kermarrec [Mon, 2 Mar 2015 07:24:51 +0000 (08:24 +0100)]
sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it

9 years agolasmi: simplify usage for the user (it's the job of the controller to manage write...
Florent Kermarrec [Sun, 1 Mar 2015 20:22:12 +0000 (21:22 +0100)]
lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)

9 years agosoc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
Florent Kermarrec [Sun, 1 Mar 2015 17:25:47 +0000 (18:25 +0100)]
soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)

9 years agoflash/spi: make bitbang optional (enabled by default)
Florent Kermarrec [Sun, 1 Mar 2015 16:06:24 +0000 (17:06 +0100)]
flash/spi: make bitbang optional (enabled by default)

9 years agouart: use data instead of d on endpoint's layouts (coherency with others cores)
Florent Kermarrec [Sun, 1 Mar 2015 15:56:48 +0000 (16:56 +0100)]
uart: use data instead of d on endpoint's layouts (coherency with others cores)

9 years agouart: add sim phy
Florent Kermarrec [Sun, 1 Mar 2015 15:52:50 +0000 (16:52 +0100)]
uart: add sim phy

9 years agoliteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
Florent Kermarrec [Sun, 1 Mar 2015 15:45:50 +0000 (16:45 +0100)]
liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen

9 years agouart: create phy directory and move phy logic to serial.py (will enable selecting...
Florent Kermarrec [Sun, 1 Mar 2015 10:58:46 +0000 (11:58 +0100)]
uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)

9 years agolitesata: create example design derived from SoC
Florent Kermarrec [Sun, 1 Mar 2015 10:33:38 +0000 (11:33 +0100)]
litesata: create example design derived from SoC

9 years agoliteXXX cores: remove Identifier duplication
Florent Kermarrec [Sun, 1 Mar 2015 10:24:58 +0000 (11:24 +0100)]
liteXXX cores: remove Identifier duplication

9 years agoliteXXX cores: share same methodology for on-board tests
Florent Kermarrec [Sun, 1 Mar 2015 10:07:28 +0000 (11:07 +0100)]
liteXXX cores: share same methodology for on-board tests

9 years agolitesata: create specialized kc705 platform to avoid duplicating things already in...
Florent Kermarrec [Sun, 1 Mar 2015 10:03:15 +0000 (11:03 +0100)]
litesata: create specialized kc705 platform to avoid duplicating things already in mibuild

9 years agolitescope: avoid uart code duplication
Florent Kermarrec [Sun, 1 Mar 2015 08:53:51 +0000 (09:53 +0100)]
litescope: avoid uart code duplication

9 years agovideo: reintegrate dvisampler from mixxeo (DVI/HDMI interfaces are common in today...
Florent Kermarrec [Sun, 1 Mar 2015 09:01:23 +0000 (10:01 +0100)]
video: reintegrate dvisampler from mixxeo (DVI/HDMI interfaces are common in today's SoCs)

9 years agopipistrello: fix lpddr parameters, crg, flash, style
Robert Jordens [Sat, 28 Feb 2015 23:01:11 +0000 (16:01 -0700)]
pipistrello: fix lpddr parameters, crg, flash, style

9 years agosoc: fix register_rom
Florent Kermarrec [Sat, 28 Feb 2015 22:50:00 +0000 (23:50 +0100)]
soc: fix register_rom

9 years agoliteeth: create example design derived from SoC that can be used on all targets with...
Florent Kermarrec [Sat, 28 Feb 2015 22:08:50 +0000 (23:08 +0100)]
liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins

9 years agoliteXXX cores: remove setup.py and relative paths (we will install misolib of use...
Florent Kermarrec [Sat, 28 Feb 2015 21:23:48 +0000 (22:23 +0100)]
liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH)

9 years agolitescope: create example design derived from SoC that can be used on all targets
Florent Kermarrec [Sat, 28 Feb 2015 21:14:02 +0000 (22:14 +0100)]
litescope: create example design derived from SoC that can be used on all targets

9 years agoliteXXX cores: remove redefinition of get_csr_csv
Florent Kermarrec [Sat, 28 Feb 2015 20:45:05 +0000 (21:45 +0100)]
liteXXX cores: remove redefinition of get_csr_csv

9 years agoliteXXX cores: update README and doc
Florent Kermarrec [Sat, 28 Feb 2015 17:13:57 +0000 (18:13 +0100)]
liteXXX cores: update README and doc

9 years agosoc: use self.cpu_reset_address as rom mem_map address and increase default bios...
Florent Kermarrec [Sat, 28 Feb 2015 19:04:51 +0000 (20:04 +0100)]
soc: use self.cpu_reset_address as rom mem_map address and increase default bios size to 0xa000

9 years agotest implementation on all targets and fix issues
Florent Kermarrec [Sat, 28 Feb 2015 11:04:51 +0000 (12:04 +0100)]
test implementation on all targets and fix issues

9 years agomove mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog...
Florent Kermarrec [Sat, 28 Feb 2015 10:45:21 +0000 (11:45 +0100)]
move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future)

9 years agosoc: move SDRAMSoC to a separate sdram.py file (ideally part of SDRAMSoC should move...
Florent Kermarrec [Sat, 28 Feb 2015 10:44:14 +0000 (11:44 +0100)]
soc: move SDRAMSoC to a separate sdram.py file (ideally part of SDRAMSoC should move mem/sdram)

9 years agoremane GenSoC to SoC (more coherent and we will add support for multiple SoCs with...
Florent Kermarrec [Sat, 28 Feb 2015 10:36:15 +0000 (11:36 +0100)]
remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)

9 years agoliteusb: move files and modify import to misoclib.com.liteusb
Florent Kermarrec [Sat, 28 Feb 2015 10:18:00 +0000 (11:18 +0100)]
liteusb: move files and modify import to misoclib.com.liteusb

9 years agomerge liteusb
Florent Kermarrec [Sat, 28 Feb 2015 10:16:16 +0000 (11:16 +0100)]
merge liteusb

9 years agoliteeth: fix example design generation and remove VivadoProgrammer from platfom....
Florent Kermarrec [Sat, 28 Feb 2015 10:08:17 +0000 (11:08 +0100)]
liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates)

9 years agoliteeth: fix example design generation and remove VivadoProgrammer from platfom....
Florent Kermarrec [Sat, 28 Feb 2015 10:04:48 +0000 (11:04 +0100)]
liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates)

9 years agolitesata: move file and modify import to misoclib.mem.litesata
Florent Kermarrec [Sat, 28 Feb 2015 09:53:51 +0000 (10:53 +0100)]
litesata: move file and modify import to misoclib.mem.litesata

9 years agomerge litesata
Florent Kermarrec [Sat, 28 Feb 2015 09:48:08 +0000 (10:48 +0100)]
merge litesata

9 years agolitescope: create example_designs directory
Florent Kermarrec [Sat, 28 Feb 2015 09:38:28 +0000 (10:38 +0100)]
litescope: create example_designs directory

9 years agolitescope: move files and modify import to misoclib.tools.litescope
Florent Kermarrec [Sat, 28 Feb 2015 09:27:16 +0000 (10:27 +0100)]
litescope: move files and modify import to misoclib.tools.litescope

9 years agomerge litescope
Florent Kermarrec [Sat, 28 Feb 2015 09:24:49 +0000 (10:24 +0100)]
merge litescope