Steve Reinhardt [Fri, 18 Mar 2011 18:47:15 +0000 (11:47 -0700)]
swig: get rid of m5.internal.random module (swig/random.i)
Thanks to swig this was interfering with the standard Python
random module. The only function in that module was seed(),
which erroneously called srand48(). Moved the function to
m5.internal.core, renamed it seedRandom(), and made it call
random_mt.init() instead.
Steve Reinhardt [Fri, 18 Mar 2011 18:47:11 +0000 (11:47 -0700)]
base: disable FastAlloc in debug builds by default
FastAlloc's reuse policies can mask allocation bugs, so
we typically want it disabled when debugging. Set
FORCE_FAST_ALLOC to enable even when debugging, and set
NO_FAST_ALLOC to disable even in non-debug builds.
Ali Saidi [Fri, 18 Mar 2011 00:24:37 +0000 (19:24 -0500)]
Automated merge with ssh://hg@repo.m5sim.org/m5
Ali Saidi [Fri, 18 Mar 2011 00:20:22 +0000 (19:20 -0500)]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
Chris Emmons [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
ARM: Add minimal ARM_SE support for m5threads.
Updated some of the assembly code sequences to use armv7 instructions and
coprocessor 15 for storing the TLS pointer.
Ali Saidi [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
ARM: Fix subtle bug in LDM.
If the instruction faults mid-op the base register shouldn't be written back.
Ali Saidi [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
ARM: Implement the Instruction Set Attribute Registers (ISAR).
The ISAR registers describe which features the processor supports.
Transcribe the values listed in section B5.2.5 of the ARM ARM
into the registers as read-only values
Ali Saidi [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
ARM: Identify branches as conditional or unconditional and direct or indirect.
Ali Saidi [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
ARM: Bare metal system should have 256MB of RAM.
Ali Saidi [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
ARM: Fix small bug with VLDM/VSTM instructions.
Ali Saidi [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
ARM: Detect and skip udelay() functions in linux kernel.
This change speeds up booting, especially in MP cases, by not executing
udelay() on the core but instead skipping ahead tha amount of time that is being
delayed.
Ali Saidi [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
ARM: Allow conditional quiesce instructions.
This patch prevents not executed conditional instructions marked as
IsQuiesce from stalling the pipeline indefinitely. If the instruction
is not executed the quiesceSkip psuedoinst is called which schedules a
wakes up call to the fetch stage.
Ali Saidi [Fri, 18 Mar 2011 00:20:20 +0000 (19:20 -0500)]
Stats: Update the statistics for rfe patch.
Matt Horsnell [Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)]
ARM: Fix RFE macrop.
This changes the RFE macroop into 3 microops:
URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack
sp = sp + offset; // optionally auto-increment
PC = URa; CPSR = URb; // write to the PC and CPSR.
Importantly:
- writing to PC is handled in the last micro-op.
- loading occurs prior to state changes.
Matt Horsnell [Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)]
ARM: Rename registers used as temporary state by microops.
Ali Saidi [Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)]
O3: Send instruction back to fetch on squash to seed predecoder correctly.
Ali Saidi [Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)]
O3: Cleanup the commitInfo comm struct.
Get rid of unused members and use base types rather than derrived values
where possible to limit amount of state.
Ali Saidi [Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)]
ARM: Previous change didn't end up setting instFlags, this does.
Ali Saidi [Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)]
O3: Update regressions for mem block caching change.
Ali Saidi [Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)]
Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.
This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.
Ali Saidi [Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)]
O3: Fix unaligned stores when cache blocked
Without this change the a store can be issued to the cache multiple times.
If this case occurs when the l1 cache is out of mshrs (and thus blocked)
the processor will never make forward progress because each cycle it will
send a single request using the recently freed mshr and not completing the
multipart store. This will continue forever.
Lisa Hsu [Fri, 18 Mar 2011 00:08:35 +0000 (17:08 -0700)]
Ruby: minor bugfix, line did not adhere to some macro usage conventions.
Lisa Hsu [Fri, 18 Mar 2011 00:01:41 +0000 (17:01 -0700)]
Ruby: expose a simple mod function in slicc interface.
Ali Saidi [Thu, 17 Mar 2011 04:43:54 +0000 (00:43 -0400)]
X86: Update the stats for parser on x86 O3.
Gabe Black [Thu, 17 Mar 2011 02:08:41 +0000 (19:08 -0700)]
X86: Update the stats for gzip on x86 O3.
Gabe Black [Sat, 12 Mar 2011 22:41:30 +0000 (14:41 -0800)]
Regressions: Move the X86_FS regressions to "quick" instead of "long".
--HG--
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
Gabe Black [Sat, 12 Mar 2011 22:38:57 +0000 (14:38 -0800)]
Regressions: Make X86_FS run automatically.
Gabe Black [Fri, 11 Mar 2011 19:27:36 +0000 (11:27 -0800)]
SCons: Stop embedding the mercurial revision into the binary.
This causes a lot of rebuilds that could have otherwise possibly been
avoided, and, more annoyingly, a lot of unnecessary rerunning of the
regressions. The benefits of having the revision in the output haven't
materialized, so this change removes it.
Gabe Black [Fri, 11 Mar 2011 19:27:26 +0000 (11:27 -0800)]
Gems: Eliminate the now unused GEMS_ROOT scons variable.
Gabe Black [Fri, 11 Mar 2011 19:27:16 +0000 (11:27 -0800)]
Ruby: Get rid of the dead ruby tester.
None of the code in the ruby tester directory is compiled or referred to
outside of that directory. This change eliminates it. If it's needed in the
future, it can be revived from the history. In the mean time, this removes
clutter and the only use of the GEMS_ROOT scons variable.
Yi Xiang [Wed, 9 Mar 2011 05:43:11 +0000 (21:43 -0800)]
Alpha: Fix the datatypes of some values read from the simulated kernel.
Gabe Black [Fri, 4 Mar 2011 08:11:02 +0000 (00:11 -0800)]
SCons: Fix the polarity on the --ignore-style check.
Gabe Black [Fri, 4 Mar 2011 07:55:21 +0000 (23:55 -0800)]
SCons: Clean up some inconsistent capitalization in scons options.
Gabe Black [Fri, 4 Mar 2011 07:54:31 +0000 (23:54 -0800)]
SCons: Turn some scons variables into command line options.
Gabe Black [Fri, 4 Mar 2011 07:01:38 +0000 (23:01 -0800)]
Mips: MIPS_FS doesn't build currently, so delete it to avoid confusion.
MIPS_FS doesn't build and presumably doesn't work right now. Users might see
the MIP_FS file in build_opts and expect it to work. To avoid confusion, this
change deletes that file.
Gabe Black [Thu, 3 Mar 2011 06:53:11 +0000 (22:53 -0800)]
Statetrace: Stub out the missing i386 version of sendState.
Gabe Black [Thu, 3 Mar 2011 06:53:11 +0000 (22:53 -0800)]
Statetrace: Rename i386 to i686.
--HG--
rename : util/statetrace/arch/i386/tracechild.cc => util/statetrace/arch/i686/tracechild.cc
rename : util/statetrace/arch/i386/tracechild.hh => util/statetrace/arch/i686/tracechild.hh
Gabe Black [Thu, 3 Mar 2011 06:53:11 +0000 (22:53 -0800)]
Statetrace: Fix the i686 detection macro.
Gabe Black [Thu, 3 Mar 2011 06:53:11 +0000 (22:53 -0800)]
Statetrace: Use sys/user.h instead of linux/user.h.
Gabe Black [Thu, 3 Mar 2011 06:53:11 +0000 (22:53 -0800)]
Statetrace: Tweak the help for the -nt option.
Gabe Black [Thu, 3 Mar 2011 06:53:11 +0000 (22:53 -0800)]
Statetrace: Accomodate cross compiling statetrace with scons.
--HG--
rename : util/statetrace/arch/tracechild_amd64.cc => util/statetrace/arch/amd64/tracechild.cc
rename : util/statetrace/arch/tracechild_amd64.hh => util/statetrace/arch/amd64/tracechild.hh
rename : util/statetrace/arch/tracechild_arm.cc => util/statetrace/arch/arm/tracechild.cc
rename : util/statetrace/arch/tracechild_arm.hh => util/statetrace/arch/arm/tracechild.hh
rename : util/statetrace/arch/tracechild_i386.cc => util/statetrace/arch/i386/tracechild.cc
rename : util/statetrace/arch/tracechild_i386.hh => util/statetrace/arch/i386/tracechild.hh
rename : util/statetrace/arch/tracechild_sparc.cc => util/statetrace/arch/sparc/tracechild.cc
rename : util/statetrace/arch/tracechild_sparc.hh => util/statetrace/arch/sparc/tracechild.hh
rename : util/statetrace/tracechild_arch.cc => util/statetrace/base/arch_check.h
rename : util/statetrace/regstate.hh => util/statetrace/base/regstate.hh
rename : util/statetrace/statetrace.cc => util/statetrace/base/statetrace.cc
rename : util/statetrace/tracechild.cc => util/statetrace/base/tracechild.cc
rename : util/statetrace/tracechild.hh => util/statetrace/base/tracechild.hh
Gabe Black [Thu, 3 Mar 2011 06:53:11 +0000 (22:53 -0800)]
Statetrace: Convert the build to scons.
Gabe Black [Thu, 3 Mar 2011 06:53:11 +0000 (22:53 -0800)]
Statetrace: Allow the user to override CXX.
Gabe Black [Thu, 3 Mar 2011 06:53:10 +0000 (22:53 -0800)]
Statetrace: Get rid of explicit register name handling.
Gabe Black [Thu, 3 Mar 2011 06:53:10 +0000 (22:53 -0800)]
Statetrace: Kill the printer functionality in statetrace.
Gabe Black [Thu, 3 Mar 2011 06:53:10 +0000 (22:53 -0800)]
Statetrace: Clean up style.
Gabe Black [Wed, 2 Mar 2011 08:41:44 +0000 (00:41 -0800)]
X86: Use the npc as the pc when doing a nativetrace, not what M5 considers the pc.
Gabe Black [Wed, 2 Mar 2011 08:41:38 +0000 (00:41 -0800)]
X86: Decode the mysterious and elusive ffreep x87 instruction.
The internet says this instruction was created by accident when an Intel CPU
failed to decode x87 instructions properly. It's been documented on a few rare
occasions and has generally worked to ensure backwards compatability. One
source claims that the gcc toolchain is basically the only thing that emits
it, and that emulators/binary translators like qemu and bochs implement it.
We won't actually implement it here since we're hardly implementing any other
x87 instructions either. If we were to implement it, it would behave the same
as ffree but then also pop the register stack.
http://www.pagetable.com/?p=16
Gabe Black [Wed, 2 Mar 2011 07:18:47 +0000 (23:18 -0800)]
Spelling: Fix the a spelling error by changing mmaped to mmapped.
There may not be a formally correct spelling for the past tense of mmap, but
mmapped is the spelling Google doesn't try to autocorrect. This makes sense
because it mirrors the past tense of map->mapped and not the past tense of
cape->caped.
--HG--
rename : src/arch/alpha/mmaped_ipr.hh => src/arch/alpha/mmapped_ipr.hh
rename : src/arch/arm/mmaped_ipr.hh => src/arch/arm/mmapped_ipr.hh
rename : src/arch/mips/mmaped_ipr.hh => src/arch/mips/mmapped_ipr.hh
rename : src/arch/power/mmaped_ipr.hh => src/arch/power/mmapped_ipr.hh
rename : src/arch/sparc/mmaped_ipr.hh => src/arch/sparc/mmapped_ipr.hh
rename : src/arch/x86/mmaped_ipr.hh => src/arch/x86/mmapped_ipr.hh
Gabe Black [Wed, 2 Mar 2011 07:18:00 +0000 (23:18 -0800)]
X86: Update stats for the x86 o3 hello world regression.
Gabe Black [Wed, 2 Mar 2011 06:42:59 +0000 (22:42 -0800)]
X86: Mark IO reads and writes as non-speculative.
Gabe Black [Wed, 2 Mar 2011 06:42:18 +0000 (22:42 -0800)]
X86: Mark prefetches as such in their instruction and request flags.
Nilay Vaish [Tue, 1 Mar 2011 21:26:11 +0000 (15:26 -0600)]
Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBuffer
At a couple of places in PerfectSwitch.cc and MessageBuffer.cc, DPRINTF()
has not been provided with correct number of arguments. The patch fixes these
bugs.
Gabe Black [Tue, 1 Mar 2011 11:00:42 +0000 (03:00 -0800)]
SCons: Separately label the global non-sticky options.
The global sticky options were being printed with a heading, and then the
global nonsticky options were being printed immediately after them without a
heading. Because the two lists ran together and the first had its own heading,
it looked like -all- those options where sticky even though some of them
aren't. This change adds a label to the second list so it's clear they're
different.
Gabe Black [Tue, 1 Mar 2011 10:59:09 +0000 (02:59 -0800)]
Ruby: Mention that Ruby's bound checking option only applies to Ruby.
Gabe Black [Mon, 28 Feb 2011 00:25:06 +0000 (16:25 -0800)]
X86: If PCI config space is disabled, pass through to regular IO addresses.
Gabe Black [Mon, 28 Feb 2011 00:24:54 +0000 (16:24 -0800)]
X86: Update X86_FS stats.
Gabe Black [Mon, 28 Feb 2011 00:24:10 +0000 (16:24 -0800)]
X86: Use regular read requests in the walker instead of read exclusive.
Korey Sewell [Sun, 27 Feb 2011 19:17:26 +0000 (14:17 -0500)]
inorder: bzip2 regression update
Nathan Binkert [Sun, 27 Feb 2011 05:43:11 +0000 (21:43 -0800)]
getopt: Remove GPL code.
This code is unused and should never have been committed
Nilay Vaish [Fri, 25 Feb 2011 23:55:20 +0000 (17:55 -0600)]
Ruby: Remove store buffer
This patch removes the store buffer from Ruby. It is not in use currently.
Since libruby is being and store buffer makes calls to libruby, it is not
possible to maintain it until substantial changes are made.
Nilay Vaish [Fri, 25 Feb 2011 23:54:56 +0000 (17:54 -0600)]
Ruby: Remove libruby
This patch removes libruby_internal.hh, libruby.hh and libruby.cc. It moves
the contents to libruby.hh to RubyRequest.hh and RubyRequest.cc files.
Nilay Vaish [Fri, 25 Feb 2011 23:51:56 +0000 (17:51 -0600)]
Ruby: Make Address.hh independent of RubySystem
This patch changes Address.hh so that it is not dependent on RubySystem.
This dependence seems unecessary. All those functions that depend on
RubySystem have been moved to Address.cc file.
Nilay Vaish [Fri, 25 Feb 2011 23:51:02 +0000 (17:51 -0600)]
Ruby: Make DataBlock.hh independent of RubySystem
This patch changes DataBlock.hh so that it is not dependent on RubySystem.
This dependence seems unecessary. All those functions that depende on
RubySystem have been moved to DataBlock.cc file.
Timothy M. Jones [Fri, 25 Feb 2011 13:50:29 +0000 (13:50 +0000)]
O3CPU: Fix iqCount and lsqCount SMT fetch policies.
Fixes two of the SMT fetch policies in O3CPU that were returning the count
of instructions in the IQ or LSQ rather than the thread ID to fetch from.
Gabe Black [Thu, 24 Feb 2011 10:14:45 +0000 (02:14 -0800)]
Configs: Explicitly import env in Benchmarks.py
env was being implicitly imported into Benchmarks.py through SysPaths.py.
This change brings it in explicitly in the file where it's used.
Brad Beckmann [Thu, 24 Feb 2011 00:41:59 +0000 (16:41 -0800)]
regress: MOESI_hammer memtest updates
Brad Beckmann [Thu, 24 Feb 2011 00:41:59 +0000 (16:41 -0800)]
ruby: automate permission setting
This patch integrates permissions with cache and memory states, and then
automates the setting of permissions within the generated code. No longer
does one need to manually set the permissions within the setState funciton.
This patch will faciliate easier functional access support by always correctly
setting permissions for both cache and memory states.
--HG--
rename : src/mem/slicc/ast/EnumDeclAST.py => src/mem/slicc/ast/StateDeclAST.py
rename : src/mem/slicc/ast/TypeFieldEnumAST.py => src/mem/slicc/ast/TypeFieldStateAST.py
Brad Beckmann [Thu, 24 Feb 2011 00:41:58 +0000 (16:41 -0800)]
MOESI_hammer: cache probe address clean up
Brad Beckmann [Thu, 24 Feb 2011 00:41:58 +0000 (16:41 -0800)]
ruby: cleaned up access permission enum
Brad Beckmann [Thu, 24 Feb 2011 00:41:26 +0000 (16:41 -0800)]
ruby: removed unsupported protocol files
Korey Sewell [Wed, 23 Feb 2011 21:35:25 +0000 (16:35 -0500)]
inorder: add 00.gzip and 60.bzip2 regression tests
Korey Sewell [Wed, 23 Feb 2011 21:35:18 +0000 (16:35 -0500)]
inorder: InstSeqNum bug
Because int and not InstSeqNum was used in a couple of places, you can
overflow the int type and thus get wierd bugs when the sequence number
is negative (or some wierd value)
Korey Sewell [Wed, 23 Feb 2011 21:35:04 +0000 (16:35 -0500)]
inorder: dyn inst initialization
remove constructors that werent being used (it just gets confusing)
use initialization list for all the variables instead of relying on initVars()
function
Korey Sewell [Wed, 23 Feb 2011 21:30:45 +0000 (16:30 -0500)]
inorder: cache packet handling
-use a pointer to CacheReqPacket instead of PacketPtr so correct destructors
get called on packet deletion
- make sure to delete the packet if the cache blocks the sendTiming request
or for some reason we dont use the packet
- dont overwrite memory requests since in the worst case an instruction will
be replaying a request so no need to keep allocating a new request
- we dont use retryPkt so delete it
- fetch code was split out already, so just assert that this is a memory
reference inst. and that the staticInst is available
Ali Saidi [Wed, 23 Feb 2011 21:10:50 +0000 (15:10 -0600)]
ARM: Update regression tests for preceeding changes.
Ali Saidi [Wed, 23 Feb 2011 21:10:50 +0000 (15:10 -0600)]
Mem: Print out memory when access > 8 bytes
Ali Saidi [Wed, 23 Feb 2011 21:10:50 +0000 (15:10 -0600)]
ARM: Set ITSTATE correctly after FlushPipe
Ali Saidi [Wed, 23 Feb 2011 21:10:50 +0000 (15:10 -0600)]
ARM: This panic can be hit during misspeculation so it can't exist.
Ali Saidi [Wed, 23 Feb 2011 21:10:50 +0000 (15:10 -0600)]
ARM: Bad interworking warn way to noisy when running real code w/misspeculation.
Ali Saidi [Wed, 23 Feb 2011 21:10:50 +0000 (15:10 -0600)]
O3: When a prefetch causes a fault, don't record it in the inst
Giacomo Gabrielli [Wed, 23 Feb 2011 21:10:50 +0000 (15:10 -0600)]
ARM: NEON instruction templates modified to set the predicate flag to false when needed.
Ali Saidi [Wed, 23 Feb 2011 21:10:49 +0000 (15:10 -0600)]
O3: If there is an outstanding table walk don't let the inst queue sleep.
If there is an outstanding table walk and no other activity in the CPU
it can go to sleep and never wake up. This change makes the instruction
queue always active if the CPU is waiting for a store to translate.
If Gabe changes the way this code works then the below should be removed
as indicated by the todo.
Ali Saidi [Wed, 23 Feb 2011 21:10:49 +0000 (15:10 -0600)]
ARM: Squash state on FPSCR stride or len write.
Matt Horsnell [Wed, 23 Feb 2011 21:10:49 +0000 (15:10 -0600)]
ARM: Mark store conditionals as such.
Ali Saidi [Wed, 23 Feb 2011 21:10:49 +0000 (15:10 -0600)]
ARM: Do something for ISB, DSB, DMB
Ali Saidi [Wed, 23 Feb 2011 21:10:49 +0000 (15:10 -0600)]
ARM: Fix bug that let two table walks occur in parallel.
Ali Saidi [Wed, 23 Feb 2011 21:10:49 +0000 (15:10 -0600)]
Includes: Don't include isa_traits.hh and use the TheISA namespace unless really needed.
Ali Saidi [Wed, 23 Feb 2011 21:10:49 +0000 (15:10 -0600)]
ARM: Make Noop actually decode to a noop and set it's instflags.
Ali Saidi [Wed, 23 Feb 2011 21:10:49 +0000 (15:10 -0600)]
O3: Fix bug when a squash occurs right before TLB miss returns.
In this case we need to throw away the TLB miss, not assume it was the
one we were waiting for.
Ali Saidi [Wed, 23 Feb 2011 21:10:48 +0000 (15:10 -0600)]
ARM: Delete OABI syscall handling.
We only support EABI binaries, so there is no reason to support OABI syscalls.
The loader detects OABI calls and fatal() so there is no reason to even check
here.
Ali Saidi [Wed, 23 Feb 2011 21:10:48 +0000 (15:10 -0600)]
CLCD: Fix some serialization bugs with the clcd controller.
Ali Saidi [Wed, 23 Feb 2011 21:10:48 +0000 (15:10 -0600)]
ARM: Clarifies creation of Linux and baremetal ARM systems.
makeArmSystem creates both bare-metal and Linux systems more cleanly.
machine_type was never optional though listed as an optional argument; a system
such as "RealView_PBX" must now be explicitly specified. Now that it is a
required argument, the placement of the arguments has changed slightly
requiring some changes to calls that create ARM systems.
Ali Saidi [Wed, 23 Feb 2011 21:10:48 +0000 (15:10 -0600)]
ARM: Add support for read of 100MHz clock in system controller.
Ali Saidi [Wed, 23 Feb 2011 21:10:48 +0000 (15:10 -0600)]
ARM: Reset simulation statistics when pref counters are reset.
The ARM performance counters are not currently supported by the model.
This patch interprets a 'reset performance counters' command to mean 'reset
the simulator statistics' instead.
Ali Saidi [Wed, 23 Feb 2011 21:10:48 +0000 (15:10 -0600)]
ARM: Adds dummy support for a L2 latency miscreg.
Korey Sewell [Wed, 23 Feb 2011 19:26:55 +0000 (14:26 -0500)]
configs: cache: add cache line size option
Korey Sewell [Wed, 23 Feb 2011 06:01:46 +0000 (01:01 -0500)]
configs: set default cache params
It's confusing (especially to new users), when you are setting some standard
parameters (as defined in Options.py) and they aren't reflected in the simulations
so we might as well link the settings in CacheConfig.py to those in Options.py
Korey Sewell [Wed, 23 Feb 2011 05:58:42 +0000 (00:58 -0500)]
ruby: extend dprintfs for RubyGenerated TraceFlag
"executing" isnt a very descriptive debug message and in going through the
output you get multiple messages that say "executing" but nothing to help
you parse through the code/execution.
So instead, at least print out the name of the action that is taking
place in these functions.
Korey Sewell [Wed, 23 Feb 2011 05:58:40 +0000 (00:58 -0500)]
ruby: cleaning up RubyQueue and RubyNetwork dprintfs
Overall, continue to progress Ruby debug messages to more of the normal M5
debug message style
- add a name() to the Ruby Throttle & PerfectSwitch objects so that the debug output
isn't littered w/"global:" everywhere.
- clean up messages that print over multiple lines when possible
- clean up duplicate prints in the message buffer