Francisco Jerez [Mon, 2 May 2016 23:10:28 +0000 (16:10 -0700)]
i965/fs: Introduce helper to extract a field from each channel of a register.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Connor Abbott [Wed, 29 Jul 2015 16:11:03 +0000 (09:11 -0700)]
i965/fs: always pass the bitsize to brw_type_for_nir_type()
v2 (Sam):
- Add bitsize to brw_type_for_nir_type() in optimize_extract_to_float()
v3 (Sam):
- Fix line width (Topi).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Connor Abbott [Mon, 3 Aug 2015 22:00:51 +0000 (15:00 -0700)]
i965/fs: add support for printing double immediates
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Connor Abbott [Mon, 3 Aug 2015 21:53:05 +0000 (14:53 -0700)]
i965/fs: don't propagate 64-bit immediates
They can only be used with 1-src instructions, which practically (since
we should've constant-propagated away all 1-src instructions with 64-bit
immediates in NIR) means that they must be kept in separate MOV's and
can't be propagated.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Connor Abbott [Wed, 29 Jul 2015 21:16:51 +0000 (14:16 -0700)]
i965/fs: use the NIR bit size when creating registers
v2 (Iago):
- Squashed bits from 'support double precission constant operands for
the implementation of 64-bit emit_load_const'.
- Do not use BRW_REGISTER_TYPE_D for all 32-bit registers since that breaks
asserts and functionality for some piglit tests. Just keep 32-bit types
untouched and add 64-bit support.
- Use DF instead of Q for 64-bit registers. Otherwise the code we generate
will use Q sometimes and DF others and we hit unwanted DF/Q conversions,
so always use DF.
v3 (Sam):
- Mark 'reg_type' occurrences as const (Topi).
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Tapani Palli <tapani.palli@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Connor Abbott [Mon, 2 Nov 2015 05:02:54 +0000 (00:02 -0500)]
i965: fixup uniform setup for doubles
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Thu, 7 Jan 2016 13:11:28 +0000 (14:11 +0100)]
i965: two-argument instructions can only use 32-bit immediates
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Wed, 18 Nov 2015 11:11:58 +0000 (12:11 +0100)]
i965: fix brw_abs_immediate() for doubles
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Wed, 18 Nov 2015 11:09:30 +0000 (12:09 +0100)]
i965: fix brw_saturate_immediate() for doubles
v2 (Sam):
- Mark 'size' as const (Topi).
- Add comment to explain that we do copies 64-bits regardless of the
type (Topi)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Connor Abbott [Wed, 18 Nov 2015 11:38:31 +0000 (12:38 +0100)]
i965: fix is_zero(), is_one() and is_negative_one() for doubles
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Connor Abbott [Wed, 18 Nov 2015 11:38:03 +0000 (12:38 +0100)]
i965: fix brw_negate_immediate() for doubles
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Connor Abbott [Mon, 3 Aug 2015 21:47:36 +0000 (14:47 -0700)]
i965/eu: add support for DF immediates
v2 (Sam):
- Remove 'however' from the comment (Topi)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Connor Abbott [Mon, 3 Aug 2015 21:47:12 +0000 (14:47 -0700)]
i965: add support for disassembling DF immediates
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Connor Abbott [Mon, 3 Aug 2015 21:40:37 +0000 (14:40 -0700)]
i965: add support for getting/setting DF immediates
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Connor Abbott [Thu, 12 Nov 2015 11:40:38 +0000 (12:40 +0100)]
i965: add brw_imm_df
v2 (Iago)
- Fixup accessibility in backend_reg
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Topi Pohjolainen [Mon, 20 Oct 2014 08:46:37 +0000 (11:46 +0300)]
i965/eu: Allow 3-src float ops with doubles
v2:
- set 3src_src_type for BRW_REGISTER_TYPE_DF (Connor)
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Connor Abbott [Wed, 29 Jul 2015 20:53:36 +0000 (13:53 -0700)]
i965/disasm: fix disasm of 3-src doubles
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Topi Pohjolainen [Tue, 16 Sep 2014 09:02:22 +0000 (12:02 +0300)]
i965: Tell backend register about double precision type
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Tapani P\344lli <tapani.palli@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Topi Pohjolainen [Wed, 3 Sep 2014 17:10:30 +0000 (20:10 +0300)]
i965: Determine size of double precision float register
This is used to determine how many registers an instruction reads and
writes as well as for offseting register region into a desired component.
v2 (Connor): rebase on master
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Tapani P\344lli <tapani.palli@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Topi Pohjolainen [Wed, 15 Oct 2014 14:41:02 +0000 (17:41 +0300)]
i965: Lower DFRACEXP/DLDEXP
v2 (Connor): rebase on master which moved this to brw_link.cpp
v3 (Sam):
- Only enable DFREXP_DLDEXP_TO_ARITH in process_glsl_ir(). This is
used for doubles. Single floating point op is lowered by NIR.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Connor Abbott [Fri, 7 Aug 2015 15:45:49 +0000 (08:45 -0700)]
i965: use pack/unpackDouble lowering
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Connor Abbott [Mon, 3 Aug 2015 22:02:05 +0000 (15:02 -0700)]
i965: use double lowering pass
v2: also lower trunc, ceil, floor, fract and roundEven (Iago)
v3: also lower mod for doubles (Sam)
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Samuel Iglesias Gonsálvez [Tue, 19 Jan 2016 14:22:18 +0000 (15:22 +0100)]
freedreno/ir3: lower lrp when operating with double operands
Lower lrp when operating with double operands because float version of
lrp is also lowered.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Samuel Iglesias Gonsálvez [Tue, 19 Jan 2016 07:19:20 +0000 (08:19 +0100)]
i965: enable lrp lowering for doubles
Broadwell and previous generations does not support lrp instruction
operating with doubles.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Dave Airlie [Tue, 10 May 2016 04:40:54 +0000 (14:40 +1000)]
st/glsl_to_tgsi: brown paper bag for the input offsets fix.
Oops, thanks compiler.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 10 May 2016 01:56:31 +0000 (11:56 +1000)]
glsl: check geometry output vertices limits.
This fixes:
GL45-CTS.geometry_shader.limits.max_output_vertices
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 10 May 2016 01:06:47 +0000 (11:06 +1000)]
mesa/vbo: fix check for zero aliases with 2/10/10/10
This fixes:
GL33-CTS.gtf33.GL3Tests.vertex_type_2_10_10_10_rev.vertex_type_2_10_10_10_rev_attrib
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
Eduardo Lima Mitev [Thu, 5 May 2016 11:52:38 +0000 (13:52 +0200)]
nir/print: Print memory qualifiers in a variable declaration
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eduardo Lima Mitev [Thu, 5 May 2016 11:52:37 +0000 (13:52 +0200)]
glsl: Apply memory qualifiers to vars inside named block interfaces
This is missing and memory qualifiers are currently being ignored for SSBOs.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Dave Airlie [Tue, 10 May 2016 01:41:02 +0000 (11:41 +1000)]
st/glsl_to_tgsi: handle offsets from inputs
This fixes:
GL45-CTS.gpu_shader5.texture_gather_offset_color_repeat
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Rob Clark [Mon, 9 May 2016 23:27:59 +0000 (19:27 -0400)]
scripts: bump git_reviewer.pl --git-min-percent default
Bump up default percentage of commits required to be auto-picked for CC.
Seems from a bit of trial-and-error to come up with a more reasonable
list of CC's this way.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Kenneth Graunke [Mon, 9 May 2016 04:49:34 +0000 (21:49 -0700)]
Revert "Revert "i965: Switch to scalar TCS by default.""
This reverts commit
bd326c229c528a214c9fda705e7a961cfa49ac9e.
Now that we've fixed the GPU hangs, let's turn it back on.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Kenneth Graunke [Mon, 9 May 2016 04:15:04 +0000 (21:15 -0700)]
i965: Actually assign binding table offsets for the TCS.
As far as I can tell, this was just entirely missing...honestly, I'm
not sure how anything worked at all.
Caught by noticing GPU hangs in image load store tests with scalar TCS,
but probably has broader implications.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Kenneth Graunke [Sun, 8 May 2016 00:30:02 +0000 (17:30 -0700)]
i965: Clamp "Maximum VP Index" to 1 when gl_ViewportIndex isn't written.
fs_visitor::emit_urb_writes skips writing the VUE header for shaders
that don't write gl_PointSize, gl_Layer, or gl_ViewportIndex. This
leaves their values uninitialized. Kristian's nearby comment says:
"But often none of the special varyings that live there are written
and in that case we can skip writing to the vue header, provided the
corresponding state properly clamps the values further down the
pipeline."
However, we were clamping gl_ViewportIndex to [0, 15], so we would end
up using a random viewport. To fix this, detect when the shader doesn't
write gl_ViewportIndex, and clamp it to [0, 0].
The vec4 backend always writes zeros to the VUE header, so it doesn't
suffer from this problem. With vec4-style HWord writes, we can write
the header and position together in a single message. In the FS world,
we would need 4 extra MOVs of 0 and a longer message, or a separate
OWord write. It's likely cheaper to just clamp the value.
Fixes DiRT Showdown and Bioshock Infinite, which only rendered half of
the screen - the lower left of two triangles.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93054
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jordan Justen [Mon, 9 May 2016 21:46:25 +0000 (14:46 -0700)]
i965/hsw: Fix brw_store_data_imm*
For Gen6 through Haswell dword 1 is MBZ. In gen 8 it becomes part of
the 64-bit address.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Thu, 5 May 2016 06:44:25 +0000 (23:44 -0700)]
i965: Reimplement ARB_transform_feedback2 on Haswell and later.
My old implementation accumulated <start, end> pairs in a buffer,
and eventually processed that data on the CPU. This meant flushing
the batchbuffer and waiting for it to completely execute before we
could map it, resulting in really long stalls. We could also run out
of space in the buffer, and have to do this early.
Instead, we can use Haswell's MI_MATH command to do the (end - start)
subtraction, as well as the multiplication by 2 or 3 to convert from
the number of primitives written to the number of vertices written.
We still need to CS stall to read the counters, but otherwise everything
is completely pipelined - there's no CPU<->GPU synchronization required.
It also uses only 80 bytes in the buffer, no matter what.
Improves performance in Manhattan on Skylake GT3e at 800x600 by
6.1086% +/- 0.954166% (n=9). At 1920x1080, improves performance
by 2.82103% +/- 0.148596% (n=84).
v2: Fix number of primitives -> number of vertices calculation for
GL_TRIANGLES (I was multiplying by 4 instead of 3.) Caught by
Jordan Justen.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Thu, 5 May 2016 05:52:52 +0000 (22:52 -0700)]
i965: Add a brw_load_register_reg64 helper.
It appears that we can't do this in a single command (like we do for
MI_LOAD_REGISTER_IMM) - the Skylake simulator gets rather grumpy about
the command length if I try to combine them. No matter.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Thu, 5 May 2016 08:57:30 +0000 (01:57 -0700)]
i965: Only enable ARB_query_buffer_object for newer kernels on Haswell.
On Haswell, we need version 6 of the kernel command parser in order to
write the math registers. Our implementation of ARB_query_buffer_object
heavily relies on MI_MATH, so we should only advertise it when MI_MATH
is available. We also need MI_LOAD_REGISTER_REG, which requires version
7 of the command parser.
To make these checks easier, introduce a screen->has_mi_math_and_lrr
flag that will be set when both commands are supported.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Dave Airlie [Mon, 9 May 2016 06:13:45 +0000 (16:13 +1000)]
mesa/objectlabel: don't return info on genned but never bound textures.
This fixes some cases in the CTS KHR debug tests where it uses
glIsTexture to find an invalid ID and then call GetObjectLabel.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 9 May 2016 06:09:13 +0000 (16:09 +1000)]
mesa: don't use genned but unnamed xfb objects.
If we try to draw or query an XFB object that hasn't been bound,
we shouldn't return any information.
This fixes a couple if cases in:
GL33-CTS.transform_feedback.api_errors_test
The ObjectLabel test is inspired by another test.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Samuel Pitoiset [Sun, 8 May 2016 22:13:41 +0000 (00:13 +0200)]
nv50/ir: silence unsupported TGSI_PROPERTY_CS_FIXED_BLOCK_*
We don't need them for compute shaders.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Jordan Justen [Thu, 5 May 2016 14:43:02 +0000 (07:43 -0700)]
mesa/compute: Fix indirect dispatch buffer size check on 32-bit systems
2655265fcba9017e793026c76e490e04db088c8f, but for compute.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Mon, 9 May 2016 17:51:18 +0000 (13:51 -0400)]
freedreno/ir3: fix fallout from new block iterators
Since this is potentially modifying the block structure of the shader,
it needs the _safe() version of the iterator.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Nicolai Hähnle [Fri, 6 May 2016 16:52:17 +0000 (11:52 -0500)]
radeonsi: workaround for tesselation on SI
We request more than 32KB of LDS here, which SI doesn't have. Since LLVM
recently started checking the size of declared LDS allocations, all shaders
involved in tesselation fail to compile on SI.
Note that the entire calculation here seems wrong, given how we calculate
indices for generic attributes, so the number ends up wrong on CI+ as well.
A proper solution is clearly needed, but this patch should serve as a band-aid
for SI in the meantime.
Also note that the real size of the LDS allocation in hardware is independent
from what we tell LLVM, so this is really more of a "cosmetic" change.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95198
Cc: "11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 5 May 2016 00:05:14 +0000 (19:05 -0500)]
radeonsi: always allocate export memory for pixel shaders
Experiments with framebuffer-no-attachments type draw calls have shown that
NULL exports stall terribly unless we ensure that export memory is allocated
by the SPI.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 4 May 2016 18:53:45 +0000 (13:53 -0500)]
radeonsi: expose performance counters as 64 bit
This is useful for shader-related counters, since they tend to quickly
exceed 32 bits.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rob Clark [Mon, 9 May 2016 16:46:13 +0000 (12:46 -0400)]
nir/search: fix typo
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Tim Rowley [Mon, 28 Mar 2016 19:29:30 +0000 (14:29 -0500)]
gallium: enable intel jitevents profiling
LLVM when configured with "intel jitevents" enabled can inform
VTune about dynamic code, so individual shaders are attributed
profiling data and the resulting assembly can be examined.
Acked-by: Roland Scheidegger <sroland@vmware.com>
Bruce Cherniak [Mon, 9 May 2016 14:00:04 +0000 (09:00 -0500)]
swr: Add missing break in query switch statement.
Missed a switch break in query stat collection when refactoring queries.
Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
Rob Clark [Fri, 6 May 2016 17:21:08 +0000 (13:21 -0400)]
freedreno/ir3: allow for additional VS sysval inputs
There are a total of four possible currently, rather than 2. So we need
to be prepared for the input array to grow by 16 components. We could
get away with less if we could pack sysval inputs.. and the way this is
handled currently isn't really the nicest thing. But it's a tactical
fix for an issue hit in:
GL31-CTS.gtf30.GL3Tests.transform_feedback.transform_feedback_vertex_id
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Emil Velikov [Mon, 9 May 2016 13:28:20 +0000 (14:28 +0100)]
docs: add news item and link release notes for 11.1.4/11.2.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 9 May 2016 13:21:01 +0000 (14:21 +0100)]
docs: add sha256 checksums for 11.2.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 9 May 2016 12:54:59 +0000 (13:54 +0100)]
docs: add release notes for 11.2.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 9 May 2016 12:49:18 +0000 (13:49 +0100)]
docs: add sha256 checksums for 11.1.4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 9 May 2016 12:25:35 +0000 (13:25 +0100)]
docs: add release notes for 11.1.4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Jose Fonseca [Fri, 6 May 2016 13:03:05 +0000 (14:03 +0100)]
scons: Improve Python module dependency discovery.
Several NIR scripts were using `from ... import ...` syntax, which wasn't
supported.
Using Python standard libary's modulefinder solves the problem with less
effort and hacks.
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Sun, 24 Apr 2016 11:23:52 +0000 (13:23 +0200)]
r300g: add support for PIPE_FORMAT_x8R8G8B8_*
And set endian swap for packed formats the way it should be done
in theory.
This allows big endian to work again, but it can still be buggy.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71789
Cc: 11.1 11.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Daniel Stone [Mon, 2 May 2016 14:34:40 +0000 (15:34 +0100)]
Revert "i965: Always use Y-tiled buffers on SKL+"
This commit broke Weston, Mutter, and xf86-video-modesetting, on KMS.
In order to use Y-tiled buffers, the kernel requires the tiling mode to
be explicitly named through the I915_FORMAT_MOD_Y_TILED AddFB2 modifier;
it disallows any attempt to infer the buffer's tiling mode.
As the GBM API does not have a way to extract modifiers for a buffer,
this commit broke all users of GBM on SKL+. Revert it for now, until we
get a way to extract modifier information from GBM, and also let GBM
users inform the implementation that it intends to use the modifiers.
This reverts commit
6a0d036483caf87d43ebe2edd1905873446c9589.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Hans de Goede <hdegoede@redhat.com>
Dave Airlie [Fri, 6 May 2016 00:21:14 +0000 (10:21 +1000)]
mesa/shader_query: add missing subroutines cases
ARRAY_SIZE and LOCATION should accept the SUBROUTINE_UNIFORM types.
Fixes:
GL43-CTS.program_interface_query.subroutines-vertex
GL43-CTS.program_interface_query.subroutines-tess-control
GL43-CTS.program_interface_query.subroutines-tess-eval
GL43-CTS.program_interface_query.subroutines-geometry
GL43-CTS.program_interface_query.subroutines-fragment
GL43-CTS.program_interface_query.subroutines-compute
Reviewed-by: Antia Puentes <apuentes@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Sun, 13 Mar 2016 08:08:56 +0000 (00:08 -0800)]
spirv: Fix structure splitting with per-vertex interface arrays.
We want to use interface_type, not vtn_var->type. They're normally
equivalent, but for geometry/tessellation per-vertex interface arrays,
we need to unwrap a level.
Otherwise, we tried to iterate a structure members but instead used
an array length. If the array length was longer than the number of
fields in the structure, we'd crash.
Fixes the CreatePipelineGeometryInputBlockPositive layer validation
test.
v2: Just use glsl_without_array() on the vtn_var type
(requested by Jason Ekstrand).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
Kenneth Graunke [Tue, 15 Mar 2016 05:01:29 +0000 (22:01 -0700)]
compiler: Add a C wrapper for glsl_type::without_array().
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
Nicolai Hähnle [Sat, 30 Apr 2016 04:41:59 +0000 (23:41 -0500)]
radeonsi: fix undefined behavior (memcpy arguments must be non-NULL)
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sat, 30 Apr 2016 03:29:22 +0000 (22:29 -0500)]
radeonsi: fix some reported undefined left-shifts
One of these is an unsigned bitfield, which I suspect is a false positive, but
gcc 5.3.1 complains about it with -fsanitize=undefined.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sat, 30 Apr 2016 03:15:48 +0000 (22:15 -0500)]
gallium/radeon: clean left-shift undefined behavior
Shifting into the sign bit of a signed int is undefined behavior.
Unfortunately, there are potentially many places where this happens using
the register macros.
This commit is the result of running
sed -ie "s/(((\(\w\+\)) & 0x\(\w\+\)) << \(\w\+\))/(((unsigned)(\1) \& 0x\2) << \3)/g"
on all header files in gallium/{r600,radeon,radeonsi}.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sat, 30 Apr 2016 02:56:25 +0000 (21:56 -0500)]
gallium: fix various undefined left shifts into sign bit
Funnily enough, some of these were turned into a compile-time error by gcc
with -fsanitize=undefined ("initializer is not a constant").
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sat, 30 Apr 2016 06:36:59 +0000 (01:36 -0500)]
compiler/glsl: do not downcast list sentinel
This crashes gcc's undefined behaviour sanitizer.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sat, 30 Apr 2016 04:38:09 +0000 (23:38 -0500)]
mesa/main: fix another undefined left shift
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sat, 30 Apr 2016 03:28:00 +0000 (22:28 -0500)]
mesa/main: define _NEW_xxx flags as unsigned shifts
Since 1 << 31 complains about undefined behaviour; the others are changed
only for consistency.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bas Nieuwenhuizen [Thu, 5 May 2016 20:25:01 +0000 (22:25 +0200)]
radeonsi: Compute correct LDS size for fragment shaders.
No sure where the 36 came from, but we clearly need at least
48 bytes per attribute per primitive.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Eric Anholt [Fri, 6 May 2016 01:04:14 +0000 (18:04 -0700)]
vc4: Add support for loading immediate values in QIR.
This will be used for resetting the uniform stream in the presence of
branching, but may also be useful as an optimization to reduce how many
uniforms we have to copy out per draw call (in exchange for increasing
icache pressure).
Eric Anholt [Tue, 3 May 2016 18:16:54 +0000 (11:16 -0700)]
vc4: Make vc4_qpu_validate() produce more verbose failures.
Seeing the expansion of a QPU_GET_FIELD in an assert isn't very
informative, and it's hard find what's going wrong without getting a dump
of the instruction that failed.
Eric Anholt [Mon, 2 May 2016 19:21:45 +0000 (12:21 -0700)]
vc4: Add a small QIR validate pass.
This has caught a couple of bugs during loop development so far, and I
should probably have written it long ago.
Eric Anholt [Fri, 6 May 2016 02:19:39 +0000 (19:19 -0700)]
vc4: Fix the src count on exp2/log2.
Found by the upcoming QIR validate pass.
Eric Anholt [Tue, 15 Mar 2016 21:15:51 +0000 (14:15 -0700)]
vc4: Reuse QPU disasm's cond flags in QIR.
In the process, this made me flatten out the "%s%s%s%s" fprintf arguments.
Eric Anholt [Mon, 2 May 2016 19:36:56 +0000 (12:36 -0700)]
vc4: When emitting an instruction to an existing temp, mark it non-SSA.
Prevents a bug in the later control-flow support series.
Eric Anholt [Mon, 2 May 2016 21:45:45 +0000 (14:45 -0700)]
vc4: Make sure that we don't overwrite the signal for PROG_END.
We should have already emitted a NOP due to the last instruction being a
TLB or VPM write. However, if you disable dead code elimination then you
might get dead code at the end, and that dead code might have the signal
bits set to something non-default, at which point you die in assertion
failure.
Samuel Pitoiset [Fri, 6 May 2016 14:25:45 +0000 (16:25 +0200)]
nvc0: unreference images when the context is destroyed
Like other resources, we need to unreference all images.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Jose Fonseca [Fri, 6 May 2016 11:00:08 +0000 (12:00 +0100)]
nir: Remove spurious return from void function.
Left over from
450c0613627d5a472fcf1122c15b66988abfb372.
Trivial. Built locally with clang and gcc.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95296
Marek Olšák [Tue, 3 May 2016 10:29:16 +0000 (12:29 +0200)]
radeonsi: set DECOMPRESS_Z_ON_FLUSH if nr_samples >= 4
Vulkan always sets this. It only affects in-place Z decompression.
This is recommended for performance, but what app uses MSAA depth
texturing?
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 30 Apr 2016 19:44:41 +0000 (21:44 +0200)]
r600g: use the hw MSAA resolving if formats are compatible
This allows resolving RGBA into RGBX.
This should improve HL2 Lost Coast performance.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Graunke [Fri, 6 May 2016 01:03:23 +0000 (18:03 -0700)]
Revert "i965: Switch to scalar TCS by default."
This reverts commit
b593737ed8349b280fa29242c35f565b59ab3025.
Apparently it causes GPU hangs on some image load store tests.
Let's turn it back off until we figure out why.
Leo Liu [Mon, 2 May 2016 17:18:52 +0000 (13:18 -0400)]
st/omx/enc: fix incorrect reference picture order for B frames
Stacking frames is for driver that's capable to do dual instances
encoding. Such feature is not enabled for B frames currently.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 3 May 2016 19:24:51 +0000 (12:24 -0700)]
i965/fs: Move handling of samples_identical into the switch statement
This is where we handle texop_texture_samples so it makes things more
consistent.
Jason Ekstrand [Tue, 3 May 2016 18:57:30 +0000 (11:57 -0700)]
i965/fs: Simplify texture destination fixups
There are a few different fixups that we have to do for texture
destinations that re-arrange channels, fix hardware vs. API mismatches, or
just shrink the result to fit in the NIR destination. These were all being
done in a somewhat haphazard manner. This commit replaces all of the
shuffling with a single LOAD_PAYLOAD operation at the end and makes it much
easier to insert fixups between the texture instruction itself and the
LOAD_PAYLOAD.
Shader-db results on Haswell:
total instructions in shared programs:
6227035 ->
6226669 (-0.01%)
instructions in affected programs: 19119 -> 18753 (-1.91%)
helped: 85
HURT: 0
total cycles in shared programs:
56491626 ->
56476126 (-0.03%)
cycles in affected programs: 672420 -> 656920 (-2.31%)
helped: 92
HURT: 42
Jason Ekstrand [Tue, 3 May 2016 18:46:31 +0000 (11:46 -0700)]
i965/fs: stop inclinding glsl/ir.h in brw_fs.h
We are no longer using anything from GLSL IR in the FS backend.
Jason Ekstrand [Tue, 3 May 2016 17:41:38 +0000 (10:41 -0700)]
i965/fs: Merge nir_emit_texture and emit_texture
The fs_visitor::emit_texture helper originated when we still had both NIR
and IR visitors for the FS backend. Since the old visitor was removed,
emit_texture serves no real purpose beyond arbitrarily splitting
heavily-linked code across two functions.
Connor Abbott [Wed, 13 Apr 2016 21:11:53 +0000 (17:11 -0400)]
nir: remove now-unused nir_foreach_block*_call()
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Connor Abbott [Wed, 13 Apr 2016 03:59:06 +0000 (23:59 -0400)]
vc4: fixup for new nir_foreach_block()
Reviewed-by: Eric Anholt <eric@anholt.net>
Connor Abbott [Wed, 13 Apr 2016 03:42:42 +0000 (23:42 -0400)]
ir3: fixup for new nir_foreach_block()
Jason Ekstrand [Thu, 28 Apr 2016 17:34:52 +0000 (10:34 -0700)]
nir/lower_double_ops: fixup for new nir_foreach_block()
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jason Ekstrand [Wed, 13 Apr 2016 23:26:57 +0000 (16:26 -0700)]
nir/lower_double_pack: fixup for new nir_foreach_block()
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jason Ekstrand [Wed, 13 Apr 2016 23:26:39 +0000 (16:26 -0700)]
nir/gather_info: fixup for new foreach_block()
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Connor Abbott [Fri, 8 Apr 2016 21:20:53 +0000 (17:20 -0400)]
nir/lower_two_sided_color: fixup for new foreach_block()
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Connor Abbott [Fri, 8 Apr 2016 20:30:23 +0000 (16:30 -0400)]
nir/lower_tex: fixup for new foreach_block()
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Connor Abbott [Fri, 8 Apr 2016 20:22:13 +0000 (16:22 -0400)]
nir/lower_outputs_to_temporaries: fixup for new foreach_block()
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Fri, 22 Apr 2016 04:42:08 +0000 (21:42 -0700)]
i965: Switch to scalar TCS by default.
Normally, we expect SIMD8 shaders to be more instructions than SIMD4x2
shaders, as it takes four instructions to operate on a vec4, rather than
a single instruction. However, the benefit is that it can process 8
objects per shader thread instead of 2.
Surprisingly, the shader-db statistics show an improvement in both
instruction and cycle counts:
Synmark: -31.25% instructions, -29.27% cycles, 0 hurt.
Tessmark: -36.92% instructions, -37.81% cycles, 0 hurt.
Unigine Heaven: -3.42% instructions, -17.95% cycles, 0 hurt.
Shadow of Mordor:
+13.24% instructions (26 with fewer instructions, 45 with more),
-5.23% cycles (44 with fewer cycles, 27 with more cycles).
Presumably, this is because the SIMD8 URB messages are a much more
natural fit than the SIMD4x2 URB messages - there's a ton less header
setup.
I benchmarked Shadow of Mordor and Unigine Heaven on my Skylake GT3e,
and the performance seems to be the same or increase ever so slightly
(< 1 FPS difference). So I believe it's strictly superior.
There's also a lot more optimization potential we can do in scalar mode.
This will also help us finish fp64 support, as scalar support is going
to land much sooner than vec4-mode support.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Wed, 20 Apr 2016 09:38:57 +0000 (02:38 -0700)]
nir: Optimize out stores of undefs.
There are a couple of cycle count changes in shader-db, but it's
basically a wash.
However, with the Broadwell scalar TCS backend enabled, many
Shadow of Mordor shaders benefit from this patch. Because we don't
batch up output writes for TCS, vec4 outputs might not have all
components defined. Many output writes have a value of undef,
which is useless.
With scalar TCS, stats for tessellation shaders on Broadwell:
total instructions in shared programs:
1283000 ->
1280444 (-0.20%)
instructions in affected programs: 34302 -> 31746 (-7.45%)
helped: 71
HURT: 0
total cycles in shared programs:
10798768 ->
10780682 (-0.17%)
cycles in affected programs: 158004 -> 139918 (-11.45%)
helped: 71
HURT: 0
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Wed, 20 Apr 2016 08:42:25 +0000 (01:42 -0700)]
nir: Replace vecN(undef, undef, ...) with a single undef.
shader-db statistics on Broadwell:
total instructions in shared programs:
8963409 ->
8962455 (-0.01%)
instructions in affected programs: 60858 -> 59904 (-1.57%)
helped: 318
HURT: 0
total cycles in shared programs:
71408022 ->
71406276 (-0.00%)
cycles in affected programs: 398416 -> 396670 (-0.44%)
helped: 199
HURT: 51
GAINED: 1
The only shaders affected were in Dota 2 Reborn.
It also sets up for the next optimization.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Wed, 20 Apr 2016 08:15:53 +0000 (01:15 -0700)]
nir: Rename opt_undef_alu to opt_undef_csel; update comments.
This better reflects what it does. I plan to add other ALU
optimizations as well, so the old name would be confusing.
In preparation for that, also move the file comments about csels
above the opt_undef_csel function, and delete the ones about there
not being other optimizations.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Tue, 3 May 2016 20:14:31 +0000 (13:14 -0700)]
i965: Rework passthrough TCS checks.
According to Timothy, using program_string_id == 0 to identify the
passthrough TCS is going to be problematic for his shader cache work.
So, change it to strcmp() the name at visitor creation time.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>