Brian Ho [Fri, 19 Jun 2020 16:47:08 +0000 (12:47 -0400)]
turnip: Fill out VkPhysicalDeviceSubgroupProperties
This commit fills out VkPhysicalDeviceSubgroupProperties if present
in a VkPhysicalDeviceProperties2. The values here are simply pulled
from the blob.
Fixes some flakes in dEQP-VK.subgroups.* since dEQP was reading
uninitialized values of VkPhysicalDeviceSubgroupProperties.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5564>
Mike Blumenkrantz [Thu, 18 Jun 2020 15:54:21 +0000 (11:54 -0400)]
zink: use int assignment for vk int type
this breaks 32bit builds that use -Werror=int-conversion
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5545>
Rob Clark [Mon, 15 Jun 2020 21:12:58 +0000 (14:12 -0700)]
freedreno/ir3: move output_loc to variant
This moves the last bit of important state to be serialized from
ir3_shader to ir3_shader_variant.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
Rob Clark [Mon, 15 Jun 2020 19:14:04 +0000 (12:14 -0700)]
freedreno/ir3: move const_state back to variant
For shader-cache, we want to not have anything important in `ir3_shader`.
And to have shader variants with lower const size limits (to properly
handle cross-stage limits), we also want variants to be able to have
their own const_state.
But we still need binning pass shaders to align with their draw pass
counterpart so that the same const emit can be used for both passes.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
Rob Clark [Mon, 15 Jun 2020 18:43:36 +0000 (11:43 -0700)]
freedreno/ir3: un-embed const_state
Make it an rzalloc'd ptr instead of embedded struct, so it can serve as
the mem ctx for immediates. This gets rid of needing to explicitly free
the immediates, so one less thing to deal with when moving const_state.
(Also, after we move const_state to the shader variant, we won't need
one for binning pass variants)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
Rob Clark [Tue, 16 Jun 2020 21:09:34 +0000 (14:09 -0700)]
freedreno/ir3: move num_reserved_user_consts out of const_state
When we move const_state to the variant, this will need to stay in the
shader, as it applies to all variants (and we need to store it somewhere
before we have any variants)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
Rob Clark [Mon, 15 Jun 2020 18:15:52 +0000 (11:15 -0700)]
freedreno/ir3: convert over to ralloc
The `ir3_shader` is the root mem ctx, with `ir3_shader_variant` hanging
off that, and various variant specific allocations hanging off the
variant.
This lets us delete a bunch of cleanup code.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
Rob Clark [Mon, 15 Jun 2020 18:14:46 +0000 (11:14 -0700)]
freedreno/ir3: pass variant to ir3_create()
Prep to convert over to ralloc.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
Connor Abbott [Wed, 10 Jun 2020 09:11:27 +0000 (11:11 +0200)]
ir3: Split out variant-specific lowering and optimizations
It seems a lot of the lowerings being run the second time were
unnecessary. In addition, when const_state is moved to the variant,
then it will become impossible to know ahead of time whether a variant
needs additional optimizing, which means that ir3_key_lowers_nir() needs
to go away. The new approach should have the same effect, since it skips
running lowerings that are unnecessary and then skips the opt loop if no
optimizations made progress, but it will work better when we move
ir3_nir_analyze_ubo_ranges() to be after variant creation.
The one maybe controversial thing I did is to make
nir_opt_algebraic_late() always happen during variant lowering. I wanted
to avoid code duplication, and it seems to me that we should push the
_late variants as far back as possible so that later opt_algebraic runs
don't miss out on optimization opportunities.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
Rob Clark [Mon, 15 Jun 2020 16:37:13 +0000 (09:37 -0700)]
freedreno/ir3: constify shader key
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
Rob Clark [Sun, 14 Jun 2020 19:54:05 +0000 (12:54 -0700)]
freedreno/ir3: drop shader->num_ubos
The only difference between this and `const_state->num_ubos` was that
the latter is counting # of ubos loaded via `ldg` (based on UBO addrs
in push-consts). But turns out there isn't really any reason to care.
Instead just add an early return in the one code-path that cares about
the number of `ldg` UBOs.
This gets rid of one more thing we need to move from `ir3_shader` to
`ir3_shader_variant`.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
Rob Clark [Sun, 14 Jun 2020 19:44:17 +0000 (12:44 -0700)]
freedreno/ir3: move ubo_state into const_state
As with const_state, this will also need to move into the variant. To
simplify that, just move it into the const_state itself, since after all
it is related.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
Rob Clark [Sun, 14 Jun 2020 19:33:54 +0000 (12:33 -0700)]
freedreno/a6xx: defer userconst cmdstream size calculation
The `ubo_state` will also need to move to `ir3_shader_variant`. But we
can prepare for that and simplify things a bit if we calculate the
cmdstream on first emit, once we already have the appropriate variant.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
Rob Clark [Sun, 14 Jun 2020 18:36:05 +0000 (11:36 -0700)]
freedreno/ir3: add accessor for const_state
We are going to want to move this back to the variant, and come up with
a different strategy for binning/nonbinning to share the same constant
layout, in order to implement shader-cache support. (Since then we
can have a mix of dynamically compiled variants and cache hits, so there
is no good place to serialize the const-state.)
To reduce the churn as we re-arrange things, move direct access to the
const-state to a helper fxn. This patch is the boring churny part.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
Rob Clark [Wed, 17 Jun 2020 15:13:12 +0000 (08:13 -0700)]
freedreno/ir3: refactor out helper to compile shader from asm
Deduplicate a bit of hand-building of ir3_shader/_variant from
computerator and delay test. This also removes the need for
external things to depend on generated ir3_parser header.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
Pierre-Eric Pelloux-Prayer [Fri, 5 Jun 2020 09:20:55 +0000 (11:20 +0200)]
st/mesa: make texture views inherit compressed_data storage
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2775
Fixes: c3fafa127a0 ("st/mesa: generalize code for the compressed texture map/unmap fallback")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5492>
Pierre-Eric Pelloux-Prayer [Tue, 16 Jun 2020 12:46:08 +0000 (14:46 +0200)]
ac/llvm: load 1 byte at a time if unaligned on gfx10
If buffer or stride is unaligned we use the same trick as on gfx6:
load 1 byte at a time and recompose the output if needed.
This change fixes lots of deqp/glcts tests:
- dEQP-GLES2.functional.draw.random.1, 10, ...
- dEQP-GLES2.functional.vertex_arrays.multiple_attributes.stride.3_float2_0_float2_0_float2_17, ...
- dEQP-GLES2.functional.vertex_arrays.single_attribute.first.byte_first24_offset1_stride2_quads256, ...
- dEQP-GLES2.functional.vertex_arrays.single_attribute.strides.buffer_0_17_byte2_vec4_dynamic_draw_quads_1, ...
- dEQP-GLES31.functional.draw_indirect.random.14, ...
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5502>
Gert Wollny [Sat, 9 May 2020 09:15:04 +0000 (11:15 +0200)]
r600/sfn: Handle memory_barrier
I'm not sure whether this should actually be a barrier accross all
shader processing units, the TGSI code path seems to handle this
only by using GROUP_BARRIER, so let's do the same here.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
Gert Wollny [Sun, 10 May 2020 11:38:17 +0000 (13:38 +0200)]
r600/sfn: Take SSBO buffer ID offset into account
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
Gert Wollny [Sat, 9 May 2020 13:09:36 +0000 (15:09 +0200)]
r600/sfn: Add support for reading cube image array dim.
The cube array size can't be queried directly, the number of array
elements must be passed via a constant buffer.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
Gert Wollny [Sat, 9 May 2020 09:30:19 +0000 (11:30 +0200)]
r600/sfn: Add support for image_size
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
Gert Wollny [Wed, 6 May 2020 22:08:15 +0000 (00:08 +0200)]
r600/sfn: Add imageio support
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
Gert Wollny [Wed, 6 May 2020 22:11:33 +0000 (00:11 +0200)]
r600/sfn: lower image derefs
v2: Signal lowering image derefs by using the CAP
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
Samuel Pitoiset [Tue, 9 Jun 2020 06:10:56 +0000 (08:10 +0200)]
radv: require LLVM 11+ for GFX 10.3 if not using ACO
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5389>
Samuel Pitoiset [Mon, 8 Jun 2020 16:16:13 +0000 (18:16 +0200)]
radv: add support for Sienna Cichlid
Bits copied from RadeonSI. Totally untested.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5389>
Samuel Pitoiset [Mon, 8 Jun 2020 16:45:35 +0000 (18:45 +0200)]
aco: replace == GFX10 with >= GFX10 where it's needed
Assume the GFX10.3 ISA is similar to GFX10 which is likely (except
possible minor changes and new instructions for raytracing).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5389>
Samuel Pitoiset [Mon, 8 Jun 2020 16:38:57 +0000 (18:38 +0200)]
radv: replace == GFX10 with >= GFX10 where it's needed
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5389>
Matt Turner [Wed, 17 Jun 2020 00:10:38 +0000 (17:10 -0700)]
intel/tools: Add assembler tests for the cr0 register
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
Matt Turner [Wed, 17 Jun 2020 00:07:15 +0000 (17:07 -0700)]
intel/tools: Disallow control subregisters > 3
> 4 was probably a typo, since the documentation says that there are 4
subregisters (0-3).
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
Matt Turner [Tue, 16 Jun 2020 23:54:07 +0000 (16:54 -0700)]
intel/tools: Require explicit regions/types for special regs
The docs say that these registers should only be read with a certain
type, and I'm inclined to believe that the hardware behaves that way,
but it makes the assembler a little more confusing and also confuses the
user of the assembler that some operands don't take types or regions.
Just always requiring regions and types seems like the sensible thing.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
Matt Turner [Tue, 16 Jun 2020 23:53:05 +0000 (16:53 -0700)]
intel/tools: Drop srctype from ipreg
It's unused, and it would cause shift/reduce conflicts after the next
patch.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
Matt Turner [Tue, 16 Jun 2020 23:53:57 +0000 (16:53 -0700)]
intel/tools: Remove unnecessary reg number checking
a0 is the only address register, and cr0 is the only control register,
so there's no need to return the register number, espcially since the
lexer explicitly consumes "a0" and "cr0".
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
Jonathan Marek [Wed, 17 Jun 2020 20:05:07 +0000 (16:05 -0400)]
turnip: move enum translation functions to a common header
Instead of having these functions sprinkled around the driver (and ending
with a duplicated tu6_compare_func for example), move everything to a
common header (using the previously unused tu_util.h).
Also applied some simplifications: using a cast when the HW enum matches
the VK enum, and using a lookup table when it makes sense (which is IMO
nicer than the switch case way).
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5538>
Rhys Perry [Thu, 18 Jun 2020 12:52:28 +0000 (13:52 +0100)]
aco: use the same regclass as the definition for undef phi operands
Subdword phis can't have SGPR operands on GFX6-8.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5544>
Rhys Perry [Thu, 18 Jun 2020 12:30:50 +0000 (13:30 +0100)]
aco: fix edge check with sub-dword temporaries
Fixes RA failure for a parallel-rdp shader on pitcairn.
fossil-db (Navi):
Totals from 2 (0.00% of 128733) affected shaders:
CodeSize: 203656 -> 205724 (+1.02%)
Instrs: 32267 -> 32529 (+0.81%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5544>
Erik Faye-Lund [Wed, 17 Jun 2020 21:50:06 +0000 (23:50 +0200)]
mesa/main: fix inverted condition
I accidentally got one of the conditions wrong here. Sorry for the
mixup.
See ttps://gitlab.freedesktop.org/mesa/mesa/-/issues/3134 for details.
Fixes: b112e62ba48 ("mesa/main: do not allow MESA_ycbcr_texture enums on gles")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5532>
Karol Herbst [Mon, 15 Jun 2020 23:08:39 +0000 (01:08 +0200)]
nv50/ir/nir: remove image uniform hack
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5480>
Karol Herbst [Mon, 15 Jun 2020 16:30:39 +0000 (18:30 +0200)]
nv50/ir/nir: handle image atomic inc and dec
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5480>
Karol Herbst [Mon, 15 Jun 2020 12:36:18 +0000 (14:36 +0200)]
nv50/ir/nir: move away from image_deref intrinsics
v2: fix lod source of image operation correctly
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5480>
Karol Herbst [Mon, 15 Jun 2020 16:30:12 +0000 (18:30 +0200)]
nir/lower_images: handle dec and inc
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5480>
Karol Herbst [Mon, 15 Jun 2020 16:29:58 +0000 (18:29 +0200)]
nir/lower_images: fix for array of arrays
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5480>
Karol Herbst [Mon, 15 Jun 2020 13:14:58 +0000 (15:14 +0200)]
st/mesa: lower images when needed
The "st/pbo download FS" builtin shader uses image derefs, so even with
PIPE_CAP_NIR_IMAGES_AS_DEREF set to 0 drivers ended up with those.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5480>
Rhys Perry [Mon, 1 Jun 2020 15:19:56 +0000 (16:19 +0100)]
aco: shrink mad_info
From 24 bytes to 16 bytes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5281>
Rhys Perry [Mon, 1 Jun 2020 10:27:53 +0000 (11:27 +0100)]
aco: make ssa_info::label 64-bit
We'll probably need these extra bits in the future.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5281>
Rhys Perry [Mon, 1 Jun 2020 15:13:09 +0000 (16:13 +0100)]
aco: shrink ssa_info
Reorder members so that it's 16 bytes instead of 24.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5281>
Boyuan Zhang [Thu, 11 Jun 2020 23:22:51 +0000 (19:22 -0400)]
radeon/vcn: bump vcn3.0 encode major version to 1
And add quality params for this version
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5501>
Boyuan Zhang [Thu, 11 Jun 2020 23:17:03 +0000 (19:17 -0400)]
radeon/vcn/enc: Re-write PPS encoding for HEVC
Due to hardware change on VCN3
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5501>
Thong Thai [Thu, 11 Jun 2020 23:02:27 +0000 (19:02 -0400)]
radeon/vcn: add vcn 3.0 encode support
Signed-off-by: Thong Thai <thong.thai@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5501>
Leo Liu [Thu, 11 Jun 2020 23:27:57 +0000 (19:27 -0400)]
radeon/vcn/dec: add db_aligned_height to message buffer
This is required for Sienna
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5501>
Leo Liu [Thu, 11 Jun 2020 22:40:07 +0000 (18:40 -0400)]
radeon/vcn: add Sienna to use internal register offset
And re-group them explicitly
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5501>
Leo Liu [Thu, 11 Jun 2020 22:28:25 +0000 (18:28 -0400)]
radeon/vcn: reset the decode flags from message buffer
This flag was never used by VCN previously, and now
it's used for feature that is not applied to us.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5501>
Daniel Schürmann [Wed, 17 Jun 2020 11:41:09 +0000 (12:41 +0100)]
aco: fix WQM handling in nested loops
If on a nested loop
- the outer loop needs WQM but
- the inner loop doesn't need WQM and
- the break condition of the inner loop is computed in the outer loop
then it could happen that we transitioned to Exact before entering the inner loop
which could create an empty exec mask and lead to an infinite loop.
Fixes a GPU hang with RDR2
Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5518>
Danylo Piliaiev [Fri, 12 Jun 2020 13:04:44 +0000 (16:04 +0300)]
st/mesa: account for "loose", per-mipmap level textures in CopyImageSubData
We may have "loose", per-image gallium resources. The src_image->Level
may not match the gallium resource texture level. In such case it is
prescribed (in st_AllocTextureImageBuffer) to specify mipmap level
as zero.
Fixes: f04f13622f3e71bee057d60a6be9c53b92b56cc9
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5477>
Gurchetan Singh [Mon, 15 Jun 2020 17:52:57 +0000 (10:52 -0700)]
virgl: apply bgra dest swizzle and add Portal 2
Apply the destination swizzle on GLES games based on HL2 engine.
Also add Portal 2 since some people are experiencing issues with
that.
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5481>
Jonathan Marek [Wed, 17 Jun 2020 13:57:56 +0000 (09:57 -0400)]
turnip: set the API version
Some CTS tests don't run because of this.
Fixes: 91c757b7963f458 ("turnip: use the common code for generating extensions and dispatch tables")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5522>
Samuel Pitoiset [Sat, 13 Jun 2020 12:23:17 +0000 (14:23 +0200)]
radv: only requires LLVM 9 for GFX10 if not using ACO
In case someone links RADV with LLVM 8 and wants to use ACO.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5454>
Neil Armstrong [Fri, 24 Apr 2020 09:07:32 +0000 (11:07 +0200)]
Revert "CI: Disable Panfrost Mali-T820 jobs"
This reverts commit
46a32f0b6bf91279d001a4905babe4e50007696e.
The lab has recovered health, thus re-enable T820 Panfrost jobs.
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4727>
Neil Armstrong [Fri, 24 Apr 2020 09:07:31 +0000 (11:07 +0200)]
Revert "CI: Disable Lima jobs due to lab unhealthiness"
This reverts commit
adeef43d15092a6910dceb3605f5ee3151dd2c47.
The lab has recovered health, thus re-enable Lima jobs.
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4727>
Samuel Pitoiset [Thu, 11 Jun 2020 14:27:17 +0000 (16:27 +0200)]
radv: compute CB_SHADER_MASK from the fragment shader outputs
The fragment shader doesn't necessarily output the number of components
expected by the target format.
Fixes new dEQP-VK.draw.output_location.*.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5427>
Samuel Pitoiset [Thu, 11 Jun 2020 13:39:46 +0000 (15:39 +0200)]
radv: make sure to set CB_SHADER_MASK correctly for internal CB operations
It should be always set to 0xf.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5427>
Erik Faye-Lund [Thu, 18 Jun 2020 08:43:36 +0000 (10:43 +0200)]
docs/features: remove driver-list for forward-compatible context
This is something that's supported by the Gallium state-tracker, there's
nothing to be done per driver here.
Erik Faye-Lund [Thu, 18 Jun 2020 08:41:43 +0000 (10:41 +0200)]
docs/features: update ARB_texture_buffer_object line
This extension isn't just exposed in OpenGL 3.1 contexts any longer, and
Zink supports it. Let's mark it as such.
Erik Faye-Lund [Thu, 18 Jun 2020 08:40:27 +0000 (10:40 +0200)]
docs/features: mark GL3 as complete for zink
Samuel Pitoiset [Wed, 17 Jun 2020 14:35:05 +0000 (16:35 +0200)]
radv: lower discards to demote to workaround a RDR2 game bug
This fixes some sort of LOD issue.
Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5525>
Rob Clark [Wed, 17 Jun 2020 00:46:43 +0000 (17:46 -0700)]
glsl_to_nir: fix vote_any/vote_all
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5505>
Rob Clark [Wed, 17 Jun 2020 00:45:59 +0000 (17:45 -0700)]
glsl_to_nir: fix shader_clock
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5505>
Rob Clark [Tue, 16 Jun 2020 23:36:32 +0000 (16:36 -0700)]
glsl_to_nir: fix is_helper_invocation
Reported-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5505>
Rob Clark [Tue, 16 Jun 2020 18:23:26 +0000 (11:23 -0700)]
spirv: drop some dead code
This case is never hit, we don't have a nir intrinsic for this spirv
opcode. And when we do, I'm not sure if it would be vectorized or not.
So best just to drop this case.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5505>
Rob Clark [Tue, 16 Jun 2020 18:21:29 +0000 (11:21 -0700)]
spirv: atomic_counter_read_deref is not vectorized
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3141
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5505>
Jonathan Marek [Tue, 16 Jun 2020 14:45:58 +0000 (10:45 -0400)]
turnip: fix renderpass gmem configs when there are too many attachments
Since a value of at least "align" is used for nblocks, we might end up
with nblocks greater than the number of GMEM blocks remaining. Check for
this case and bail out, sysmem rendering will be used for such cases.
Fixes some of these tests:
dEQP-VK.pipeline.render_to_image.core.*.huge.*
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5499>
Jonathan Marek [Tue, 16 Jun 2020 13:11:02 +0000 (09:11 -0400)]
turnip: fix a sample shading case
Check pipeline's sampleShadingEnable to enable sample shading.
Also fix behavior of gl_Fragcoord with sample shading.
Fixes at least:
dEQP-VK.pipeline.multisample.min_sample_shading.min_0_5.samples_4.primitive_triangle
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5499>
Jonathan Marek [Wed, 17 Jun 2020 18:23:37 +0000 (14:23 -0400)]
turnip: fix a crash when rasterizerDiscardEnable is set
pMultisampleState needs to be ignored when rasterizerDiscardEnable, so the
current code can crash when trying to load msaa_info->pNext.
At the same time this simplifies tu_pipeline_shader_key_init a bit, by not
calling it for the compute shader case (which doesn't need to set anything
in the key struct).
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5499>
Eric Engestrom [Fri, 22 Nov 2019 14:21:05 +0000 (14:21 +0000)]
docs: remind release maintainers to sign the tarballs and publish their key
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2857>
Eric Engestrom [Fri, 22 Nov 2019 14:10:50 +0000 (14:10 +0000)]
docs: publish our release maintainers' keys
They should be published to various key servers as well, but this
provides the authoritative source for their list.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2140
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2857>
Rob Clark [Sun, 14 Jun 2020 16:53:11 +0000 (09:53 -0700)]
freedreno/ir3: update obsolete comment
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5458>
Rob Clark [Sat, 13 Jun 2020 17:43:00 +0000 (10:43 -0700)]
freedreno/computerator: MERGEDREGS update
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5458>
Rob Clark [Sat, 13 Jun 2020 16:35:40 +0000 (09:35 -0700)]
turnip: set .MERGEDREGS based on variant
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5458>
Rob Clark [Sat, 13 Jun 2020 16:31:11 +0000 (09:31 -0700)]
freedreno/a6xx: set .MERGEREGS based on variant
Also set HALFREGFOOTPRINT, since in the non-mergeregs case this will be
non-zero.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5458>
Rob Clark [Sat, 13 Jun 2020 03:48:36 +0000 (20:48 -0700)]
freedreno/ir3: make mergedregs a property of the variant
Rather than assuming a6xx+ means mergedregs. We can actually (mostly?)
do splitregs on a6xx as well. And GS/DS/HS currently require it, which
might be papering over a bug, or might be something to do with how
chaining shaders works. At any rate, we should at least be consistent,
and not have the compiler thinking we are doing mergedregs when we are
actually doing splitregs.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5458>
Rob Clark [Sat, 13 Jun 2020 17:49:47 +0000 (10:49 -0700)]
freedreno/ir3: re-work assembler API
Just pass thru the variant, since it has everything we need. And
will be needed in the next patch.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5458>
Rob Clark [Sat, 13 Jun 2020 16:23:57 +0000 (09:23 -0700)]
freedreno/ir3: pass variant to postsched
Prep for the next patch.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5458>
Rob Clark [Sat, 13 Jun 2020 03:56:48 +0000 (20:56 -0700)]
freedreno/ir3: decouple regset from gpu gen
Allow different regset's to coexist, so we can make mergedregs vs split
reg file a variant property.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5458>
Rob Clark [Sat, 13 Jun 2020 03:42:36 +0000 (20:42 -0700)]
freedreno/ir3: move mergedreg state out of reg
It is only needed one place, let's move it there.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5458>
Rob Clark [Sat, 13 Jun 2020 03:33:31 +0000 (20:33 -0700)]
freedreno/ir3: convert regmask_t to struct
Prep to make merged/split register file mode a property of the regmask,
rather than the ir3_register.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5458>
Jonathan Marek [Tue, 9 Jun 2020 22:48:34 +0000 (18:48 -0400)]
freedreno/fdl6: rework layout code a bit (reduce linear align to 64 bytes)
Reduce linear alignment, and rework the layout code a bit.
This rework has a side effect of also increasing the alignment on linear
levels of tiled (non-ubwc) cpp=1 and cpp=2 layouts. Since we should be
UBWC for those cases anyway, its not a big loss.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5013>
Jonathan Marek [Tue, 12 May 2020 16:34:37 +0000 (12:34 -0400)]
freedreno/a6xx: FETCHSIZE is PITCHALIGN
"FETCHSIZE" is actually a "minimum pitch" or "pitchalign" value that's
relevant for mipmaps. The 0 value means 64-bytes. Understanding this allows
some simplifications and will make it possible to use less alignment on
linear formats.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5013>
Eric Engestrom [Fri, 5 Jun 2020 08:55:41 +0000 (10:55 +0200)]
virgl: replace all dup() with os_dupfd_cloexec()
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
Eric Engestrom [Fri, 5 Jun 2020 08:55:35 +0000 (10:55 +0200)]
svga: replace all dup() with os_dupfd_cloexec()
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
Eric Engestrom [Fri, 5 Jun 2020 08:22:47 +0000 (10:22 +0200)]
freedreno: replace all dup() with os_dupfd_cloexec()
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
Eric Engestrom [Fri, 5 Jun 2020 08:22:29 +0000 (10:22 +0200)]
etnaviv: replace all dup() with os_dupfd_cloexec()
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
Eric Engestrom [Fri, 5 Jun 2020 08:22:22 +0000 (10:22 +0200)]
egl: replace all dup() with os_dupfd_cloexec()
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
Eric Engestrom [Fri, 5 Jun 2020 08:55:03 +0000 (10:55 +0200)]
i965: replace all dup() with os_dupfd_cloexec()
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
Eric Engestrom [Fri, 5 Jun 2020 08:54:51 +0000 (10:54 +0200)]
iris: replace all dup() with os_dupfd_cloexec()
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
Eric Engestrom [Fri, 5 Jun 2020 08:54:43 +0000 (10:54 +0200)]
anv: replace all dup() with os_dupfd_cloexec()
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
Eric Engestrom [Fri, 5 Jun 2020 08:22:04 +0000 (10:22 +0200)]
radv: replace all dup() with os_dupfd_cloexec()
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
Eric Engestrom [Fri, 5 Jun 2020 08:55:22 +0000 (10:55 +0200)]
vulkan/wsi: replace all dup() with os_dupfd_cloexec()
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
Eric Engestrom [Thu, 4 Jun 2020 23:09:35 +0000 (01:09 +0200)]
replace all F_DUPFD_CLOEXEC with os_dupfd_cloexec()
All squashed into a single commit because it shouldn't have any
behaviour change, except that it might work now on platforms where it
was broken because F_DUPFD_CLOEXEC is not supported but FD_CLOEXEC is.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
Eric Engestrom [Thu, 4 Jun 2020 23:08:33 +0000 (01:08 +0200)]
util: introduce os_dupfd_cloexec() helper
Adapted from wayland's wl_os_dupfd_cloexec().
Suggested-by: Kristian H. Kristensen <hoegsberg@google.com>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
Eric Engestrom [Fri, 5 Jun 2020 10:39:28 +0000 (12:39 +0200)]
util/os_file: replace broken windows-detection code with detect_os.h
The meson-windows-vs2019 job was going down the `!defined(WIN32)` path,
leading to a broken build once that path contained non-windows code.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
Eric Anholt [Wed, 17 Jun 2020 22:29:31 +0000 (15:29 -0700)]
ci: disable the windows tests until the runner can be stabilized again
I've been getting a stream of errors from Marge today like:
FAILED: src/gallium/drivers/llvmpipe/lp_test_conv.exe
link @src/gallium/drivers/llvmpipe/lp_test_conv.exe.rsp
LINK : fatal error LNK1102: out of memory
[1080/1141] Compiling C object src/gallium/frontends/wgl/
945cc3d@@wgl@sta/stw_getprocaddress.c.obj
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5534>
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