Andreas Sandberg [Fri, 7 Aug 2015 08:59:23 +0000 (09:59 +0100)]
dev: Add a simple DMA engine that can be used by devices
Add a simple DMA engine that sits behind a FIFO. This engine can be
used by devices that need to read large amounts of data (e.g., display
controllers). Most aspects of the controller, such as FIFO size,
maximum number of in-flight accesses, and maximum request sizes can be
configured.
The DMA copies blocks of data into its FIFO. Transfers are initiated
with a call to startFill() command that takes a start address and a
size. Advanced users can create a derived class that overrides the
onEndOfBlock() callback that is triggered when the last request to a
block has been issued. At this point, the DMA engine is ready to start
fetching a new block of data, potentially from a different address
range.
The DMA engine stops issuing new requests while it is draining. Care
must be taken to ensure that devices that are fed by a DMA engine are
suspended while the system is draining to avoid buffer underruns.
Andreas Sandberg [Fri, 7 Aug 2015 08:59:22 +0000 (09:59 +0100)]
sim: Split ClockedObject to make it usable to non-SimObjects
Split ClockedObject into two classes: Clocked that provides the basic
clock functionality, and ClockedObject that inherits from Clocked and
SimObject to provide the functionality of the old ClockedObject.
Andreas Sandberg [Fri, 7 Aug 2015 08:59:19 +0000 (09:59 +0100)]
base: Rewrite the CircleBuf to fix bugs and add serialization
The CircleBuf class has at least one bug causing it to overwrite the
wrong elements when wrapping. The current code has a lot of unused
functionality and duplicated code. This changeset replaces the old
implementation with a new version that supports serialization and
arbitrary types in the buffer (not just char).
Andreas Sandberg [Fri, 7 Aug 2015 08:59:15 +0000 (09:59 +0100)]
dev, x86: Fix serialization bug in the i8042 device
The i8042 device drops the contents of a PS2 device's buffer when
serializing, which results in corrupted PS2 state when continuing
simulation after a checkpoint. This changeset fixes this bug and
transitions the i8042 model to use the new serialization API that
requires the serialize() method to be const.
Andreas Sandberg [Fri, 7 Aug 2015 08:59:14 +0000 (09:59 +0100)]
dev: Make serialization in Sinic constant
This changeset transitions the Sinic device to the new serialization
framework that requires the serialization method to be constant.
Andreas Sandberg [Fri, 7 Aug 2015 08:59:13 +0000 (09:59 +0100)]
base: Declare a type for context IDs
Context IDs used to be declared as ad hoc (usually as int). This
changeset introduces a typedef for ContextIDs and a constant for
invalid context IDs.
Andreas Sandberg [Fri, 7 Aug 2015 08:59:12 +0000 (09:59 +0100)]
base: Use constexpr in Cycles
Declare the constructor and all of the operators that don't change the
state of a Cycles instance as constexpr. This makes it possible to use
Cycles as a static constant and allows the compiler to evaulate simple
expressions at compile time. An unfortunate side-effect of this is
that we cannot use assertions since C++11 doesn't support them in
constexpr functions. As a workaround, we throw an invalid_argument
exception when the assert would have triggered. A nice side-effect of
this is that the compiler will evaluate the "assertion" at compile
time when an expression involving Cycles can be statically evaluated.
Andreas Hansson [Fri, 7 Aug 2015 08:55:38 +0000 (04:55 -0400)]
mem: Remove extraneous acquire/release flags and attributes
This patch removes the extraneous flags and attributes from the
request and packet, and simply leaves the new commands. The change
introduced when adding acquire/release breaks all compatibility with
existing traces, and there is really no need for any new flags and
attributes. The commands should be sufficient.
This patch fixes packet tracing (urgent), and also removes the
unnecessary complexity.
Andreas Sandberg [Wed, 5 Aug 2015 09:27:11 +0000 (10:27 +0100)]
sim: Fixup comments and constness in draining infrastructure
Fix comments that got outdated by the draining rewrite. Also fixup
constness for methods in the querying drain state in the DrainManager.
Andreas Sandberg [Wed, 5 Aug 2015 09:12:12 +0000 (10:12 +0100)]
mem: Fixup incorrect include guards
--HG--
extra : rebase_source :
9dba84eaf9c734a114ecd0940e1d505303644064
Andreas Hansson [Wed, 5 Aug 2015 08:36:31 +0000 (04:36 -0400)]
util: Enable DRAM sweep to print power and efficiency
This patch enhances the functionality of the DRAM sweep script to not
only plot the bandwidth utilisation, but also total power and power
efficiency. To do so, a command-line switch is added, and a bit more
data extracted from the stats.
Andreas Hansson [Wed, 5 Aug 2015 08:36:29 +0000 (04:36 -0400)]
stats: Reflect current behaviour
Not sure what went wrong in the pushing of the Ruby patches, but
somehow these regressions are not updated.
Andreas Sandberg [Tue, 4 Aug 2015 09:31:37 +0000 (10:31 +0100)]
sim: Initialize Drainable::_drainState to the system's state
It is sometimes desirable to be able to instantiate Drainable objects
when the simulator isn't in the Running state. Currently, we always
initialize Drainable objects to the Running state. However, this
confuses many of the sanity checks in the base class since objects
aren't expected to be in the Running state if the system is in the
Draining or Drained state.
Instead of always initializing the state variable in Drainable to
DrainState::Running, initialize it to the state the DrainManager is
in.
Note: This means an object can be created in the Draining/Drained
state without first calling drain().
Andreas Sandberg [Tue, 4 Aug 2015 09:29:13 +0000 (10:29 +0100)]
stats: Update stats for tgen to reflect CommMonitor changes
The name of the stack distance stats changed slightly when the stack
distance calculator was redesigned as a probe. Update the reference
stats to reflect this.
Andreas Sandberg [Tue, 4 Aug 2015 09:29:13 +0000 (10:29 +0100)]
mem: Move trace functionality from the CommMonitor to a probe
This changeset moves the access trace functionality from the
CommMonitor into a separate probe. The probe can be hooked up to any
component that exports probe points of the type ProbePoints::Packet.
This patch moves the dependency on Google's Protocol Buffers library
from the CommMonitor to the MemTraceProbe, which means that the
CommMonitor (including stack distance profiling) no long depends on
it.
Andreas Sandberg [Tue, 4 Aug 2015 09:29:13 +0000 (10:29 +0100)]
mem: Redesign the stack distance calculator as a probe
This changeset removes the stack distance calculator hooks from the
CommMonitor class and implements a stack distance calculator as a
memory system probe instead. The probe can be hooked up to any
component that exports probe points of the type ProbePoints::Packet.
Andreas Sandberg [Tue, 4 Aug 2015 09:29:13 +0000 (10:29 +0100)]
mem: Add probe support to the CommMonitor
This changeset adds a standardized probe point type to monitor packets
in the memory system and adds two probe points to the CommMonitor
class. These probe points enable monitoring of successfully delivered
requests and successfully delivered responses.
Memory system probe listeners should use the BaseMemProbe base class
to provide a unified configuration interface and reuse listener
registration code. Unlike the ProbeListenerObject class, the
BaseMemProbe allows objects to be wired to multiple ProbeManager
instances as long as they use the same probe point name.
Matthias Jung [Tue, 4 Aug 2015 04:08:40 +0000 (23:08 -0500)]
misc: Coupling gem5 with SystemC TLM2.0
Transaction Level Modeling (TLM2.0) is widely used in industry for creating
virtual platforms (IEEE 1666 SystemC). This patch contains a standard compliant
implementation of an external gem5 port, that enables the usage of gem5 as a
TLM initiator component in SystemC based virtual platforms. Both TLM coding
paradigms loosely timed (b_transport) and aproximately timed (nb_transport) are
supported.
Compared to the original patch a TLM memory manager was added. Furthermore, the
transaction object was removed and for each TLM payload a PacketPointer that
points to the original gem5 packet is added as an TLM extension. For event
handling single events are now created.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Timothy Jones [Tue, 4 Aug 2015 04:08:40 +0000 (23:08 -0500)]
sim: function for testing for auto deletion
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Timothy Jones [Tue, 4 Aug 2015 04:08:40 +0000 (23:08 -0500)]
uby: Fix checkpointing and restore
There are 2 problems with the existing checkpoint and restore code in ruby.
The first is that when the event queue is altered by ruby during serialization,
some events that are currently scheduled cannot be found (e.g. the event to
stop simulation that always lives on the queue), causing a panic.
The second is that ruby is sometimes serialized after the memory system,
meaning that the dirty data in its cache is flushed back to memory too late
and so isn't included in the checkpoint.
These are fixed by implementing memory writeback in ruby, using the same
technique of hijacking the event queue, but first descheduling all events that
are currently on it. They are saved, along with their scheduled time, so that
the event queue can be faithfully reconstructed after writeback has finished.
Events with the AutoDelete flag set will delete themselves when they
are descheduled, causing an error when attempting to schedule them again.
This is fixed by simply not recording them when taking them off the queue.
Writeback is still implemented using flushing, so the cache recorder object,
that is created to generate the trace and manage flushing, is kept
around and used during serialization to write the trace to disk.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Tue, 4 Aug 2015 03:44:29 +0000 (22:44 -0500)]
ruby: mesi three level: multiple corrections to the protocol
1. Eliminate state NP in L0 and L1 Caches: The two states 'NP' and 'I' both
mean that the cache block is not present in the cache. 'I' also means that the
cache entry has been allocated. This causes problems when we do not correctly
initialize the cache entry when it is re-used. Hence, this patch eliminates
the state NP altogether. Everytime a new block comes into the cache, a cache
entry is allocated. Everytime a block leaves, the corresponding entry is
deallocated.
2. Separate transient state for instruction fetches: purely for accouting
purposes.
3. Drop state IS_I in L1 Cache and the message type STALE_DATA: when
invalidation is received for a block in IS, the block used to be moved to IS_I.
This meant that the data that would arrive in future would be used but not
stored since the controller lost the permissions after gaining them. This
state is being dropped and now invalidation messages would not processed till
the data has arrived. This also means that STALE_DATA type is not longer
required.
Nilay Vaish [Tue, 4 Aug 2015 03:44:28 +0000 (22:44 -0500)]
ruby: mesi two,three level: copy data only when dirty
The level 2 controller has a bug. In one particular action, the data block was
copied from a message irrespective whether the block is dirty or not. In cases
when L1 sends no data, the data value copied was incorrect.
Nilay Vaish [Tue, 4 Aug 2015 03:44:27 +0000 (22:44 -0500)]
ruby: correctly number the sequencer in MESI_Three_Level.py
Brad Beckmann [Sat, 1 Aug 2015 16:59:47 +0000 (12:59 -0400)]
ruby: removed invalid assert in message comparitor
It is perfectly valid to compare the same message and the greater than
operator should work correctly.
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: improved stall and wait debugging
Added dprintfs and asserts for identifying stall and wait bugs.
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: fix error in conflicing symbol declaration
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: enable overloading in functions not in classes
For many years the slicc symbol table has supported overloaded functions in
external classes. This patch extends that support to functions that are not
part of classes (a.k.a. no parent). For example, this support allows slicc
to understand that mapAddressToRange is overloaded and the NodeID is an
optional parameter.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: change router pipeline stages to 2
This patch changes the router pipeline stages from 4 to 2. The
canonical 4-stage router is conservative while a lower-latency router
with look ahead routing and speculative allocation is well acknowledged.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: change advance_stage for flit_d
Sets m_stage.second to the second parameter of the function.
Then, for every place where advance_stage is called, adds
a cycle to the argument being passed.
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: improved stalling support in protocols
Adds features to allow protocols to reschedule controllers when conditionally
stalling within inport logic or actions. Also insures that resource and
protocol stalls are re-evaluated the next cycle.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: expose access permission to replacement policies
This patch adds support that allows the replacement policy to identify each
cache block's access permission. This information can be useful when making
replacement decisions.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: adds size and empty apis to the msg buffer stallmap
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: fix deadlock bug in banked array resource checks
The Ruby banked array resource checks (initiated from SLICC) did a check and
allocate at the same time. If a transition needs more than one resource, then
it might check/allocate resource #1, then fail to get resource #2. Another
transition might then try to get the same resources, but in reverse order.
Deadlock.
This patch separates resource checking and resource reservation into two
steps to avoid deadlock.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: Fix for stallAndWait bug
It was previously possible for a stalled message to be reordered after an
incomming message. This patch ensures that any stalled message stays in its
original request order.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
config: add base class for ruby controllers
The CntrlBase python class handles configuration parameters such as running
counts of controllers and sequencers.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
mem: add request types for acquire and release
Add support for acquire and release requests. These synchronization operations
are commonly supported by several modern instruction sets.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: allocate a block in CacheMemory without updating LRU state
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: speed up function used for cache walks
This patch adds a few helpful functions that allow .sm files to directly
invalidate all cache blocks using a trigger queue rather than rely on each
individual cache block to be invalidated via requests from the mandatory
queue.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: support for arbitrary DPRINTF flags (not just RubySlicc)
This patch allows DPRINTFs to be used in SLICC state machines similar to how
they are used by the rest of gem5. Previously all DPRINTFs in the .sm files
had to use the RubySlicc flag.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: support for local variable declarations in action blocks
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: initialize replacement policies with their own simobjs
this is in preparation for other replacement policies that take additional
parameters.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: give access to cache tag/data latencies from SLICC
This patch exposes the tag and data array latencies to the SLICC state machines
so that it can be used to determine the correct enqueue latency for response
messages.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: support for multiple cache entry types in the same state machine
To have multiple Entry types (e.g., a cache Entry type and
a directory Entry type), just declare one of them as a secondary
type by using the pair 'main="false"', e.g.:
structure(DirEntry, desc="...", interface="AbstractCacheEntry",
main="false") {
...and the primary type would be declared:
structure(Entry, desc="...", interface="AbstractCacheEntry") {
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: Fix bug in enqueue and peek statements.
These were not generating the correct c names for types declared within a
machine scope.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: fix missing inline function in LocalVariableAST
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: improve support for prefix operations
This patch fixes the type handling when prefix operations are used. Previously
prefix operators would assume a void return type, which made it impossible to
combine prefix operations with other expressions. This patch allows SLICC
programmers to use prefix operations more naturally.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: support for transitions with a wildcard next state
This patches adds support for transitions of the form:
transition(START, EVENTS, *) { ACTIONS }
This allows a machine to collapse states that differ only in the next state
transition to collapse into one, and can help shorten/simplfy some protocols
significantly.
When * is encountered as an end state of a transition, the next state is
determined by calling the machine-specific getNextState function. The next
state is determined before any actions of the transition execute, and
therefore the next state calculation cannot depend on any of the transition
actions.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: support for multiple message types on the same buffer
This patch allows SLICC protocols to use more than one message type with a
message buffer. For example, you can declare two in ports as such:
in_port(ResponseQueue_in, ResponseMsg, responseFromDir, rank=3) { ... }
in_port(tgtResponseQueue_in, TgtResponseMsg, responseFromDir, rank=2) { ... }
Brad Beckmann [Sat, 1 Aug 2015 16:37:52 +0000 (12:37 -0400)]
slicc: fatal->panic on invalid transitions
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
mem: Hit callback delay fix
This patch was created by Bihn Pham during his internship at AMD.
There is no need to delay hit callback response messages by a cycle because
the response latency is already incurred in the Ruby protocol. This ensures
correct timing of memory instructions.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
cpu: Fixed a bug on where to fetch the next instruction from
Figure out if the next instruction to fetch comes from the micro-op ROM
or not. Otherwise, wrong instructions may be fetched.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
x86: x86 instruction-implementation bug fixes
Added explicit data sizes and an opcode type for correct execution.
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
util: added .cl OpenCL extension to file_type.py
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
util: added .mk makefile extension to file_types.py
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: re-added the addressToInt slicc interface function
This helper function is very useful converting address offsets to integers
that can be used for protocol specific destination mapping.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
syscall: Add readlink to x86 with special case /proc/self/exe
This patch implements the correct behavior.
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: add useful dprints to sequencer
Added two data block dprints that are useful when tracking down data check
failures in the ruby random tester.
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
slicc: isinstance bugfix
This fix prevents spurious errors when searching for a symbol that may be
located in one of multiple symbol tables.
Anthony Gutierrez [Sat, 1 Aug 2015 02:53:17 +0000 (22:53 -0400)]
util: add a vimrc that matches gem5 style guide
Andreas Sandberg [Fri, 31 Jul 2015 16:04:59 +0000 (17:04 +0100)]
stats: Update switcheroo reference stats
The Minor draining fixes affect perturb the timing slightly since it
affects how the simulator is drained. Update reference statistics to
reflect this expected change.
Andreas Sandberg [Fri, 31 Jul 2015 16:04:59 +0000 (17:04 +0100)]
cpu: Update debug message from Fetch1 isDrained() in Minor
Fix a spurious %s and include the state of the Fetch1 stage in the
debug printout.
Andreas Sandberg [Fri, 31 Jul 2015 16:04:59 +0000 (17:04 +0100)]
cpu: Fix Minor drain issues when switched out
The Minor CPU currently doesn't drain properly when it is switched
out. This happens because Fetch 1 expects to be in the FetchHalted
state when it is drained. However, because the CPU is switched out, it
is stuck in the FetchWaitingForPC state. Fix this by ignoring drain
requests and returning DrainState::Drained from MinorCPU::drain() if
the CPU is switched out. This is always safe since a switched out CPU,
by definition, doesn't have any instructions in flight.
Andreas Sandberg [Thu, 30 Jul 2015 09:16:36 +0000 (10:16 +0100)]
stats: Bump stats after Minor switcheroo inclusion
Andreas Sandberg [Thu, 30 Jul 2015 09:16:28 +0000 (10:16 +0100)]
tests: Add Minor to the ARM full switcheroo tests
Add the Minor CPU to the RealView and RealView64 full switcheroo
tests.
Andreas Sandberg [Thu, 30 Jul 2015 09:15:50 +0000 (10:15 +0100)]
cpu: Only activate thread 0 in Minor if the CPU is active
Minor currently activates thread 0 in startup() to work around an
issue where activateContext() is called from LiveProcess before the
process entry point is known. When activateContext() is called, Minor
creates a branch instruction to the process's entry point. The first
time it is called, the branch points to an undefined location (0). The
call in startup() updates the branch to point to the actual entry
point.
When instantiating a switched out Minor CPU, it still tries to
activate thread 0. This is clearly incorrect since a switched out CPU
can't have any active threads. This changeset adds a check to ensure
that the thread is active before reactivating it.
Andreas Sandberg [Thu, 30 Jul 2015 09:15:50 +0000 (10:15 +0100)]
cpu: Fix drain issues in the Minor CPU
The drain refactor patches introduced a couple of bugs in the way
Minor handles draining. This patch fixes an incorrect assert and a
case of infinite recursion when the CPU signals drain done.
Andreas Hansson [Thu, 30 Jul 2015 07:42:27 +0000 (03:42 -0400)]
stats: Update stats for clean eviction addition
Andreas Hansson [Thu, 30 Jul 2015 07:42:25 +0000 (03:42 -0400)]
mem: Add missing clean eviction on uncacheable access
This patch adds a missing clean eviction, occuring when an uncacheable
access flushes and invalidates an existing block.
Andreas Hansson [Thu, 30 Jul 2015 07:41:43 +0000 (03:41 -0400)]
mem: Remove unused RequestCause in cache
This patch removes the RequestCause, and also simplifies how we
schedule the sending of packets through the memory-side port. The
deassertion of bus requests is removed as it is not used.
David Guillen-Fandos [Thu, 30 Jul 2015 07:41:42 +0000 (03:41 -0400)]
mem: Make caches way aware
This patch makes cache sets aware of the way number. This enables
some nice features such as the ablity to restrict way allocation. The
implemented mechanism allows to set a maximum way number to be
allocated 'k' which must fulfill 0 < k <= N (where N is the number of
ways). In the future more sophisticated mechasims can be implemented.
Andreas Hansson [Thu, 30 Jul 2015 07:41:40 +0000 (03:41 -0400)]
mem: Transition away from isSupplyExclusive for writebacks
This patch changes how writebacks communicate whether the line is
passed as modified or owned. Previously we relied on the
isSupplyExclusive mechanism, which was originally designed to avoid
unecessary snoops.
For normal cache requests we use the sharedAsserted mechanism to
determine if a block should be marked writeable or not, and with this
patch we transition the writebacks to also use this
mechanism. Conceptually this is cleaner and more consistent.
Andreas Hansson [Thu, 30 Jul 2015 07:41:39 +0000 (03:41 -0400)]
mem: Tidy up CacheBlk class
This patch modernises and tidies up the CacheBlk, removing dead code.
Andreas Hansson [Thu, 30 Jul 2015 07:41:38 +0000 (03:41 -0400)]
mem: Tidy up packet
Some minor fixes and removal of dead code. Changing the flags to be
enums rather than static const (to avoid any linking issues caused by
the latter). Also adding a getBlockAddr member which hopefully can
slowly finds its way into caches, snoop filters etc.
Andreas Hansson [Thu, 30 Jul 2015 07:41:36 +0000 (03:41 -0400)]
stats: Bump stats to match current behaviour
Somehow this one seems to have slipped through. Perhaps
non-determinism somewhere?
Andreas Hansson [Thu, 30 Jul 2015 07:41:22 +0000 (03:41 -0400)]
cpu: Fix issue identified by UBSan
Nilay Vaish [Tue, 28 Jul 2015 06:58:04 +0000 (01:58 -0500)]
Nilay Vaish [Sun, 26 Jul 2015 15:21:20 +0000 (10:21 -0500)]
cpu: implements vector registers
This adds a vector register type. The type is defined as a std::array of a
fixed number of uint64_ts. The isa_parser.py has been modified to parse vector
register operands and generate the required code. Different cpus have vector
register files now.
Nilay Vaish [Sun, 26 Jul 2015 15:20:07 +0000 (10:20 -0500)]
cpu: o3: slight correction to identation in rename_impl.hh
Brandon Potter [Fri, 24 Jul 2015 19:25:23 +0000 (12:25 -0700)]
style: change Process function calls to use camelCase
The Process class methods were using an improper style and this subsequently
bled into the system call code. The following regular expressions should be
helpful if someone transitions private system call patches on top of these
changesets:
s/alloc_fd/allocFD/
s/sim_fd(/simFD(/
s/sim_fd_obj/getFDEntry/
s/fix_file_offsets/fixFileOffsets/
s/find_file_offsets/findFileOffsets/
Brandon Potter [Fri, 24 Jul 2015 19:25:23 +0000 (12:25 -0700)]
syscall_emul: standardized file descriptor name and add return checks.
The patch clarifies whether file descriptors are host file descriptors or
target file descriptors in the system call code. (Host file descriptors
are file descriptors which have been allocated through real system calls
where target file descriptors are allocated from an array in the Process
class.)
Brandon Potter [Fri, 24 Jul 2015 19:25:22 +0000 (12:25 -0700)]
base: refactor process class (specifically FdMap and friends)
This patch extends the previous patch's alterations around fd_map. It cleans
up some of the uglier code in the process file and replaces it with a more
concise C++11 version. As part of the changes, the FdMap class is pulled out
of the Process class and receives its own file.
Brandon Potter [Fri, 24 Jul 2015 19:25:22 +0000 (12:25 -0700)]
syscall_emul: file descriptor interface changes
This patch gets rid of unused Process::dup_fd method and does minor
refactoring in the process class files. The file descriptor max has been
changed to be the number of file descriptors since this clarifies the loop
boundary condition and cleans up the code a bit. The fd_map field has been
altered to be dynamically allocated as opposed to being an array; the
intention here is to build on this is subsequent patches to allow processes
to share their file descriptors with the clone system call.
Brandon Potter [Fri, 24 Jul 2015 19:25:22 +0000 (12:25 -0700)]
ruby: dma sequencer: removes redundant code
Nilay Vaish [Wed, 22 Jul 2015 16:20:07 +0000 (11:20 -0500)]
ruby: network: NetworkLink inherits from Consumer now.
Nilay Vaish [Tue, 21 Jul 2015 15:08:25 +0000 (10:08 -0500)]
configs: network test: remove redundant physical memory
Nilay Vaish [Sat, 18 Jul 2015 20:07:35 +0000 (15:07 -0500)]
stats: x86: updates due to patch on vex
Nilay Vaish [Fri, 17 Jul 2015 16:31:22 +0000 (11:31 -0500)]
x86: decode instructions with vex prefix
This patch updates the x86 decoder so that it can decode instructions with vex
prefix. It also updates the isa with opcodes from vex opcode maps 1, 2 and 3.
Note that none of the instructions have been implemented yet. The
implementations would be provided in due course of time.
Gabor Dozsa [Thu, 16 Jul 2015 00:53:50 +0000 (19:53 -0500)]
dev: add support for multi gem5 runs
Multi gem5 is an extension to gem5 to enable parallel simulation of a
distributed system (e.g. simulation of a pool of machines
connected by Ethernet links). A multi gem5 run consists of seperate gem5
processes running in parallel (potentially on different hosts/slots on
a cluster). Each gem5 process executes the simulation of a component of the
simulated distributed system (e.g. a multi-core board with an Ethernet NIC).
The patch implements the "distributed" Ethernet link device
(dev/src/multi_etherlink.[hh.cc]). This device will send/receive
(simulated) Ethernet packets to/from peer gem5 processes. The interface
to talk to the peer gem5 processes is defined in dev/src/multi_iface.hh and
in tcp_iface.hh.
There is also a central message server process (util/multi/tcp_server.[hh,cc])
which acts like an Ethernet switch and transfers messages among the gem5 peers.
A multi gem5 simulations can be kicked off by the util/multi/gem5-multi.sh
wrapper script.
Checkpoints are supported by multi-gem5. The checkpoint must be
initiated by a single gem5 process. E.g., the gem5 process with rank 0
can take a checkpoint from the bootscript just before it invokes
'mpirun' to launch an MPI test. The message server process will notify
all the other peer gem5 processes and make them take a checkpoint, too
(after completing a global synchronisation to ensure that there are no
inflight messages among gem5).
Andreas Hansson [Mon, 13 Jul 2015 12:46:28 +0000 (08:46 -0400)]
mem: Fix (ab)use of emplace to avoid temporary object creation
Andreas Hansson [Mon, 13 Jul 2015 12:46:16 +0000 (08:46 -0400)]
mem: Updated DRAMSim2 wrapper to new drain API
Somehow this one slipped through without being updated.
Brandon Potter [Fri, 10 Jul 2015 21:05:24 +0000 (16:05 -0500)]
ruby: replace global g_abs_controls with per-RubySystem var
This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.
The list of abstract controllers is per-RubySystem and should be
represented that way, rather than as a global.
Since this is the last remaining Ruby global variable, the
src/mem/ruby/Common/Global.* files are also removed.
Brandon Potter [Fri, 10 Jul 2015 21:05:23 +0000 (16:05 -0500)]
ruby: replace global g_system_ptr with per-object pointers
This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.
With possibly multiple RubySystem objects, we can no longer use a global
variable to find "the" RubySystem object. Instead, each Ruby component
has to carry a pointer to the RubySystem object to which it belongs.
Brandon Potter [Fri, 10 Jul 2015 21:05:23 +0000 (16:05 -0500)]
ruby: replace g_ruby_start with per-RubySystem m_start_cycle
This patch begins the process of removing global variables from the Ruby
source with the goal of eventually allowing users to create multiple Ruby
instances in a single simulation. Currently, users cannot do so because
several global variables and static members are referenced by the RubySystem
object in a way that assumes that there will only ever be a single RubySystem.
These need to be replaced with per-RubySystem equivalents.
This specific patch replaces the global var g_ruby_start, which is used
to calculate throughput statistics for Throttles in simple networks and
links in Garnet networks, with a RubySystem instance var m_start_cycle.
Brandon Potter [Fri, 10 Jul 2015 21:05:23 +0000 (16:05 -0500)]
ruby: remove extra whitespace and correct misspelled words
Andreas Sandberg [Tue, 7 Jul 2015 09:03:14 +0000 (10:03 +0100)]
dev, arm: Add a device model that uses the NoMali model
Add a simple device shim that interfaces with the NoMali model
library. The gem5 side of the interface supports Mali T60x/T62x/T760
GPUs. This device model pretends to be a Mali GPU, but doesn't render
anything and executes in zero time.
Andreas Sandberg [Tue, 7 Jul 2015 09:03:13 +0000 (10:03 +0100)]
ext: Add the NoMali GPU no-simulation library
Add revision
9adf9d6e2d889a483a92136c96eb8a434d360561 of NoMali-model
from https://github.com/ARM-software/nomali-model. This library
implements the register interface of the Mali T6xx/T7xx series GPUs,
but doesn't do any rendering. It can be used to hide the effects of
software rendering.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:05 +0000 (09:51 +0100)]
stats: Update pc-switcheroo stats
The pc-switcheroo test cases has slightly different timing after
decoupling draining from the SimObject hierarchy. This is expected
since objects aren't drained in the exact same order as before.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:05 +0000 (09:51 +0100)]
sim: Refactor and simplify the drain API
The drain() call currently passes around a DrainManager pointer, which
is now completely pointless since there is only ever one global
DrainManager in the system. It also contains vestiges from the time
when SimObjects had to keep track of their child objects that needed
draining.
This changeset moves all of the DrainState handling to the Drainable
base class and changes the drain() and drainResume() calls to reflect
this. Particularly, the drain() call has been updated to take no
parameters (the DrainManager argument isn't needed) and return a
DrainState instead of an unsigned integer (there is no point returning
anything other than 0 or 1 any more). Drainable objects should return
either DrainState::Draining (equivalent to returning 1 in the old
system) if they need more time to drain or DrainState::Drained
(equivalent to returning 0 in the old system) if they are already in a
consistent state. Returning DrainState::Running is considered an
error.
Drain done signalling is now done through the signalDrainDone() method
in the Drainable class instead of using the DrainManager directly. The
new call checks if the state of the object is DrainState::Draining
before notifying the drain manager. This means that it is safe to call
signalDrainDone() without first checking if the simulator has
requested draining. The intention here is to reduce the code needed to
implement draining in simple objects.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:05 +0000 (09:51 +0100)]
sim: Decouple draining from the SimObject hierarchy
Draining is currently done by traversing the SimObject graph and
calling drain()/drainResume() on the SimObjects. This is not ideal
when non-SimObjects (e.g., ports) need draining since this means that
SimObjects owning those objects need to be aware of this.
This changeset moves the responsibility for finding objects that need
draining from SimObjects and the Python-side of the simulator to the
DrainManager. The DrainManager now maintains a set of all objects that
need draining. To reduce the overhead in classes owning non-SimObjects
that need draining, objects inheriting from Drainable now
automatically register with the DrainManager. If such an object is
destroyed, it is automatically unregistered. This means that drain()
and drainResume() should never be called directly on a Drainable
object.
While implementing the new functionality, the DrainManager has now
been made thread safe. In practice, this means that it takes a lock
whenever it manipulates the set of Drainable objects since SimObjects
in different threads may create Drainable objects
dynamically. Similarly, the drain counter is now an atomic_uint, which
ensures that it is manipulated correctly when objects signal that they
are done draining.
A nice side effect of these changes is that it makes the drain state
changes stricter, which the simulation scripts can exploit to avoid
redundant drains.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:04 +0000 (09:51 +0100)]
sim: Move mem(Writeback|Invalidate) to SimObject
The memWriteback() and memInvalidate() calls used to live in the
Serializable interface. In this series of patches, the Serializable
interface will be redesigned to make serialization independent of the
object graph and always work on the entire simulator. This means that
the Serialization interface won't be useful to perform maintenance of
the caches in a sub-graph of the entire SimObject graph. This
changeset moves these memory maintenance methods to the SimObject
interface instead.