Clifford Wolf [Mon, 22 Apr 2019 07:03:11 +0000 (09:03 +0200)]
Re-added clean after techmap in synth_xilinx
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 22 Apr 2019 07:01:00 +0000 (09:01 +0200)]
Merge pull request #916 from YosysHQ/map_cells_before_map_luts
synth_xilinx to map_cells before map_luts
Clifford Wolf [Mon, 22 Apr 2019 06:58:09 +0000 (08:58 +0200)]
Merge pull request #911 from mmicko/gowin-nobram
Make nobram false by default for gowin
Clifford Wolf [Mon, 22 Apr 2019 06:51:34 +0000 (08:51 +0200)]
Merge pull request #909 from zachjs/master
support repeat loops with constant repeat counts outside of constant functions
Clifford Wolf [Mon, 22 Apr 2019 06:39:37 +0000 (08:39 +0200)]
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx
Add pmux2shiftx command
Clifford Wolf [Mon, 22 Apr 2019 06:38:52 +0000 (08:38 +0200)]
Merge pull request #945 from YosysHQ/clifford/libwb
New behavior for read_verilog handling of whiteboxes
Clifford Wolf [Mon, 22 Apr 2019 00:07:36 +0000 (02:07 +0200)]
Disable blackbox detection in techmap files
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Sun, 21 Apr 2019 21:24:50 +0000 (14:24 -0700)]
Merge branch 'master' into map_cells_before_map_luts
Clifford Wolf [Sun, 21 Apr 2019 09:40:20 +0000 (11:40 +0200)]
Fix tests
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 21 Apr 2019 09:40:09 +0000 (11:40 +0200)]
Add "noblackbox" attribute
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 20 Apr 2019 20:24:50 +0000 (22:24 +0200)]
New behavior for front-end handling of whiteboxes
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 20 Apr 2019 18:51:54 +0000 (20:51 +0200)]
Merge pull request #943 from YosysHQ/clifford/whitebox
[WIP] Add "whitebox" attribute, add "read_verilog -wb"
Clifford Wolf [Sat, 20 Apr 2019 16:13:37 +0000 (18:13 +0200)]
Auto-initialize OnehotDatabase on-demand in pmux2shiftx.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 20 Apr 2019 15:52:16 +0000 (17:52 +0200)]
Add "onehot" pass, improve "pmux2shiftx" onehot handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 20 Apr 2019 09:23:24 +0000 (11:23 +0200)]
Add "techmap -wb", use in formal flows
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 20 Apr 2019 09:10:05 +0000 (11:10 +0200)]
Check blackbox attribute in techmap/simplemap
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 20 Apr 2019 09:04:46 +0000 (11:04 +0200)]
Add "wbflip" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 20 Apr 2019 08:05:35 +0000 (10:05 +0200)]
Merge pull request #942 from YosysHQ/clifford/fix931
Improve proc full_case detection and handling
Clifford Wolf [Sat, 20 Apr 2019 00:03:44 +0000 (02:03 +0200)]
Improve "pmux2shiftx"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 19 Apr 2019 23:18:07 +0000 (01:18 +0200)]
Fix some typos
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 19 Apr 2019 23:15:48 +0000 (01:15 +0200)]
Improvements in "pmux2shiftx"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 19 Apr 2019 21:37:11 +0000 (23:37 +0200)]
Improvements in pmux2shiftx
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 19 Apr 2019 18:23:09 +0000 (20:23 +0200)]
Add test for pmux2shiftx
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 19 Apr 2019 18:20:08 +0000 (20:20 +0200)]
Improve pmux2shift ctrl permutation finder
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 19 Apr 2019 16:10:12 +0000 (18:10 +0200)]
Complete rewrite of pmux2shiftx
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 19 Apr 2019 12:03:05 +0000 (14:03 +0200)]
Import initial pmux2shiftx from eddieh
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 19 Apr 2019 22:37:43 +0000 (00:37 +0200)]
Improve "show" handling of 0/1/X/Z padding
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 19 Apr 2019 19:17:12 +0000 (21:17 +0200)]
Change "ne" to "neq" in btor2 output
we need to do this because they changed the parser:
https://github.com/Boolector/btor2tools/commit/
e97fc9cedabadeec4f621de22096e514f862c690
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 19 Apr 2019 12:04:12 +0000 (14:04 +0200)]
Add tests/aiger/.gitignore
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Thu, 11 Apr 2019 22:09:13 +0000 (15:09 -0700)]
Spelling fixes
Eddie Hung [Fri, 19 Apr 2019 06:05:59 +0000 (23:05 -0700)]
Revert "write_json to not write contents (cells/wires) of whiteboxes"
This reverts commit
4ef03e19a8eafc324d3442f0642abf858071fdd4.
Clifford Wolf [Thu, 18 Apr 2019 16:51:36 +0000 (18:51 +0200)]
Update to ABC
3709744
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Thu, 18 Apr 2019 17:56:41 +0000 (10:56 -0700)]
Merge pull request #917 from YosysHQ/eddie/fix_retime
Retime by default when abc -dff
Eddie Hung [Thu, 18 Apr 2019 17:30:45 +0000 (10:30 -0700)]
write_json to not write contents (cells/wires) of whiteboxes
Eddie Hung [Thu, 18 Apr 2019 17:19:45 +0000 (10:19 -0700)]
Ignore 'whitebox' attr in flatten with "-wb" option
Eddie Hung [Thu, 18 Apr 2019 16:55:03 +0000 (09:55 -0700)]
Fix abc's remap_name to not ignore [^0-9] when extracting sid
Eddie Hung [Thu, 18 Apr 2019 15:46:41 +0000 (08:46 -0700)]
ABC to call retime all the time
Clifford Wolf [Thu, 18 Apr 2019 15:42:12 +0000 (17:42 +0200)]
Add "whitebox" attribute, add "read_verilog -wb"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Thu, 18 Apr 2019 14:59:16 +0000 (07:59 -0700)]
Revert "synth_* with -retime option now calls abc with -D 1 as well"
This reverts commit
9a6da9a79a22e984ee3eec02caa230b66f10e11a.
Eddie Hung [Thu, 18 Apr 2019 14:57:17 +0000 (07:57 -0700)]
Merge branch 'master' into eddie/fix_retime
Clifford Wolf [Thu, 18 Apr 2019 13:07:43 +0000 (15:07 +0200)]
Improve proc full_case detection and handling, fixes #931
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 17 Apr 2019 11:51:34 +0000 (13:51 +0200)]
Update to ABC
d1b6413
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Tue, 16 Apr 2019 18:59:21 +0000 (11:59 -0700)]
Merge pull request #939 from YosysHQ/revert895
Revert #895 (mux-to-shiftx optimisation)
Eddie Hung [Tue, 16 Apr 2019 18:07:51 +0000 (11:07 -0700)]
Revert #895
Eddie Hung [Tue, 16 Apr 2019 01:39:20 +0000 (18:39 -0700)]
Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch
Revert "Recognise default entry in case even if all cases covered (fix for #931)"
Eddie Hung [Tue, 16 Apr 2019 00:52:45 +0000 (17:52 -0700)]
Revert "Recognise default entry in case even if all cases covered (fix for #931)"
Eddie Hung [Mon, 15 Apr 2019 19:22:05 +0000 (12:22 -0700)]
Merge pull request #936 from YosysHQ/README-fix-quotes
README: fix some incorrect quoting
whitequark [Mon, 15 Apr 2019 14:29:46 +0000 (14:29 +0000)]
README: fix some incorrect quoting.
Eddie Hung [Fri, 12 Apr 2019 18:52:45 +0000 (11:52 -0700)]
Merge pull request #928 from litghost/add_xc7_sim_models
Add additional cells sim models for core 7-series primitives.
Keith Rothman [Fri, 12 Apr 2019 16:30:49 +0000 (09:30 -0700)]
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Clifford Wolf [Fri, 12 Apr 2019 12:57:36 +0000 (14:57 +0200)]
Merge pull request #933 from dh73/master
Fixing issues in CycloneV cell sim
Clifford Wolf [Fri, 12 Apr 2019 12:57:01 +0000 (14:57 +0200)]
Merge pull request #932 from YosysHQ/eddie/fixdlatch
Recognise default entry in case even if all cases covered (fix for #931)
Diego [Fri, 12 Apr 2019 00:59:03 +0000 (19:59 -0500)]
Fixing issues in CycloneV cell sim
Eddie Hung [Thu, 11 Apr 2019 22:03:40 +0000 (15:03 -0700)]
Add default entry to testcase
Eddie Hung [Thu, 11 Apr 2019 19:34:51 +0000 (12:34 -0700)]
Recognise default entry in case even if all cases covered (#931)
Eddie Hung [Wed, 10 Apr 2019 15:32:53 +0000 (08:32 -0700)]
synth_* with -retime option now calls abc with -D 1 as well
Eddie Hung [Wed, 10 Apr 2019 15:31:40 +0000 (08:31 -0700)]
Revert "abc -dff now implies "-D 0" otherwise retiming doesn't happen"
This reverts commit
19271bd996a79cb4be1db658fcf18227ee0a1dff.
Eddie Hung [Wed, 10 Apr 2019 15:31:35 +0000 (08:31 -0700)]
Revert ""&nf -D 0" fails => use "-D 1" instead"
This reverts commit
3c253818cab2013dc4db55732d3e21cfa0dc3f19.
Eddie Hung [Wed, 10 Apr 2019 15:23:00 +0000 (08:23 -0700)]
Merge remote-tracking branch 'origin/master' into eddie/fix_retime
Keith Rothman [Tue, 9 Apr 2019 18:43:19 +0000 (11:43 -0700)]
Fix LUT6_2 definition.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Zachary Snow [Tue, 9 Apr 2019 16:28:32 +0000 (12:28 -0400)]
support repeat loops with constant repeat counts outside of constant functions
Keith Rothman [Tue, 9 Apr 2019 16:01:53 +0000 (09:01 -0700)]
Add additional cells sim models for core 7-series primatives.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Eddie Hung [Mon, 8 Apr 2019 23:46:33 +0000 (16:46 -0700)]
Fix a few typos
Clifford Wolf [Mon, 8 Apr 2019 19:14:05 +0000 (21:14 +0200)]
Merge pull request #919 from YosysHQ/multiport_transp
memory_bram: Fix multiport make_transp
David Shah [Sun, 7 Apr 2019 15:56:31 +0000 (16:56 +0100)]
memory_bram: Fix multiport make_transp
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Fri, 5 Apr 2019 23:28:46 +0000 (16:28 -0700)]
Add retime test
Eddie Hung [Fri, 5 Apr 2019 23:28:14 +0000 (16:28 -0700)]
Fix S0 -> S1
Eddie Hung [Fri, 5 Apr 2019 22:39:05 +0000 (15:39 -0700)]
Move techamp t:$_DFF_?N? to before abc call
Eddie Hung [Fri, 5 Apr 2019 22:31:54 +0000 (15:31 -0700)]
Retry
Eddie Hung [Fri, 5 Apr 2019 22:30:19 +0000 (15:30 -0700)]
"&nf -D 0" fails => use "-D 1" instead
Eddie Hung [Fri, 5 Apr 2019 22:15:13 +0000 (15:15 -0700)]
Resolve @daveshah1 comment, update synth_xilinx help
Eddie Hung [Fri, 5 Apr 2019 21:43:06 +0000 (14:43 -0700)]
synth_xilinx to techmap FFs after abc call, otherwise -retime fails
Eddie Hung [Fri, 5 Apr 2019 21:42:25 +0000 (14:42 -0700)]
abc -dff now implies "-D 0" otherwise retiming doesn't happen
Clifford Wolf [Fri, 5 Apr 2019 15:31:49 +0000 (17:31 +0200)]
Add "read_ilang -lib"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 4 Apr 2019 16:10:10 +0000 (18:10 +0200)]
Added missing argument checking to "mutate" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Thu, 4 Apr 2019 15:13:10 +0000 (08:13 -0700)]
Missing techmap entry in help
Eddie Hung [Thu, 4 Apr 2019 14:48:13 +0000 (07:48 -0700)]
synth_xilinx to map_cells before map_luts
Eddie Hung [Wed, 3 Apr 2019 13:27:41 +0000 (06:27 -0700)]
Merge pull request #913 from smunaut/fix_proc_mux
proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
Sylvain Munaut [Wed, 3 Apr 2019 12:50:12 +0000 (14:50 +0200)]
proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
last_mux_cell can be NULL ...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Clifford Wolf [Wed, 3 Apr 2019 08:00:18 +0000 (10:00 +0200)]
Merge pull request #912 from YosysHQ/bram_addr_en
memory_bram: Consider read enable for address expansion register
Clifford Wolf [Wed, 3 Apr 2019 07:59:11 +0000 (09:59 +0200)]
Merge pull request #910 from ucb-bar/memupdates
Refine memory support to deal with general Verilog memory definitions.
David Shah [Tue, 2 Apr 2019 18:47:50 +0000 (19:47 +0100)]
memory_bram: Consider read enable for address expansion register
Signed-off-by: David Shah <dave@ds0.me>
Miodrag Milanovic [Tue, 2 Apr 2019 17:21:01 +0000 (19:21 +0200)]
Make nobram false by default for gowin
Eddie Hung [Tue, 2 Apr 2019 07:16:14 +0000 (00:16 -0700)]
Merge pull request #895 from YosysHQ/pmux2shiftx
RFC: Add a pmux-to-shiftx optimisation to proc_mux
Jim Lawson [Mon, 1 Apr 2019 22:02:12 +0000 (15:02 -0700)]
Refine memory support to deal with general Verilog memory definitions.
Clifford Wolf [Fri, 29 Mar 2019 23:09:42 +0000 (00:09 +0100)]
Merge pull request #907 from YosysHQ/clifford/fix906
Build Verilog parser with -DYYMAXDEPTH=100000
Clifford Wolf [Fri, 29 Mar 2019 15:32:44 +0000 (16:32 +0100)]
Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 28 Mar 2019 08:32:05 +0000 (09:32 +0100)]
Merge pull request #901 from trcwm/libertyfixes
Libertyfixes: accept superfluous ; at end of group.
Clifford Wolf [Thu, 28 Mar 2019 08:30:48 +0000 (09:30 +0100)]
Merge pull request #903 from YosysHQ/bram_reset_transp
memory_bram: Reset make_transp when growing read ports
David Shah [Wed, 27 Mar 2019 17:19:14 +0000 (17:19 +0000)]
memory_bram: Reset make_transp when growing read ports
Signed-off-by: David Shah <dave@ds0.me>
Niels Moseley [Wed, 27 Mar 2019 14:17:58 +0000 (15:17 +0100)]
Liberty file parser now accepts superfluous ;
Niels Moseley [Wed, 27 Mar 2019 14:16:19 +0000 (15:16 +0100)]
Liberty file parser now accepts superfluous ;
Niels Moseley [Wed, 27 Mar 2019 14:15:53 +0000 (15:15 +0100)]
Liberty file parser now accepts superfluous ;
Clifford Wolf [Wed, 27 Mar 2019 13:03:35 +0000 (14:03 +0100)]
Add "read -verific" and "read -noverific"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 27 Mar 2019 12:47:42 +0000 (13:47 +0100)]
Add "rename -output"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 27 Mar 2019 12:33:26 +0000 (13:33 +0100)]
Improve "rename" help message
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 26 Mar 2019 15:01:14 +0000 (16:01 +0100)]
Add "cutpoint -undef"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 26 Mar 2019 13:51:35 +0000 (14:51 +0100)]
Add "hdlname" attribute
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 26 Mar 2019 13:17:46 +0000 (14:17 +0100)]
Fix "verific -extnets" for more complex situations
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 25 Mar 2019 18:49:00 +0000 (19:49 +0100)]
Add "cutpoint" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>